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一个DDR时钟差分线设置为T型走线,但是连上线后,出现DRC错误。
9 `" C" J! `) _* W- s2 w" z' u请教一下,是哪里出错了呢,正确的走线方式又是怎么样的呢?, m7 u6 a, h" @+ i2 Z+ ]( F. L
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错误如下:
( |2 K) T; {1 ?4 ^LISTING: 1 element(s)
& W5 V! F. K6 z: g0 ^1 e; y4 b
0 w% L4 _$ R% ~1 h: K: j < DRC ERROR >: m- z( p% ?9 B- K4 Z
4 O3 G4 o D/ [- s Class: DRC ERROR CLASS$ g3 n5 ~0 C+ `5 L2 W
Subclass: ALL
: `1 \5 r+ A# Y4 E* A [ Origin xy: (-772.35 1153.00)
2 F0 b6 h9 Z- W! b* p* i& |# g q Constraint: Net Schedule Topology
^0 X g8 L& k2 ] Constraint Set: ECS2. h4 B2 m4 x, ?; R. D
Constraint Type: NET ELECTRICAL CONSTRAINTS
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Constraint value: VERIFY
& Q1 E% w1 e" q* Q' x4 I Actual value: DOES NOT VERIFY: q- g5 r. Y1 M8 x2 N
# N& q+ Y; X/ h0 D
- - - - - - - - - - - - - - - - - - - -0 r7 m4 z l% E. H L/ Q. Z* f
Element type: SYMBOL PIN: k3 G- `4 ^8 w X! P3 p: I
Class: PIN
9 E5 ]% @/ Z# j/ g2 `0 c- k/ C p8 J a; Q) q2 W o( S
PIN: C254.1
6 H4 Y1 l) d0 e& q; _. e9 y pinuse: UNSPEC# Z9 n7 n P j- P
location-xy: (-772.35 1153.00)
$ H8 o: K- Y3 q5 ]& Q$ t# g part of net name: DSCK#$ k5 f% ^. @9 f# f) L: ~
- - - - - - - - - - - - - - - - - - - -
3 P, x: \: ~6 n0 k' |0 E Element type: RATSNEST TPOINT: O% n/ n- `( Z* t5 {9 D/ ~
Class: DRC ERROR CLASS9 M& E% n( V ^7 v B
Subclass: TOP
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5 b' M, i1 M& K0 D" x9 o9 \ Name: DSCK#.T.1; N' m1 B' D7 j8 V
8 y6 o9 y5 E) H (-745.00 970.00)) p# d5 m5 ?+ q. M+ {2 o
1 K* ]3 ^+ y6 a' g* ?1 G
- - - - - - - - - - - - - - - - - - - -3 \/ X+ Q. f: w) p: O
4 B6 ~( U# t6 V& z1 z
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