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本帖最后由 zgyzgy 于 2015-3-15 14:42 编辑 ' X$ q/ B. q% q9 L" h; F
6 X/ j( v9 a/ zDATE: 03-13-2015 HOTFIX VERSION: 0456 f& D% ~$ U0 ~ }/ d3 F
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1308671 concept_HDL PDF Pivotal symbol on Hierarchical Split Symbol bodies needs to be hidden in the generated PDF
# p+ p/ E* X# k7 H, O. B1349899 Pspice NETLISTER PSpice: Getting different simulation results in versions 16.5 and 16.6
: k3 X$ C9 v( I; y0 l, e1355271 FSP DE-HDL_SCHEMATIC FSP generating incorrect connectivity information in HDL' w3 U3 Z; a, |& F
1370402 ADW TDA TDO does not use the specified name for creating the local work area." p& ^, Y* l; L1 d' u
1371281 CONCEPT_HDL CONSTRAINT_MGR It takes 10 minutes to launch Constraint Manager. C3 f' c4 Y' e
1372480 CONCEPT_HDL CORE How do I get ASA to recognize changes made to a schematic block?4 J3 V" \3 e2 y! \ {" f4 A1 \
1372939 CONCEPT_HDL CORE Save Hierarchy and Save All do not resolve the duplicate refdes issue in a SIZEd part
7 |; T* ?0 ]! J0 Y& O, D1375265 ASI_SI OTHER allegro Sigrity SI to XtractIM translation failed with a workspace file opening error
% L5 P' V1 I- W& D1 Q' N1 J* S% j Q1376225 SIP_LAYOUT DIE_ABSTRACT_IF 'Refresh co-design die' operation fails with "incorrect number of ETCH subclasses defined" message1 X% u- K8 d/ S7 u3 r
1376644 ALLEGRO_EDITOR mentor Command line mbs2brd still needs SI licenses
, m/ i( S* B6 C9 n6 O0 V4 i9 E1376846 SIP_LAYOUT IC_IO_EDITING Running the Show IC Details command generates a drawing/symbol extents error, then SiP crashes
; X9 L' i3 A( W! u1377297 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes when using the Remove Tuning command: s7 t/ `+ o6 m/ x
1377587 CONCEPT_HDL MARKERS The marker file cannot be loaded using the console command "_! markers load <filename.mkr>".
. ^2 N* A# |0 u8 x1377711 TRANSLATOR SPDLINKS Unable to open an MCM file in XtractIM from APD
# G, @8 G/ Y. ]7 y5 N1377962 CONCEPT_HDL CORE If an instantiated part is removed from the library, DE-HDL hangs while reading the .xcon file( s1 Y( h0 w* q; K: t
1378032 ALLEGRO_EDITOR REPORTS Report command and batch mode give different Waived DRC Report results in PCB Editor7 V6 L4 n8 j- h. M
1379797 F2B PACKAGERXL Connections are missing in the generated netlist* N7 L t/ h4 H3 `* l* E; R+ k
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