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发表于 2014-11-16 10:34
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DATE: 11-14-2014 HOTFIX VERSION: 039
: J3 t. z5 X! ~6 q6 @' Q===================================================================================================================================% e# U0 o3 f. G" P* x
CCRID PRODUCT PRODUCTLEVEL2 TITLE' L% N; c- L& D9 |8 G
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1213239 FLOWS PROJMGR SPI_ERROR: Missing closing quote at line 41 in""
/ t2 x. n. r7 p* X+ \5 y# j M% T# e1301262 SPIF OTHER When creating .dsn file for designs containing netclasses with net groups, PCB Editor stops responding.
/ M6 q9 X( n. d1301469 CONCEPT_HDL CORE DE-HDL Import Design - Need a directive to enable the "Retain Hard Packaging Information" option by default
4 z: ~: T4 f3 w1309535 SYSTEMSI ENG_PBA PA5700: Cannot print, save, or post process SI analysis reports
# w D# B* x- T) o$ z% y7 Y1317019 SIG_INTEGRITY LIBRARY Buffer model for pins not changing correctly when multiple DML files are present in working directory.
7 M& p% x6 h d- h) `1318452 ALLEGRO_EDITOR DATABASE Derive Connectivity does not update connections; DRC errors thrown
# t3 X+ g! K0 i1 e7 o+ j( a1318610 CONCEPT_HDL CORE DE-HDL does not re-validate/re-read DML files on disk upon launching Constraint Manager
w+ M1 K/ G( F8 l. Y" x1320997 CAPTURE SCHEMATIC_EDITOR Copy paste of multiple images are stacked in same place.
/ Y1 }* y# Z& f, {1321377 FSP GUI FSP crashes while performing copy-paste operations between different arrays in the Rule text editor! ?8 ]4 _ _2 y. }8 `9 `
1321513 ALLEGRO_EDITOR SYMBOL Preview not available for DRA
# E! g2 M7 W1 j1 O' A, f/ F1324479 ALLEGRO_EDITOR OTHER Option specified in license_packages_allegro.txt file but missing in license server causes Segmentation fault on LINUX) ]( w, C% k" o# \3 w. G& M
1327962 FSP MODEL_EDITOR Need ability to select multiple pins in the Preview area of Rule Editor1 L2 D" B+ V! w8 G9 A. S, }
1328633 CONCEPT_HDL CORE On running Save All, changes were partially saved before DE-HDL crashed. j4 |: A* }, ?5 T) L! m+ R
1328921 ALLEGRO_EDITOR DATABASE Running Derive Connectivity followed by Database Check throws SPMHUT-17 error
& r1 ^' V3 {* i1 H# S* R$ ?! k1330029 CONCEPT_HDL CORE PIN_TYPE and PINUSE attributes not updated consistently in DE-HDL design
; j; V! K# b# N8 I- t* N* r1330580 SIP_LAYOUT SYMB_EDIT_APPMOD When adding a pin using the Symbol Editor the Pin Name is being changed if duplicated
- g( W# h3 G, J+ y, F4 R4 ]3 s1331028 CONCEPT_HDL CHECKPLUS Rules Checker fails on DE-HDL component.
0 ]1 n# H) m5 D8 C1331051 ALLEGRO_EDITOR INTERFACES Soldermask layer is mapped to both Soldermask solderPaste and Miscellaneous Image Layers columns using IPC-2581B F; ^8 G$ P" _% d( b9 ^, j: J
1333127 CONCEPT_HDL CORE Sheet number in the new window is only the block-level number and not the design-level number! R; w3 @; t/ }: P( M; E0 _8 [
1333591 SIP_LAYOUT SKILL Difference in behavior for padstack replace using axlPadstackReplace and command Replace Padstack+ m; `$ K5 @: L5 C3 \
1333896 ASI_SI OTHER signoise -f and -k options don't work for net names with consecutive underscores.
* e1 x) u* \4 S1333982 ALLEGRO_EDITOR ARTWORK ARTWORK: Coordinates of the hole get shifted by the "Draw holes only" option.
: I2 l$ E( y: k7 P1334302 CONSTRAINT_MGR SCHEM_FTB Import Logic - Import changes only or Overwrite current constraints fails to update signal models.5 t. Z& [: @" L) \
1335276 CONCEPT_HDL OTHER On selecting objects near the schematic page border, the border is also selected% T) n4 [* a. |% n# G
1336322 CONCEPT_HDL CORE DE-HDL does not open with maximized window.$ g- K |/ Q, }1 w
1336783 PCB_LIBRARIAN IMPORT_EXPORT con2cap fails to export the part to OrCAD Capture format |
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发表于 2014-11-16 10:30
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发表于 2014-11-16 23:52
