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Introduction:
0 V! i5 F" q |' R, T1 c FPGA designers are faced with a unique task when it comes to designing power distribution
- T+ I9 t- C; L- `systems (PDS). Most other large, dense ICs (such as large microprocessors) come with very
2 j. M9 k; @0 k$ n% ]6 O! Jspecific bypass capacitor requirements. Since these devices are only designed to implement
+ `+ M ^5 |+ C' rspecific tasks in their hard silicon, their power supply demands are fixed and only fluctuate
$ M2 M, Z5 S! w7 ]" D# O0 ^within a certain range. FPGAs do not share this property. Since FPGAs can implement an9 S. ~% x6 Y9 q0 }
almost infinite number of applications at undetermined frequencies and in multiple clock
: K6 g* y1 f5 } x/ S0 X; ddomains, it can be very complicated to predict what their transient current demands will be.5 V5 z5 N7 F5 ?* _
Since exact transient current behavior cannot be known for a new FPGA design, the only
! T9 |' A: U# w! x$ T$ r7 E5 r$ \- Wchoice when designing the first version of an FPGA PDS is to go with a conservative worstcase0 P; V# \! R3 h
design.6 ~/ N! [% a. I7 G ]
Transient current demands in digital devices are the cause of ground bounce, the bane of highspeed) S! C2 u; {% ]( j
digital designs. In low-noise or high-power situations, the power supply decoupling; D* y5 F2 }' T6 W1 l
network must be tailored very closely to these transient current needs, otherwise ground; [! `0 w- \+ u, a0 n7 c
bounce and power supply noise will exceed the limits of the device. The transient currents in an4 |% _7 W+ x& [, A
FPGA are different from design to design. This application note provides a comprehensive" D: t7 T& f3 c
method for designing a bypassing network to suit the individual needs of a specific FPGA
( S, [. `4 o# t* b7 c2 Z* Edesign.& ~8 u( N- i& S# W: b K
The first step in this process is to examine the utilization of the FPGA to get a rough idea of its; E- }0 y! X9 w2 |6 T" k% E
transient current requirements. Next, a conservative decoupling network is designed to fit these0 Y) Z1 r5 ?0 C
requirements. The third step is to refine the network through simulation and modification of
5 s# Y4 |3 p+ v( ], E- ncapacitor numbers and values. In the fourth step, the full design is built and in the fifth step it is
# V ]8 M) X" |( }measured. Measurements are made consisting of oscilloscope and possibly spectrum analyzer' k% W. o h5 E6 g) q* F
readings of power supply noise. Depending on the measured results, further iterations through
! \, F$ e. S5 ~- r I- v" mthe part selection and simulation steps could be necessary to optimize the PDS for the specific
; ?8 {' f+ C$ `* N: N, r1 w6 }- oapplication. A sixth optional step is also given for cases where a peRFectly optimized PDS is
. r7 J: w$ r s6 {0 m& \9 q) l* o. G- rneeded. |
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