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第二章 虚拟地址到物理地址转换2 Z6 ~" [# S# Z$ `% C: j
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2.1 MMU 硬件VA到PA转换% z+ L( |- @7 G( w8 T! [
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9850K 的cpu是Cortex A7的。3 s c2 m( z8 V- M, l( ]& i9 y
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. _% `. g: v9 C/ g' B; KThe Cortex-A7 MPCore processorimplements the Extended VMSAv7 MMU, which includes the ARMv7-A Virtual MemorySystem Architecture (VMSA), the Security Extensions, the Large Physical AddressExtensions (LPAE), and the Virtualization Extensions.$ y! p: J3 R6 f+ v. f
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+ B: C- q4 k J! W: xVMSAv7 defines two alternativetranslation table formats:
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Short-descriptor format6 y9 V, ~( T# S5 k
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9 ~$ F* }# c4 U$ i3 b% LThis is the original format definedin issue A of this Architecture Reference Manual, and is the only7 \; V8 ^* `$ K' E/ m- I
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' t8 ` H' x# h1 `7 x# \4 \format supported on implementationsthat do not include the Large Physical Address Extension. It8 |" r9 P% g0 T# r% ~/ F% l, q
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6 z- [ _" w& Z& V% ]! j" wuses 32-bit descriptor entries inthe translation tables, and provides:
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• Up to two levels of address lookup.9 s# G/ F) i/ H9 y3 U$ A; o
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• 32-bit input addresses.
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• Output addresses of up to 40 bits.
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& U. m$ q9 s4 |: o5 {" C• Support for PAs of more than 32 bits by use of supersections, with16MB granularity.2 i9 ]. B; `6 |4 {7 u6 M
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) d9 M3 ~, Y' Q' l• Support for No access, Client, and Manager domains.0 @' S( a& }! O' n
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• 32-bit table entries.6 y W p3 J7 g: M6 d7 x J
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( n; B t+ X# K0 G5 _: ?4 { ALong-descriptor format
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