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本帖最后由 auto1860 于 2017-7-3 15:25 编辑 5 G+ B2 T2 Z `' \- L
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Fixed CCRs: SPB 17.2 HF022
! _; q9 m" ~4 u06-16-2017- O+ ~( k& g s" h9 T; B
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CCRID Product ProductLevel2 Title
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1755789 ADW DBEDITOR Checking in HSS Block returns 'Failed to create archive'+ K$ |1 L Q8 l, a! _
1731459 ADW FLOW_MGR Cannot open LRM from Flow Manager
; ?: u- x6 _ A- i1731460 ADW FLOW_MGR Cannot open LRM from Flow Manager
2 ~5 g5 \% `! k) w9 F1744081 ADW FLOW_MGR Error regarding configuration file when trying to open Workflow Manager
" u" n( `- ~ a7 f- u, k1756727 ADW LIBIMPORT EDM Library Import fails with java exceptions when merging classifications" u4 |6 u7 b% J5 H+ W2 ?1 x
1743763 ADW SRM Find filter is grayed out when allegro PCB Editor is opened from EDM Flow Manager
* S I8 J$ L9 H; v7 N0 O* T" ]1748399 ALLEGRO_EDITOR DATABASE In release 17.2-2016, end caps not visible for certain clines in PCB Editor/ y+ l: a. G4 e- O! ~
1748522 ALLEGRO_EDITOR INTERACTIV A component mirrored using the 'funckey' command jumps to (0,0) position when the 'move' command is used on it) k* j' o( h4 ]4 r& u8 S
1734983 ALLEGRO_EDITOR INTERFACES Secondary step model does not stay mapped after drawing is reopened
1 K9 J L) r% B0 P" H, Z1753704 ALLEGRO_EDITOR REFRESH Refreshing symbols crashes PCB Editor
1 \& ~4 @) u5 i' `5 @3 y5 S1493721 ALLEGRO_EDITOR SHAPE Voids on negative planes are not adhering to constraints
( F3 j7 e+ S; x1711242 ALLEGRO_EDITOR SHAPE Route keep out leads to partly unfilled shapes with gaps
8 ?4 b+ e) u6 |2 p0 ]. Q1726865 ALLEGRO_EDITOR UI_GENERAL Pop-up Mirror command does not mirror at cursor position( b8 U+ A; i4 H
1752987 ALLEGRO_EDITOR UI_GENERAL axlUIViewFileCreate zoom to xy location not working while in user created form.: D5 ~) D) q: E, p. ]/ O1 A B/ y' u
1755638 ALLEGRO_EDITOR UI_GENERAL In release 17.2-2016, zoom operations using mouse button not working when axlShellPost() is run
' l7 i! v+ w1 ?5 Q1719792 ALLEGRO_PROD_TOOLB CORE Productivity Toolbox Z-DRC hangs or crashes PCB Editor( F7 C$ A1 ~7 j
1624869 ALTM_TRANSLATOR CAPTURE A structure file is required to translate a third-party schematic to orcad Capture
9 \" x2 T# ^! ]0 }! R1707416 ALTM_TRANSLATOR CAPTURE Missing components and pins in the OrCAD Capture schematic translated from a third-party tool) D+ c! P8 [1 H# _
1708825 ALTM_TRANSLATOR CAPTURE The third-party translator fails to translate the schematic
: ?# F: Z( k9 g8 G% C7 G0 Z1719200 ALTM_TRANSLATOR CAPTURE The third-party translator fails to translate all the pages of a schematic
& S6 A0 N) U- r$ Y' ^2 o1 T6 n, z1546070 ALTM_TRANSLATOR CORE Third-party to DE-HDL schematic translation fails+ c/ b0 b; r T% p3 L4 |
1700508 ALTM_TRANSLATOR CORE Third-party PCB translator does not work in release 17.2-2016
" W) {" O1 e, d: t; @1699340 ALTM_TRANSLATOR DE_HDL Unable to import third-party schematic into DE-HDL using Import menu in PCB Editor/ A3 [" a$ ?$ r$ g9 Q- F
1630379 ALTM_TRANSLATOR PCB_EDITOR Third-party translator is not importing clines and vias
6 _1 l9 O( L' [9 b$ u1708615 ALTM_TRANSLATOR PCB_EDITOR All items of third-party PCB not imported in release 17.2-2016
# G2 `* w0 x( L1 \; \' i+ ~1758296 APD DXF_IF DXF OUT: Rounded rectangle pads mirrored incorrectly
3 Q1 t8 F1 H( x' t1756040 APD IMPORT_DATA The 'die text in' command ignores values after the decimal point$ ]9 n5 @/ W0 [4 G$ M" j
1727206 APD SHAPE Merging two shapes results in an incorrect shape
* ^6 z2 U- y ?- ~/ u- M5 \- L J1753682 concept_HDL CONSTRAINT_MG Constraint Manager stops responding while cross probing DE-HDL
6 | \1 O J. O1721334 CONCEPT_HDL CORE dsreportgen not able to resolve gated part on schematic
5 }5 |% o& O( |2 X: v1747559 CONCEPT_HDL CORE Copying a logic symbol without a part table entry results in ERROR(SPCODD-53)! F( F) t! W6 P
1749644 CONCEPT_HDL CORE In release 17.2-2016 Hotfix 019, 'align components' is not working on Windows 8 and DE-HDL crashes& B+ ^2 L1 c! G& G7 ~; q
1746910 CONCEPT_HDL GLOBALCHANGE Global Component Change unable to identify part data when using schematic pick option1 t: }) |% b4 J1 H }2 A
1743572 FLOWS PROJMGR Project Manager displays incorrect values in Project Setting2 ?3 J4 i! M' e. T
1724124 FSP DESIGN_EXPLOR Provide TCL command to filter design connectivity window
- o1 }9 ?7 C t: s2 [" m$ V( }, O4 s) t1719105 FSP GUI Tabular sorting not working in FPGA System Planner
- ?! ~: @6 q* O' t* M* K1755750 PCB_LIBRARIAN GRAPHICAL_EDI In release 17.2-2016, unable to delete _N pins in PDV Symbol Editor
6 Y" Z, w/ T) ~. H7 b4 Z9 `; ^! y1722993 PCB_LIBRARIAN IMPORT_CSV Part Developer crashes while importing part information stored in a .csv file
( z1 s7 R5 V/ t4 [; M8 H1758856 SIP_LAYOUT 3D_VIEWER Correct the spelling error in the 3D Viewer Design Configuration window
5 h4 p# j. b0 n1755179 SIP_LAYOUT ARTWORK PCB Editor crashes when creating Gerber files* j+ S! @4 Q, Q7 D
1743511 SIP_LAYOUT MANUFACTURING Package Design Integrity shows non-redundant padstacks in the Redundant Padstacks check
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