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补丁包更新列表！
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DATE: 11-20-2015 HOTFIX VERSION: 061
/ L' W, q+ a4 s \" g4 d: n& Y===================================================================================================================================
i. L; i- k5 O% B1 \" J0 R& M- k6 X, ACCRID PRODUCT PRODUCTLEVEL2 TITLE" R9 A T6 T' A! g
===================================================================================================================================/ u1 Z! t5 ^3 Y& x: k! ?7 J
1306441 APD OTHER The Minimum Shape Area option in Layer Compare uses an unspecified value
' x- j$ w# v2 s `4 l1342644 ADW COMPONENT_BROWSE Need directive or method for Component Browser to load a search criteria file upon init' s$ Y9 D; M& Z. \) D' S
1413248 concept_HDL CORE Import from another TDO project makes the block read-only
. O Y& f' ]" m! C( J1417429 allegro_EDITOR INTERACTIV Pick box only accepts 1 set of values. You need to close the box and reopen it to draw a rectangle
0 h, N5 [' W' m) L) W! F% s1417442 ALLEGRO_EDITOR INTERACTIV Spin via stack and only part of the stack spins
( @7 _9 S7 s x( S& K3 U8 p1451977 CONCEPT_HDL PDF Origin of PDF mediabox not starting at (0,0) when PDF page_height and page_width are set* u5 x8 v8 B5 [. r- N
1453527 ALLEGRO_EDITOR EDIT_ETCH Contour route hugs the outer edge of the route keepin8 G" \" \, {6 R% A
1464948 PCB_LIBRARIAN VERIFICATION The errors/warnings do not match between the various tools# q1 _' H0 J7 x
1467826 CONCEPT_HDL PDF PublishPDF from Console Window creates a long PDF filename/ q- o( e+ z* j3 m
1478639 CAPTURE OTHER Capture Browse Nets window does not display all nets
- U! R, H L% m( e- G1479177 SIP_LAYOUT OTHER Pin pair constraints do not appear to be supported in Sip Layout XL% [9 ~; L* ^ u4 n
1479227 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule flagging invalid voltage in hierarchy# a8 j2 p8 j' m( M+ \$ x9 @
1479454 CONCEPT_HDL OTHER DE-HDL issue: locked DIFF_PAIR property is editable
) v/ p+ D) _$ N1480293 CAPTURE PROJECT_MANAGER Capture hangs when searching for all nets
7 X/ H x6 \6 M8 v9 G& @1483894 CONCEPT_HDL CORE Import Design hangs when pull-down arrow is clicked twice% s4 O. D, a: [$ R) ?3 [+ \0 v! p
1484781 CONCEPT_HDL CORE Three different Hierarchical Viewer issues- N' g7 E7 K# J0 X( m* V
1485059 PCB_LIBRARIAN CORE Part Developer pin attributes are randomly marked as read-only
& Q( O. r# r8 P" T" [% @: D1485960 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule is crashing the project
- d1 F7 w; U4 L) j6 `0 i1486086 ALLEGRO_EDITOR ARTWORK Cannot generate artwork.. @* x, }- Z5 J' B5 b6 C' }
1486834 CONSTRAINT_MGR OTHER Restore the Status column in cmDiffUtility
% I5 T' b/ V: h+ m J/ L. e- t1487085 CONCEPT_HDL CONSTRAINT_MGR Import Physical with the Constraints only option reports problems. [" f, ` f. k. d) {1 U
1487197 ALLEGRO_EDITOR DRC_CONSTR Drill to Via DRCs are not being reported
N& e+ z: W& N! X+ G4 s1487265 CONCEPT_HDL CORE Replace command in Windows mode shows incorrect behavior* e- P8 G% Z1 Y2 [
1487733 CONSTRAINT_MGR OTHER Running Export Physical - It takes over two hours to update the PCB Editor board
$ U. v( _! O2 J1488758 CONCEPT_HDL CONSTRAINT_MGR CM_VALIDATION_ON_SAVE should be a hard stop on Constraint Manager
5 e( o. e5 J5 {& @: z1490299 SCM OTHER ASA does not update revision properly/ l+ q4 v8 {/ C- h
1490744 ALLEGRO_EDITOR skill axlChangeLine2Cline changes line to cline and places it on the TOP layer
k3 h$ X5 {/ {/ l2 K, S1490924 F2B PACKAGERXL Save Design/Export Physical is resetting Via constraints/ g3 n- j$ `. z$ E. L6 Z' V
1491351 ALLEGRO_EDITOR OTHER Create Detail for bond fingers on a custom layer not working
0 b5 P m; d3 w6 H3 w$ d6 `" r( x1492595 ALLEGRO_EDITOR MANUFACT Dimension character substitution help is wrong2 J8 n' P5 y q8 w; X9 F# ~
1492777 ORBITIO ALLEGRO_SIP_IF OrbitIO import of customer mcm results in crash+ O: `! M7 G8 a8 H% G
1492901 CONCEPT_HDL CORE Cannot instantiate a multi-sections symbol (> 10 versions) in Design Entry HDL
( {( s, `! {2 e9 z% r( I1495621 ALLEGRO_EDITOR INTERFACES Oval pins are placed with wrong orientation in IPC2581- X, x8 c2 Z9 G$ r' o5 M( g8 O% ^
1497597 ALLEGRO_EDITOR DATABASE Show Element on pin shows wrong drill size9 @: m0 l4 P1 n* C9 d: Z
1497956 CONCEPT_HDL CORE ADW Library Flow test schematic generation crashes DE-HDL while saving the design when using customer adw_conf_root, q% V3 A; t& y S! m5 `
1498234 ALLEGRO_EDITOR ARTWORK PCB Editor fails to create artwork and no error is listed in the log file
/ ?" J/ R) T6 m. i" G+ T1499363 CONCEPT_HDL CORE Custom attributes under variant management stopped working in Hotfix60
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1 F2 i. ~: `2 a1 {最新破解包列表！
2 k( h# f2 \: r% q------------------------------------------------------------------------------
/ c4 J8 c" p" Y1 @2 q2 {$ pSPB 16.6 UPDATED KITS RELEASE: ISR 16.60.061 EST.DATE: 11-20-2015
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CompBrowser16.60-s037wint
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DSCore16.60-s055wint4 F/ M4 N+ t4 A- h$ F$ P+ g7 n
DSSchgen16.60-s030wint
! H4 [( t, W0 C6 V0 jDSSetup16.60-s010wint
2 s, A4 i; z. Y0 r# \DSTableEditor16.60-s018wint
% x3 E; W$ a$ J/ EDSTextEditor16.60-s015wint
) o" m( P' ^- c3 bDSUICommonIndep16.60-s019
) ^. v4 @. _8 u/ H1 UDSUICommon16.60-s026wint
6 e" c. r0 h; u$ J i3 ~DSUIUtils16.60-s037wint
- M4 Y8 }- I1 _2 i# KSPBIX06116.60-p002wint
$ t4 @3 B; g6 n" \' I" IadpPDFLibs16.60-s033wint
+ t& ]! Y( }5 d& v- T3 V3 GadvanPakgDsnr16.60-s129wint
( |/ P& Z' C1 f' |* G* PadwLRM16.60-s033wint
. v5 N5 F* ]6 Y9 k$ P" H; tadwSDM16.60-s044wint1 n; ^: ]6 R- c; z+ [0 |; K3 ?
algroAcad16.60-s122wint
- H4 ^$ }) o Q+ s- A: YalgroArtwork16.60-s122wint
: Z+ p4 v2 z/ ZalgroAxl16.60-s0488 i E: [0 }/ C0 S; G2 t( H! R
algroBase16.60-s129wint
" C9 y0 ~( c ?, s3 B) dalgroCxt16.60-s077& o, `) T0 }: q( i' E% k, b6 }. G
algroDBTools16.60-s124wint% L5 N0 o) _- I* W% T! p
algroDsign16.60-s122wint
: Q0 O7 y& r$ d6 S ]( e8 u( xalgroF2B16.60-s122wint4 c6 L3 K2 a- K0 O
algroIDF16.60-s122wint7 o* e O+ {- N1 v/ z- ?4 _) x* S
algroIgin16.60-s122wint5 c& c: D. E! ?' @; J+ a3 X5 P
algroIgout16.60-s122wint5 d2 w M6 n! L
algroIpc16.60-s122wint
" }2 D5 G8 y4 U& L# h7 O0 ]algroMfg16.60-s122wint, ~" g8 q3 H' V
algroNetin16.60-s122wint
! a; `8 S6 O/ D$ p. O& z2 t ]algroPlace16.60-s122wint
; r b9 Q7 O/ C5 `: V/ F; t3 H3 WalgroSgnse16.60-s122wint/ v9 D8 [ \% ^% C) |
algroSpif16.60-s122wint
: T5 V8 \) l/ J4 halgroStrm16.60-s122wint1 a' L$ K- s% _3 f9 d. Z p0 y! G
algroTextIndep16.60-s089 B4 v6 \0 }4 p4 K% @3 a8 A1 i
algroTransltr16.60-s121wint
' |. m# {! A. i. N [algroUtlty16.60-s122wint
" D" r6 d- x# k& n) h3 nbom16.60-s030wint
6 \5 A$ J0 o6 T5 ?7 M* [( k5 mcapPSpLibMAB16.60-s018wint9 I0 _& v( e, |; L) X
capProg16.60-s044wint
7 U+ }9 n2 H6 S, R6 n0 echeckplus_exp16.60-s023wint) F. B1 i+ p6 a: @ J0 Z+ \
conceptNT16.60-s106wint
5 j# } _8 L5 CconcptSetup16.60-s015wint7 Y7 d/ Y% R( z7 O* s
consMgr16.60-s104wint, L* E/ b8 W: \7 }7 [7 _
desSync16.60-s019wint& L. P) a. l9 q) A0 B7 y
eCWCore16.60-s009wint
- `# X* D4 z- y4 u3 KfetBase16.60-s034wint
4 u7 a+ C- o: |* o# jicpCommon16.60-s122wint
# y. Y/ H5 c, M7 Yiff2hdl16.60-s010wint
! X C" |4 U) `: p6 W, flmancore16.60-s036wint1 Q( _3 M0 f7 d |8 B. E- N' [! y6 l
lmanext16.60-s012wint
- c( R c0 n' z( a! xlman16.60-s023wint$ d) E2 w$ e" I" n8 B) V9 F3 [
productServer16.60-s084wint
6 g* J9 J7 d* m% u* V! TprojMgr16.60-s015wint
& G/ K+ }3 K7 s- N- T# CpspProg16.60-s043wint
1 _3 [! {, P% T5 R! c; S0 ~# Xrfpcbfe16.60-s026wint1 [* _8 o" s& m3 {1 l7 i2 A
rfsipPcellIndep16.60-s005/ U1 P; j) _! P
sipDsnr16.60-s128wint6 d6 z2 U7 H; ]( Q- c) _5 \, [2 S1 _( p
spbFPGAPlanner16.60-s065wint
* L, R: D; x4 Z. QspecctraQuest16.60-s122wint
6 _4 J, ^ ^7 M+ SspgSignal16.60-s123wint' g; H! q. d0 E& {# b7 T& ]
vedit16.60-s043wint
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* S5 n" D& f9 H+ R/ }2 J, o补丁包种子！, c% V: a! [ O$ m g, L8 g" t
cadence.spb.orcad.16.60.061.hotfix.rar
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发表于 2015-12-3 09:33
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