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DATE: 02-13-2015 HOTFIX VERSION: 0431 U5 w7 \( @6 _: S
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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1 z8 Z' w" b' C1259909 ADW DSN_FLOW Unlike Project Manager, parts cannot be copied from one design to another using ADW; ]7 ]# m: p- r7 I* B/ L' D
1341092 ALLEGRO_EDITOR MANUFACT Export > PDF should show drill holes if the Filled option is selected: A4 i+ P7 [6 i4 [, ?% ^* O
1356711 SPIF OTHER Unable to use PCB Router function with PA5700 license.
5 I; ?+ w) @ ?. {; H6 d4 |9 c- Q1357880 ALLEGRO_EDITOR INTERFACES Incorrect Step model view in Step Package mapping window
: n& z! ]( E& i. {) t5 D% |1362132 ALLEGRO_EDITOR DATABASE X hatch shape with cell High shows shape boundary error0 B( A7 E, T- K
1362641 ALLEGRO_EDITOR INTERACTIV Unwanted apostrophes are added to ads_sdart and few other variables under File_management in User Preference
3 m- m6 r9 [& g% L1362771 ALLEGRO_EDITOR EDIT_ETCH Running AiDT displays an error; the tool crashes on subsequent runs
7 j* M! m$ u1 g) [, }* y1363908 SIP_LAYOUT PLACEMENT SiP Layout crashes when refreshing symbols
9 D2 d, G* ]; g1364113 ALLEGRO_EDITOR MANUFACT NC drill output does not comply with NC Parameters if the unit is inconsistent* D6 R+ F5 l$ z! C
1364146 PSPICE SIMULATOR Simulating the attached Design gives 'RPC Server is unavailable' Error." N; ~% @! O! c; t; m
1364209 ALLEGRO_EDITOR INTERFACES STEP export: Allow for zero height and instance height change with PLACE_BOUND_TOP/BOTTOM
) I/ o" P' A9 z7 Y# ^' E' [1364329 CONCEPT_HDL CORE Show Physical Net Name causing netlisting errors4 G5 `7 R6 G3 }# A7 a
1364367 PCB_LIBRARIAN IMPORT_VIEWLOGIC viewlogic2con translator does not complete9 F( Z9 a9 \* d% C: c! n* f
1364771 ALLEGRO_EDITOR MANUFACT Incorrect Gerber created for mounting holes$ C+ s6 `1 ^: f4 m% @ k% N
1366415 CONCEPT_HDL CORE global navigation not working for few buses in the design1 Q7 L) W8 Z1 P" H }8 o
1367650 SIP_LAYOUT IC_IO_EDITING Add Respace command to Symed app mode for I/O drivers/ h& g" _, v( U' x8 x
1368246 SIP_LAYOUT OTHER Cannot delete die(s) that were placed manually in a design
8 h- s6 W+ c, b' [& a7 D/ T7 }0 R) ?1368889 ALLEGRO_EDITOR INTERFACES Unable to export incremental updates of the IDX baseline file
# p% d" Y7 z* ?. o5 h2 J+ A" n1369177 SIP_LAYOUT OTHER Add a new command to create a bounding shape+ T1 {+ Z$ K+ o& J
& o2 ^8 b; |) k3 z6 JDATE: 01-30-2015 HOTFIX VERSION: 042: M- G: B% y" Z4 O6 z% s
===================================================================================================================================
' ^4 U/ ^$ m% c! ?; R1 [CCRID PRODUCT PRODUCTLEVEL2 TITLE
4 ^7 X" G6 Q8 W4 J: Y/ j. e9 _3 @ R===================================================================================================================================
2 e& D1 T% W8 H' C. r5 }$ c9 e1334361 ALLEGRO_EDITOR INTERACTIV ZCopy should be able to copy multiple clines' T" X, m) m& A
1348389 CIS PART_MANAGER Update selected part status should re-query every time the command is run) B# c/ ]( Z2 H) ]; [5 e
1349342 ALLEGRO_EDITOR EDIT_ETCH Need information on how to resolve (SPMHA1-170): No available buffer identifiers.8 q8 j( v7 {. R% W) C* H$ o. f
1349849 CIS OTHER Capture crashes on generating variant reports
( d8 L. ]) l" K8 I- I: m1349983 PSPICE SIMULATOR Simulation aborts if save data option is greater than 1 sec
' H: f5 ]3 t+ S- a& T& ]1350477 PSPICE SIMULATOR RPC server is unavailable1 y! `! O7 P, ~2 U) s) m2 E
1353830 SIG_INTEGRITY SIMULATION xtalk analysis leads to crash3 I( f6 v5 q1 Z8 e+ D {& k0 {+ Q
1354644 ALLEGRO_EDITOR EXTRACT Extracta does not extract a value for specific property
9 b' R9 h \2 z7 Z" q1355337 ALLEGRO_EDITOR EDIT_ETCH Windows 8 Route Connect produces Buffer error.
# d% S% V7 M- S+ z* O$ \5 y: [8 M1355522 SIP_LAYOUT IC_IO_EDITING Option to select reference point for alignment should be available when aligning single drivers6 o) q2 F! N3 S3 I% R4 j) C9 |5 R( }
1355737 ALLEGRO_EDITOR EDIT_ETCH No available buffer identifiers cause loss of control in a routing phase( A2 X' _* K# J5 ~9 V" s
1356373 ALLEGRO_EDITOR DRC_CONSTR Design is crashing when attempting to update the DRCs.
6 O# ?/ h* n- @2 R! G1356684 SIP_LAYOUT SYMB_EDIT_APPMOD Enhance highlight of swappable pins excluding the pin to be swapped to
* {+ G* a6 l/ y) ]1358383 ALLEGRO_EDITOR MODULES mdd file is not created correctly0 m" I$ ?- I! |# x
1358558 CONCEPT_HDL GLOBALCHANGE "Global Component Change" could not update parts.
% K' r) i$ f' a. |1359780 ALLEGRO_EDITOR EDIT_ETCH The board database crashes on using Route Connect after some editing of traces.3 V" d" S. w' g9 G; e+ _
1360416 SIP_LAYOUT OTHER SiP Design Variant not being created on the design4 h9 v! J4 I1 T8 @# P- k
1360630 FSP ALLEGRO_INTEGRAT For Fixed Internal and Fixed External nets, FSP shows net schedule difference in PCB Editor
( G, F: O& A, S' n. B1361157 ALLEGRO_EDITOR GRAPHICS 3D view of footprint with STEP model not correct, although it shows correctly when footprint is placed on board file.
" R; e0 X; `2 b/ H1361925 FSP DE-HDL_SCHEMATIC Port is not connected for the nets having netname as NC.
* h1 V$ l) D7 k o* w0 N1362865 CONSTRAINT_MGR OTHER Import logic is not creating model-defined differential pairs.
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发表于 2015-2-15 23:37
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