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Power Distribution System (PDS) Design!

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    2019-12-3 15:20
  • 签到天数: 3 天

    [LV.2]偶尔看看I

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    发表于 2007-9-17 09:11 | 只看该作者 回帖奖励 |正序浏览 |阅读模式

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    Introduction:! @4 [9 [1 n! t( q' o1 x+ [
           FPGA designers are faced with a unique task when it comes to designing power distribution- a  M+ {5 Z9 p$ U
    systems (PDS). Most other large, dense ICs (such as large microprocessors) come with very$ \# R" X5 a: P
    specific bypass capacitor requirements. Since these devices are only designed to implement
    ; j1 P8 A0 F  Hspecific tasks in their hard silicon, their power supply demands are fixed and only fluctuate1 u# n. l/ T6 Y
    within a certain range. FPGAs do not share this property. Since FPGAs can implement an
    2 r. Z% u, U* t* k+ t7 [7 ^+ walmost infinite number of applications at undetermined frequencies and in multiple clock
    ( Q' A8 a5 H9 F# M# Y4 u' A2 udomains, it can be very complicated to predict what their transient current demands will be.
    6 P- R, l. N% I9 T( U1 ?* mSince exact transient current behavior cannot be known for a new FPGA design, the only6 w1 b* w' t; {0 y: q( f/ s
    choice when designing the first version of an FPGA PDS is to go with a conservative worstcase& W. N; W" }4 s3 v( D7 q
    design.
    . M% ?7 v0 U' C+ ETransient current demands in digital devices are the cause of ground bounce, the bane of highspeed4 t0 C$ N6 N# S
    digital designs. In low-noise or high-power situations, the power supply decoupling: x& U7 X, K3 N: s' s
    network must be tailored very closely to these transient current needs, otherwise ground. O1 j2 c. b2 a2 A& [/ n
    bounce and power supply noise will exceed the limits of the device. The transient currents in an9 Q  u6 O- l& c7 W. q+ H) t
    FPGA are different from design to design. This application note provides a comprehensive( V' c! X6 ?$ X' ?9 r$ @+ z' l5 D! n+ U
    method for designing a bypassing network to suit the individual needs of a specific FPGA
    * A7 c4 x6 G( @$ o7 Z) ddesign.6 }; l4 N1 c8 Q4 E) t% {# C
    The first step in this process is to examine the utilization of the FPGA to get a rough idea of its7 J5 K) [6 _. [4 _3 |4 m0 C% O
    transient current requirements. Next, a conservative decoupling network is designed to fit these
    1 I( P8 D( J0 i  brequirements. The third step is to refine the network through simulation and modification of( F( t, k! `* r' T4 V
    capacitor numbers and values. In the fourth step, the full design is built and in the fifth step it is. U1 K3 z. |+ O  j4 q" K1 j
    measured. Measurements are made consisting of oscilloscope and possibly spectrum analyzer
    5 `3 X3 f# E1 [" |0 V5 y: @readings of power supply noise. Depending on the measured results, further iterations through
    ' f9 d$ J0 A* tthe part selection and simulation steps could be necessary to optimize the PDS for the specific% s7 r: c( R# w, R  v9 b" o
    application. A sixth optional step is also given for cases where a peRFectly optimized PDS is9 R) w$ A# e* T9 P+ G% r  \; F
    needed.

    Power Distribution System (PDS) Design.pdf

    436.62 KB, 下载次数: 130, 下载积分: 威望 -5

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    6#
    发表于 2010-7-1 14:23 | 只看该作者
    很经典的东西,收藏了

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    5#
    发表于 2010-6-25 09:55 | 只看该作者
    多谢楼主了!在这儿总能找到需要的资料!

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    4#
    发表于 2008-1-3 20:08 | 只看该作者
    有没有中文的,看英文累啊............不过还是先谢谢楼主了.

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    3#
    发表于 2008-1-2 16:22 | 只看该作者
    哥們,還有麼 ,繼續發阿...河合
    头像被屏蔽

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    2#
    发表于 2007-12-27 07:55 | 只看该作者
    提示: 作者被禁止或删除 内容自动屏蔽

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    1#
    发表于 2007-12-22 09:08 | 只看该作者
    LZ摘录的一段已经蛮有吸引了,资料不错,谢谢
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