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EDA365电子论坛网»电子社区 › EDA工具&PCB设计 › PADS PCB论坛 › ORCAD导入网络表后出现这种情况一般哪里有问题?
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ORCAD导入网络表后出现这种情况一般哪里有问题?

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kris_2008

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发表于 2008-7-23 17:42 | 只看该作者 回帖奖励 |正序浏览 |阅读模式

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请各位高手帮忙看看,orcad导入网络表后出现如下的错误:
0 Y6 M, ~! ]; f: `" oReading file --  C:\ORCAD\FIC8120(REWORK).asc9 `5 D6 b* L. r9 Q/ ?
*Unspecified or unsupported version of ASCII file
$ Z- ]$ r- u" s- Z3 e! N. ]*pads-PCB*! r4 {* p& G) e+ ]
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal ARMICESEL
, J2 F8 k# o- n  u*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal ICE_GOICE
5 `# R/ }3 i& x& R5 ]5 W* Q*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal ICE_TCK
+ n* R6 p% _: q, b) w*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal ICE_DBGACK
* V: }9 ^% O6 V, m1 T2 n*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal MAC_PHY_LINKSTS
- K' a' p' u7 o- R1 c" ~*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal ICE_TMS
0 ^! R2 q8 D, C% o*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal MAC_RX_DV* q- l1 `$ {) V) b* e! Z7 V2 T
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal MAC_RX_ER* |7 Q) J4 s$ U
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal S4_TXD
5 \. Y. Y& U& U! M*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal MAC_RX_CLK/ d" N& v) z* u% R2 |3 Q
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal ICE_TRSTN0 B+ d) N5 z# g0 K! v9 ~: s
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal MAC_MDC) \( _8 D  [, T# O, g# N
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal S4_RXD! L8 [; ]- ?, p- r0 @: {4 g
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal MAC_TXD0+ T9 O1 j  j; e" v# P3 C
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal MAC_TXD1
$ Z$ p0 w( i, W*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal MAC_TXD2
: O' ~8 \/ n: n/ u*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal MAC_TXD3
8 n, i! M+ m- g) R*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal S2_TXD_16866971
6 `& _+ ^/ ~! l, {% j*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal V_DO6_16866325
0 |( b( x( j+ h8 Y*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal V_DO7_168663255 v0 B! ^/ t# S6 L
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal V_PCLKIN_16866325
$ J+ U4 ?. z5 C$ V2 m/ ?' c! [# d*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal MAC_RXD06 W7 I; m! ]# a$ D
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal V_DO5_168663259 A" I1 Y& n8 ]* M. D, A1 g. H
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal MAC_RXD1
/ y( Y! e) `9 K0 v*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal U_VBUS_16866872
* K* T( H7 p  S$ C*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal MAC_RXD2
6 r5 w" |; m: h/ V9 P6 U*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal V_DI5_16866325
2 M' D$ t' ]1 l. Q) `; g*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal MAC_RXD3
+ Y2 n  o" H$ c, q9 l*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal MAC_PHY_LINKSTS_16866325
- M& p0 \* g" N# M, k0 w*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal S1_TXD_168669712 F5 i0 X# G8 [+ D) {! [: f
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal S3_RXD_16866971: L5 `0 I! }2 A; f6 u0 l  n
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal U_PWM_EXT_16866872% ]# x/ w7 c0 |0 G: h# q
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal V_DI3_16866325# `4 U% W2 x3 P  T7 M
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal V_DI2_16866325  ?0 q1 K; a% M0 V* e) L. F1 c
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal U_PWM_OUT_16866872
) T8 V1 H) p: K/ M*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal V_DI0_16866325
: ]1 B: G; }4 z. f, ]*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal V_DO7
. r( F6 D) y: U. P- z*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal V_DO0
8 x7 o  q( E: f* A3 }* r0 u9 T9 f9 k*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal V_DO12 i& q7 D+ \! G8 i* _, O
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal V_DO2
, Y% T! [# s$ v. v- b*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal V_DO35 U+ M& ^9 A+ p) J7 \
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal V_DO4. f# F6 m, b% o2 W( o+ i: ]
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal V_DO5
  E2 E8 K) q0 O1 K*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal V_DO6" U+ |3 y& d& H
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal N20752712
6 c4 |0 h3 u3 T7 ^# Z2 z* q7 x2 r1 K*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal U_PWM_PDMOS
  l% r$ a! t4 n6 ?% i8 o*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal N18528902
- N" R2 K+ B" i1 V/ N*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal A3.3VAUD% S9 `& K+ ^8 `0 X' s' I" w8 h& p
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal S2_RXD
1 Q2 k, B9 [6 e% q. R/ Z9 q*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal S2_TXD" ]; U/ D5 X/ \* `  D1 }. z$ ^/ e( j" O
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal MAC_RXD1_168663251 s& Z7 z- P4 A$ \9 e. @0 w
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal MAC_RX_ER_16866325" v; D! b& f1 j& h
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal MAC_MDC_16866325
  n8 I( R; Y& ^/ ~; ?*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal MAC_RX_CLK_16866325
; C6 f% B4 u; C; n7 ], L*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal MAC_TX_CLK_168663259 g- X0 y3 {3 c4 Y0 n2 E2 W; a5 ^  K
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal V_DO2_16866325# r9 {; G4 f* N
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal MAC_CRS_16866325
; l8 g7 R* A9 i! d" f*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal MAC_COL_16866325
% V* M  q$ |& R3 f* G" |  C*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal MAC_RX_DV_16866325$ D# f: T; N/ U- D  j+ R
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal MAC_TXD0_16866325
) ?- v6 T! g& f3 k*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal MAC_RXD3_16866325
( Y- N; D7 E# j$ ^+ l# w*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal V_DO4_16866325# b1 \& H( f# u4 i
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal V_DO3_16866325  g/ i6 v4 l( h& G* k) ?8 s! z
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal V_DI6_16866325
0 d0 P6 r' h0 W$ P3 a2 x* p! ]: D*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal V_DI4_16866325( R' `2 f4 d! X  L
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal S4_TXD_16866971
  @# ?9 t5 \$ C2 m0 H*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal MAC_TXD2_16866325
/ X5 V- I, e) ^) T% n7 D*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal U_PWM_PDMOS_16866872
  I/ S3 P; s' T- `- f- h) o*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal MAC_RXD0_16866325& O- s0 @6 z* _, L4 c  `* M
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal V_DO1_168663251 E9 N# ]6 t# s+ d* m. [
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal SD_WPN_16866872  ]7 \# r3 J0 t5 L
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal V_DO0_16866325
. G8 z1 F+ h' q2 I, @) K*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal SD_CDN_16866872
% O5 \" _$ s& n, w3 ~2 n*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal MAC_RXD2_16866325
' g1 d( M% {% K5 Q: O*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal MAC_TXD1_16866325- p# m0 y; ~& A1 c
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal MAC_TXD3_16866325
1 d& _0 x, {! T. l" V*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal S3_TXD_16866971
* k/ ~- k" n" E*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal MAC_TX_EN_168663254 s$ B% d# m( u$ L, F
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal S1_RXD_16866971
* _& U" V3 m+ C& [0 O, a) G*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal S4_RXD_16866971) l9 C6 s5 W( W1 V8 w3 U
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal V_DI7_16866325; p; M' W8 N6 j3 t& R
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal S3_RXD
, k& R$ z9 R5 D+ X& E: j( |% u*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal V_DI1_16866325/ v: c. Z+ l* c) _
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal S2_RXD_16866971
; E& I. C2 n/ C6 K& S" T' K*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal S1_TXD0 d5 n0 T1 o& s) z
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal MAC_TX_EN* k; u4 D0 l1 j
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal S3_TXD
8 e0 E1 e0 i2 E0 [% N. `*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal S1_RXD
5 `2 G2 z  l6 A  W" Q- c, Q*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal MAC_TX_CLK
4 L5 G- m" G5 U! |% U  _& A*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal ICE_TDI
  D  M( s9 |) ?$ B*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal ICE_TDIO+ `) ^& _+ ?1 t# u9 }
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal V_CLKOUT" c  f9 i" n3 P$ T
Warning: deleting signal ARMICESEL9 {: ?: i5 O3 I+ Q! j
Warning: deleting signal ICE_GOICE9 p* G: E; f; V# @+ Z. I
Warning: deleting signal ICE_TCK
5 s( E6 v4 @! X& E0 B5 q. P3 \! EWarning: deleting signal ICE_DBGACK% Q5 M  o2 k5 l
Warning: deleting signal MAC_PHY_LINKSTS
# u2 A% a( c" O# c0 a) w# MWarning: deleting signal ICE_TMS; L4 u# f! U  Q  \& G' Q
Warning: deleting signal MAC_RX_DV" O" g7 S) g0 a5 W+ G3 V
Warning: deleting signal MAC_RX_ER
% O2 ]( j" E8 ?- T9 Z  |# r( bWarning: deleting signal S4_TXD2 d) D* n1 x+ ^0 S' `' l% q
Warning: deleting signal MAC_RX_CLK
! p( @8 C2 ^8 C9 w# s7 Z9 TWarning: deleting signal ICE_TRSTN( M. C- ]4 L9 s* F' R: G
Warning: deleting signal MAC_MDC" ?- z7 a; j1 B  K
Warning: deleting signal S4_RXD
  H( `+ P% |0 y; r0 C$ S4 _Warning: deleting signal MAC_TXD0* {4 @) V4 L" k6 k0 k
Warning: deleting signal MAC_TXD1
5 P) @5 g/ T3 S. ]) F# gWarning: deleting signal MAC_TXD2$ m  J* M3 _: ?
Warning: deleting signal MAC_TXD3( S6 i, X9 V. x4 ]0 D
Warning: deleting signal S2_TXD_16866971& F: C/ O2 W0 K
Warning: deleting signal V_DO6_16866325
' H8 w* W& E1 BWarning: deleting signal V_DO7_16866325
* `' t+ p# {8 N/ s" M* tWarning: deleting signal V_PCLKIN_16866325
4 m& C9 x' G$ N$ R2 HWarning: deleting signal MAC_RXD05 T( s4 s6 k1 ~% F: E# |! n
Warning: deleting signal V_DO5_16866325
! G0 i0 N) _7 }* ?6 `# r5 x/ LWarning: deleting signal MAC_RXD1
5 ^5 i& q1 ~( }# c( W" B) lWarning: deleting signal U_VBUS_168668723 t& @% p( h+ B0 b) E, \
Warning: deleting signal MAC_RXD2
' _2 P! m$ ?5 O. T9 [6 x; p  i! aWarning: deleting signal V_DI5_16866325
3 b. h" d! V) S. k9 R' pWarning: deleting signal MAC_RXD3
' ?5 @' y, O0 o3 c9 s% F' o8 C# ~8 _Warning: deleting signal MAC_PHY_LINKSTS_16866325
7 z5 ?( v7 M, d; o  d# D+ A* L. C6 zWarning: deleting signal S1_TXD_168669713 [( S3 |6 k) l  A: t/ j
Warning: deleting signal S3_RXD_16866971
. o" \3 o+ M) N& _9 A- wWarning: deleting signal U_PWM_EXT_16866872
' V3 b% j  `0 L; |" g7 I1 JWarning: deleting signal V_DI3_16866325. B+ H+ a0 ~) s% g8 e0 |
Warning: deleting signal V_DI2_16866325
* C" l0 q  f2 s$ ~0 l9 D0 bWarning: deleting signal U_PWM_OUT_16866872
* W( s8 l/ E8 _) J( S; n, Z" bWarning: deleting signal V_DI0_168663250 V  ]0 a' B. Z: [. S3 C& t
Warning: deleting signal V_DO76 o1 A3 {3 q, O  ~2 c/ [3 n
Warning: deleting signal V_DO0
- f/ n4 A3 h' F( mWarning: deleting signal V_DO1( G! \0 N9 M& p) P' V
Warning: deleting signal V_DO2/ \+ {0 \5 Q& z+ z  l
Warning: deleting signal V_DO3& y. s- Z& U/ J$ c: K
Warning: deleting signal V_DO4
  r# s8 ^% V: [: W: Q% A% jWarning: deleting signal V_DO54 ^2 _2 m, Q5 ^9 o8 r; e: `: W0 m
Warning: deleting signal V_DO6
+ m. ?! j: s, N* PWarning: deleting signal N20752712
) T: y  {0 q; {7 \* kWarning: deleting signal U_PWM_PDMOS4 X4 r4 l* [3 f( w+ ^8 n) {" b
Warning: deleting signal N18528902* d. j) b8 Y# Z+ B
Warning: deleting signal A3.3VAUD
) ]. p) p/ \/ z$ ~Warning: deleting signal S2_RXD1 w6 K7 [! Y& N3 M
Warning: deleting signal S2_TXD
, V' ?2 O, T  J0 j$ _Warning: deleting signal MAC_RXD1_16866325, l* A# u" t4 b8 z( y
Warning: deleting signal MAC_RX_ER_16866325
, J7 A  \6 `8 e! a! |7 f) ~, g" LWarning: deleting signal MAC_MDC_168663253 c+ \# s% f( e% Y# m
Warning: deleting signal MAC_RX_CLK_16866325; a' t' f, b9 \% c- H* H3 G( R
Warning: deleting signal MAC_TX_CLK_16866325
. q& A0 d; |/ A4 mWarning: deleting signal V_DO2_16866325
0 I0 A6 e- V8 Z5 _. `Warning: deleting signal MAC_CRS_16866325
# R, J0 Y! Z4 k+ T" @# lWarning: deleting signal MAC_COL_16866325
- [) ?4 P2 d7 p% h1 pWarning: deleting signal MAC_RX_DV_168663250 T; b  b7 B. n# G
Warning: deleting signal MAC_TXD0_16866325- E) R1 F* z6 L; [. |# M+ d$ y
Warning: deleting signal MAC_RXD3_168663259 \* v- l  c9 j7 F
Warning: deleting signal V_DO4_16866325  }% k, y: ]- \
Warning: deleting signal V_DO3_16866325# w$ r( K# N$ H% J3 S- o
Warning: deleting signal V_DI6_16866325
  X! n5 b# h' `  ^) @+ x9 wWarning: deleting signal V_DI4_16866325# a; e  X( U& G
Warning: deleting signal S4_TXD_168669711 I4 F, E4 e: ^, g$ c8 _* U
Warning: deleting signal MAC_TXD2_16866325. \, I) N) ~: T& N9 a0 \) Z
Warning: deleting signal U_PWM_PDMOS_16866872
3 r! P& Y3 c- [' m  U1 N. xWarning: deleting signal MAC_RXD0_168663250 a7 l& z, E" k  |# n; J* ]* j
Warning: deleting signal V_DO1_16866325; J+ I/ g1 L7 r8 v
Warning: deleting signal SD_WPN_16866872
. X' [, L' v& d( S& vWarning: deleting signal V_DO0_16866325! Q) Y' x7 U* V1 o2 @5 s
Warning: deleting signal SD_CDN_16866872
* t" i5 l# I7 J; G) Z* ]Warning: deleting signal MAC_RXD2_16866325' a# i( C. {, Y4 @' w3 S
Warning: deleting signal MAC_TXD1_16866325! _. T- y; F/ [8 [. P
Warning: deleting signal MAC_TXD3_16866325
/ F9 V: F6 `4 B% |Warning: deleting signal S3_TXD_168669713 B* l4 y5 M6 e( e6 _0 q! Z% `
Warning: deleting signal MAC_TX_EN_16866325
: R5 x3 s. D( ^* ^& s5 X" i/ yWarning: deleting signal S1_RXD_16866971* J! ~: J9 Y6 D: m  T/ N  N
Warning: deleting signal S4_RXD_168669719 y' r! U* {; O
Warning: deleting signal V_DI7_16866325
# d$ C( c" D8 P) U9 _9 Y' sWarning: deleting signal S3_RXD
0 X% ?1 O% F# qWarning: deleting signal V_DI1_168663257 K7 a$ a1 n9 M; d2 U! o
Warning: deleting signal S2_RXD_16866971
7 b- a6 G2 a5 c$ e( ]( `% I) _Warning: deleting signal S1_TXD3 [. ?# |9 r# A' I3 v% g/ r) a
Warning: deleting signal MAC_TX_EN2 u' u7 N% n- D5 z6 c
Warning: deleting signal S3_TXD
, W) N, H+ Z7 {  s2 _Warning: deleting signal S1_RXD
: m+ Q  N) T. _4 V* |4 CWarning: deleting signal MAC_TX_CLK2 m  o8 n- b( U0 e- w7 l7 a8 b
Warning: deleting signal ICE_TDI
5 k) c/ V& v! h4 h. LWarning: deleting signal ICE_TDIO
. y& J  k- S! {9 aWarning: deleting signal V_CLKOUT
) e/ t: P5 i/ T1 \8 ^**INPUT WARNINGS FOUND**

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lzpsy

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14#
发表于 2008-8-4 19:31 | 只看该作者
你的pads的库中没有你在orcad中使用的封装，添加或修改封装后就可以了

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zombie

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13#
发表于 2008-7-25 14:30 | 只看该作者
应该是sch里原件的part和footprint属性与pads layout library中的不对应匹配造成；还有和你生成netlist的dll文件版本有关(见下图)，因为不同版本的dll产生的文件是不同的（主要反映在原件属性的对应匹配上）

Snap1.jpg (40.45 KB, 下载次数: 7)

Snap1.jpg

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kris_2008

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12#
 楼主| 发表于 2008-7-25 10:53 | 只看该作者
Thanks!

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jianghao8888

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11#
发表于 2008-7-24 23:30 | 只看该作者
原帖由 kris_2008 于 2008-7-24 17:54 发表 - N2 T$ l; h- s# B0 b: P( C
我已经用OFFPAGE连接而且在整个DSN中用EDIT下面的FIND找网络也可以找到,但是进行DRC时候就有这个警告,现在只剩下下面这个warning了.对了还有个问题就是我的CPU原理图用分块做的,本来想改PIN TYPE的但是我点其中的一块 ...
1 z4 v% Z% {9 b* E
/ a# W: Z( U% @7 m
PIN的属性不匹配。不过没关系，不会影响Layout，网络都是链接好的了。

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hlmm

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10#
发表于 2008-7-24 21:12 | 只看该作者
是不是你的元件管脚没有用数字编号,而是用的象管脚名一样去编了,就会成这样怪的问题

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kris_2008

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9#
 楼主| 发表于 2008-7-24 18:23 | 只看该作者
大哥能否讲得详细点啊!什么信号类型?我觉得很奇怪一个发射一个接收我都用总线进行连接但是为什么接收的有问题而发射的就没问题?今天被这个问题郁闷了一天啦!在网上也找不到相应的答案.

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datao1225

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8#
发表于 2008-7-24 18:08 | 只看该作者
Original posted by kris_2008 at 2008-7-24 17:54 8 J, G9 q+ ?# F9 q% }
我已经用OFFPAGE连接而且在整个DSN中用EDIT下面的FIND找网络也可以找到,但是进行DRC时候就有这个警告,现在只剩下下面这个warning了.对了还有个问题就是我的CPU原理图用分块做的,本来想改PIN TYPE的但是我点其中的一块 ...

) I% S- _, i! l
; K+ `9 Z. S8 N* |网络上可能已经没有问题了，但是DRC检查可能是一些信号的类型没有做好而已。' |8 r$ D9 ?+ M$ P) [
我之前遇到过类似的问题，网表是没有问题的！

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datao1225

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7#
发表于 2008-7-24 18:05 | 只看该作者
Original posted by youyou058 at 2008-7-24 11:49 / t2 O. I4 @& Q& F
/ f  E6 O, l9 _# w5 u( Y
LOGIC就比较严谨,不会有这样的问题!
7 l! ?( g) C/ s) K: ^
6 H/ l3 `5 v8 Q# o
这点麻烦跟它的便捷轻松相比，值了
2 d& c  H  s7 w( g
" {+ K; s, m6 |& Y1 A& aLogic就不是这样简单的问题了

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kris_2008

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6#
 楼主| 发表于 2008-7-24 17:54 | 只看该作者
我已经用OFFPAGE连接而且在整个DSN中用EDIT下面的FIND找网络也可以找到,但是进行DRC时候就有这个警告,现在只剩下下面这个warning了.对了还有个问题就是我的CPU原理图用分块做的,本来想改PIN TYPE的但是我点其中的一块然后EDIT PART后出现的这部分不是我点的,不知道怎么会这样啊!
+ G+ t) T+ M) c8 ^) w& K* J. RChecking for Unconnected Nets
* ^# r( q2 E! Q( UWARNING:  [DRC0007]  Net has no driving source MAC_RXD2
: S' W" h5 \# x5 r                    SCHEMATIC1, 01_FIC8120  (10.48, 1.40)
" f, H. s) g+ T$ d8 {: H6 [- iWARNING:  [DRC0007]  Net has no driving source MAC_RXD0( \2 ^; B9 X6 J
                    SCHEMATIC1, 01_FIC8120  (10.48, 1.20) ) m7 L7 l; U' R9 y4 b
WARNING:  [DRC0007]  Net has no driving source MAC_RXD13 G% U  T1 U$ ^8 \
                    SCHEMATIC1, 01_FIC8120  (10.48, 1.30) $ L* `$ r5 d  ]5 R- N: x4 `
WARNING:  [DRC0007]  Net has no driving source MAC_RX_DV
/ P, y% @, I) W- n9 K                    SCHEMATIC1, 01_FIC8120  (1.27, 2.89) * x, M( d7 E8 ~1 k9 [
WARNING:  [DRC0007]  Net has no driving source MAC_RX_CLK& ^( a2 G7 E4 h  [
                    SCHEMATIC1, 01_FIC8120  (2.17, 2.78) # J0 Z0 p7 ?; n9 L& S4 P+ R3 [/ u. _
WARNING:  [DRC0007]  Net has no driving source MAC_RXD3+ o  P9 W( X( _! q2 m* s
                    SCHEMATIC1, 01_FIC8120  (10.48, 1.50) $ y; l& ^/ s$ d3 K
上面的MAC_RXD0到MAC_RXD3我是用总线进行连接的,麻烦各位看下,实在是找不出哪里的问题啦

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youyou058
  • TA的每日心情
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    2024-6-17 15:02

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    [LV.1]初来乍到
    5#
    发表于 2008-7-24 11:49 | 只看该作者
    原帖由 datao1225 于 2008-7-24 11:22 发表 7 C& Q; P# W* O9 l2 f
    # a4 r' P+ s/ |5 w0 ?3 d& g% h; X

    2 C0 K' M$ H& Q不是已经说了吗？
    0 M& ~; N3 q$ j8 [2 W# gnets must contain more than one pin ***% q- x. J6 r& T7 e: C/ P& M2 ~- s
    Warning: deleting signal  ***
    % B0 k8 f+ U6 L1 ~6 cPADS不允许没有pin pair 的单独网络！！！
    0 b2 `/ y* y( F5 D检查你原理图的网络名有没有连接上。
    9 n8 f  I0 g0 P( _" R6 G具体的可以点击某一根线，看看它 ...

    9 B9 u2 V6 ?, \% G' G LOGIC就比较严谨,不会有这样的问题!

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    datao1225

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    4#
    发表于 2008-7-24 11:22 | 只看该作者
    Original posted by kris_2008 at 2008-7-23 17:42 : o3 U; b" D7 f
    请各位高手帮忙看看,ORCAD导入网络表后出现如下的错误:8 \3 @$ [5 W5 p8 V% f! y% q6 F; e# j( u
    Reading file --  C:\ORCAD\FIC8120(REWORK).asc
    + k  v- y" C$ g*Unspecified or unsupported version of ASCII file
    : Y# V! P0 g: P8 X" y) w*PADS-PCB*
    + I+ S! h! H5 Z  {( x7 e: u9 m*Bad *CONNECTION* ascii data format,  ...
    0 [" ~* u6 M8 J2 M) o

    " P; W# G2 F* W9 C4 U# w不是已经说了吗？* H9 V. L! N3 N- g+ w
    nets must contain more than one pin ***
    , N* n8 ~" z' TWarning: deleting signal  ***
    9 e) |& ~7 U  \1 I. R& A8 d2 LPADS不允许没有pin pair 的单独网络！！！$ K9 O, I- g5 V) R: X" S4 T8 `
    检查你原理图的网络名有没有连接上。, _7 s3 I& r+ R8 m% [
    具体的可以点击某一根线，看看它是不是你所标上的网络名？- o7 D# b  e+ T, r0 P% ]# S

    , b: s: T4 X+ W% U# N" l看来楼主的问题还有在于页面连接的问题！
    " Q! E7 c! q7 f- m( @) v0 A你看一下不同的页面之间的具有相同  Net Alias 的网络是不是也不相同？" _: i: }* y7 B
    是不是后面多了一串数字？" |/ A) ^6 R8 X6 s+ |+ ~
    那就对了，你没有用Port或者offpage connector来对它们进行连接啊！

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    kris_2008

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    3#
     楼主| 发表于 2008-7-24 10:59 | 只看该作者
    我已经进行了DRC,没出现ERRORS但是有好多warning

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    mengzhuhao
  • TA的每日心情
    擦汗
    2020-1-14 15:59

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    [LV.1]初来乍到
    2#
    发表于 2008-7-23 18:22 | 只看该作者
    orcad里面你drc了吗

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