|
|
EDA365欢迎您登录!
您需要 登录 才可以下载或查看,没有帐号?注册
x
本帖最后由 烧饼夹肉 于 2020-11-24 14:01 编辑 5 n; j! X9 a; h# N( Y$ d
& |9 y' [, H% @/ E毛老师《信号、电源完整性仿真设计与高速产品应用实例》
6 E$ c4 R) w9 y第九章 SPEED2000 DDR仿真 ,按照书籍教程操作,开始仿真后报错,如下图:9 X# E% c. s* |6 ^2 U
求大佬解答![]()
) d8 F' F! @' I! ^# A5 I' r' S1 `3 _' p f# D
SPEED GENERATOR
" }- C5 [! \: `* U0 t4 E Warning: Cannot find the intermediate file
- f% u9 H8 h; r N# x$ p$ P c esktop\ TEST_BOAR_Ddemo_DDR\Sim3_L2\net\SpModel.sp" X" a: @* M9 J/ _! |& z
One possible reason is the net selection is changed after you set the simulation options.
! I" a( X# Z7 Q/ [/ n+ `0 }/ L 1. Do not change the net selection after setting the simulation options.
2 H* Y [! M6 H7 b; Q 2. If you do change the net selection, go through the workflow and save the simulation options again.9 O$ G+ F F$ y$ e* ^! E, n
|
|