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第二章 虚拟地址到物理地址转换% \0 z% ~4 o% w
( |- C: Z5 b: w+ M3 s6 i( H. ?2.1 MMU 硬件VA到PA转换
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9850K 的cpu是Cortex A7的。
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The Cortex-A7 MPCore processorimplements the Extended VMSAv7 MMU, which includes the ARMv7-A Virtual MemorySystem Architecture (VMSA), the Security Extensions, the Large Physical AddressExtensions (LPAE), and the Virtualization Extensions.
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VMSAv7 defines two alternativetranslation table formats:
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Short-descriptor format
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7 g3 X+ T1 m% ]6 PThis is the original format definedin issue A of this Architecture Reference Manual, and is the only9 S! D( K0 C( x- f4 y
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format supported on implementationsthat do not include the Large Physical Address Extension. It
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4 F4 I2 e6 G3 y3 M; ?* T w' Vuses 32-bit descriptor entries inthe translation tables, and provides:
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• Up to two levels of address lookup.' f: b1 q% \; c/ c
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1 P& s j1 W1 ]3 @• 32-bit input addresses.$ e' k+ `2 U2 N* ^
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• Output addresses of up to 40 bits.
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• Support for PAs of more than 32 bits by use of supersections, with16MB granularity.
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/ p2 b& c; ~8 }9 |7 R* f0 b7 g• Support for No access, Client, and Manager domains.8 U! n: M" x/ q1 W/ F8 y# ]6 S
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Long-descriptor format; Z. N( k0 F, _: `# ]) M
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