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! u& S/ ^% l; E补丁包更新列表！4 q7 d: H' \# k0 O4 K0 ?2 \
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DATE: 11-20-2015 HOTFIX VERSION: 061
o& A$ {5 A1 J2 u9 U7 r===================================================================================================================================
3 j; y+ v' O2 b, v. L0 \CCRID PRODUCT PRODUCTLEVEL2 TITLE1 h* P# A* H- i T' V' j$ v; `
===================================================================================================================================
; C. D4 Q3 O% T' S5 \ k5 U& V4 R1306441 APD OTHER The Minimum Shape Area option in Layer Compare uses an unspecified value
. h! x5 } k- @- u9 L& _5 b& M' b1342644 ADW COMPONENT_BROWSE Need directive or method for Component Browser to load a search criteria file upon init( P/ ]5 z* e- W2 [1 @/ s; l0 R+ u
1413248 concept_HDL CORE Import from another TDO project makes the block read-only, t! A- _( Z2 C% j) L6 X' l+ E
1417429 allegro_EDITOR INTERACTIV Pick box only accepts 1 set of values. You need to close the box and reopen it to draw a rectangle6 i' }4 V) E# R% k! r$ s5 _ v! n
1417442 ALLEGRO_EDITOR INTERACTIV Spin via stack and only part of the stack spins
% B. k9 y3 m* W8 ^$ P1 A' i6 T1 B1451977 CONCEPT_HDL PDF Origin of PDF mediabox not starting at (0,0) when PDF page_height and page_width are set
2 O. q$ y; L5 r0 \$ Y1 Y0 x1453527 ALLEGRO_EDITOR EDIT_ETCH Contour route hugs the outer edge of the route keepin% ^% I& m! d4 P @, K
1464948 PCB_LIBRARIAN VERIFICATION The errors/warnings do not match between the various tools
9 y$ _3 A& K) z7 M1467826 CONCEPT_HDL PDF PublishPDF from Console Window creates a long PDF filename- }- _7 A, C8 ^4 h2 h4 K
1478639 CAPTURE OTHER Capture Browse Nets window does not display all nets
$ P1 L( q5 \+ ~% K! y' s" U4 S& e1479177 SIP_LAYOUT OTHER Pin pair constraints do not appear to be supported in Sip Layout XL2 S2 _3 E% ?- M: i8 v {
1479227 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule flagging invalid voltage in hierarchy% P3 P+ Z" h. B
1479454 CONCEPT_HDL OTHER DE-HDL issue: locked DIFF_PAIR property is editable! E# z9 Q7 L) b y- {3 m' V) m. x
1480293 CAPTURE PROJECT_MANAGER Capture hangs when searching for all nets) @2 s* _9 X4 |8 m, ^. f5 T& u# E
1483894 CONCEPT_HDL CORE Import Design hangs when pull-down arrow is clicked twice
/ i' B( r. y) w/ }1484781 CONCEPT_HDL CORE Three different Hierarchical Viewer issues
2 g8 N3 c% _0 r4 q: ^8 p# ^8 v1485059 PCB_LIBRARIAN CORE Part Developer pin attributes are randomly marked as read-only$ _( q6 D o+ @) M# o
1485960 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule is crashing the project, a, B& L, p% \. n
1486086 ALLEGRO_EDITOR ARTWORK Cannot generate artwork./ t% v9 [4 h; |
1486834 CONSTRAINT_MGR OTHER Restore the Status column in cmDiffUtility/ i% I. }! T9 X* g
1487085 CONCEPT_HDL CONSTRAINT_MGR Import Physical with the Constraints only option reports problems" C$ m/ U: p! u0 ~" N/ U, W
1487197 ALLEGRO_EDITOR DRC_CONSTR Drill to Via DRCs are not being reported* m% j; ~9 b' s* a, f( K1 n9 @. E
1487265 CONCEPT_HDL CORE Replace command in Windows mode shows incorrect behavior4 \) b# g6 h+ @3 H' D( Y# ?' Y1 ?+ ~
1487733 CONSTRAINT_MGR OTHER Running Export Physical - It takes over two hours to update the PCB Editor board9 S* J$ s& ^ q
1488758 CONCEPT_HDL CONSTRAINT_MGR CM_VALIDATION_ON_SAVE should be a hard stop on Constraint Manager p+ F f% G- t3 z. N" q, L
1490299 SCM OTHER ASA does not update revision properly
& v1 s- m8 u: T" o0 s7 V8 w1490744 ALLEGRO_EDITOR skill axlChangeLine2Cline changes line to cline and places it on the TOP layer6 I" |( X: k/ f
1490924 F2B PACKAGERXL Save Design/Export Physical is resetting Via constraints
+ R: d+ ]9 a" T1491351 ALLEGRO_EDITOR OTHER Create Detail for bond fingers on a custom layer not working
" g; d9 u' J7 v z3 J& [" u1492595 ALLEGRO_EDITOR MANUFACT Dimension character substitution help is wrong9 O) _: ?9 Q9 A/ y2 B3 R1 i) M$ b
1492777 ORBITIO ALLEGRO_SIP_IF OrbitIO import of customer mcm results in crash# g' w+ @ R4 H5 d9 P
1492901 CONCEPT_HDL CORE Cannot instantiate a multi-sections symbol (> 10 versions) in Design Entry HDL) u0 f/ O& C, {% l) m5 e3 D6 k+ A
1495621 ALLEGRO_EDITOR INTERFACES Oval pins are placed with wrong orientation in IPC25816 D( a( N! v/ x3 i' t
1497597 ALLEGRO_EDITOR DATABASE Show Element on pin shows wrong drill size' P2 r+ z1 a& l) r; N
1497956 CONCEPT_HDL CORE ADW Library Flow test schematic generation crashes DE-HDL while saving the design when using customer adw_conf_root- \ ]* I! S' g4 p% ?( A
1498234 ALLEGRO_EDITOR ARTWORK PCB Editor fails to create artwork and no error is listed in the log file) V# u; }, x& Z$ u
1499363 CONCEPT_HDL CORE Custom attributes under variant management stopped working in Hotfix60+ K3 ?, b% _1 K! v% O W- t
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最新破解包列表！4 b( ^3 H( a9 p! \/ \0 Z, a
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SPB 16.6 UPDATED KITS RELEASE: ISR 16.60.061 EST.DATE: 11-20-20153 Z* ^# z+ ?: C! [7 G. _
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CompBrowser16.60-s037wint
{ @9 ^5 i2 ]& p. a \DSCoreUtils16.60-s077wint% o/ J: a% f1 q7 _6 E: C
DSCore16.60-s055wint/ w6 Q2 D8 S( x& U% ^3 i
DSSchgen16.60-s030wint2 E3 w$ O3 a0 f" S0 R) [
DSSetup16.60-s010wint* `# y }9 f1 g, l8 J/ t
DSTableEditor16.60-s018wint3 W0 D. _" C9 U) r
DSTextEditor16.60-s015wint/ J6 ^7 p& u1 M: I
DSUICommonIndep16.60-s019
; z- P* a' S! j* r0 t1 t& R, MDSUICommon16.60-s026wint
, C2 ~! e( s7 k" O* J1 XDSUIUtils16.60-s037wint# P% h3 }+ U* h3 F& b' L
SPBIX06116.60-p002wint" t0 o& R1 J5 A/ M& a
adpPDFLibs16.60-s033wint3 x( `. T+ z2 T0 f2 i: v5 ?
advanPakgDsnr16.60-s129wint# V3 C. R& a" ^ r
adwLRM16.60-s033wint
( l; z$ Z9 B( }6 GadwSDM16.60-s044wint
. M8 ?6 S1 C* A. S) S, H+ AalgroAcad16.60-s122wint' ]/ v" u& i# ?+ T
algroArtwork16.60-s122wint" [( T8 W9 Y3 ^
algroAxl16.60-s048
9 M2 d& Z/ A7 D6 [& H& I/ k' J. DalgroBase16.60-s129wint+ X6 b& Q8 U/ ~4 \3 S7 O
algroCxt16.60-s0773 p, ]: \' y. i n; U
algroDBTools16.60-s124wint3 w+ u6 f+ n0 t, H/ ]( R
algroDsign16.60-s122wint6 L/ M) q( Z: Z2 I: o# y0 @
algroF2B16.60-s122wint
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+ A# N9 m9 A0 d8 O1 ^; malgroIgin16.60-s122wint
7 {$ z( q. q8 Q9 H% ~0 y5 q/ walgroIgout16.60-s122wint
/ c( s- F2 p/ Z: j% HalgroIpc16.60-s122wint
5 ^- k7 b; q! }" W( UalgroMfg16.60-s122wint
" m+ W+ w/ E2 XalgroNetin16.60-s122wint
" l9 n( _' |4 |7 Z$ calgroPlace16.60-s122wint
( D/ |% Y* x2 d) e. valgroSgnse16.60-s122wint; S/ D- X( q; R h/ ^
algroSpif16.60-s122wint; y' D- S, H: t
algroStrm16.60-s122wint
9 G! e8 o! t" C( U1 ?' e6 C9 u# KalgroTextIndep16.60-s0897 C( W, q5 z( l4 @! S
algroTransltr16.60-s121wint
+ s8 C7 |9 K4 U7 G s* t3 ^4 PalgroUtlty16.60-s122wint( t; [' ~8 [. d
bom16.60-s030wint" {- r2 q: A: c) i/ o1 E3 I
capPSpLibMAB16.60-s018wint
, _4 x' `1 H1 H$ {capProg16.60-s044wint
0 D% V$ O( u* K& N; Acheckplus_exp16.60-s023wint1 \- l! ~# ~7 A0 A/ J U
conceptNT16.60-s106wint
. ]: P; I; u5 z/ D3 EconcptSetup16.60-s015wint
' @3 T. u5 d7 {( t1 a. \0 \ \consMgr16.60-s104wint
6 T; } ?8 _/ z' r6 A( edesSync16.60-s019wint
. }; r; ~9 E$ @; s. ueCWCore16.60-s009wint% n0 T6 _1 N$ \0 i
fetBase16.60-s034wint
1 f h3 N0 K$ K. P9 u0 i( c7 f' z0 K DicpCommon16.60-s122wint
5 @" ~, [$ e( E- w' f9 i( piff2hdl16.60-s010wint
- v5 ?5 D- L/ ~; s# _. Jlmancore16.60-s036wint
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lman16.60-s023wint" k7 L! t( F) ~
productServer16.60-s084wint2 U& ^6 |, ^; R
projMgr16.60-s015wint$ r4 \; p2 z; ^2 e2 f9 L
pspProg16.60-s043wint8 S+ l# _9 f# V4 _6 @+ `
rfpcbfe16.60-s026wint; ~6 b4 W$ |3 ~3 \5 r2 g
rfsipPcellIndep16.60-s005
+ Q! @: B" s3 OsipDsnr16.60-s128wint
. {& b: t# X& N2 P# o j2 EspbFPGAPlanner16.60-s065wint9 n Q# T! w8 C# `4 C
specctraQuest16.60-s122wint
6 ^1 Y$ K8 x5 \5 y' VspgSignal16.60-s123wint- r2 P) W3 x5 ~( D: R
vedit16.60-s043wint
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3 X- n" M$ _2 K. w补丁包种子！$ L6 h( ^8 B* B; E; `7 @3 ^
cadence.spb.orcad.16.60.061.hotfix.rar
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发表于 2015-12-3 09:33
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