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DATE: 02-13-2015 HOTFIX VERSION: 043! `6 r& ~2 D& @+ I
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& a6 v& K5 l- E! n' }CCRID PRODUCT PRODUCTLEVEL2 TITLE1 d$ N0 L: S) T# ?5 m/ @- p
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/ A6 P2 p0 E. u* R1259909 ADW DSN_FLOW Unlike Project Manager, parts cannot be copied from one design to another using ADW; o0 z9 A. M, E% i0 d9 j
1341092 ALLEGRO_EDITOR MANUFACT Export > PDF should show drill holes if the Filled option is selected
M- r3 P- g$ f6 A( b1356711 SPIF OTHER Unable to use PCB Router function with PA5700 license.3 S% C3 f( t, s0 Z( G9 {# {/ q' L
1357880 ALLEGRO_EDITOR INTERFACES Incorrect Step model view in Step Package mapping window
, B$ ]1 |& h- t& B# }. @1362132 ALLEGRO_EDITOR DATABASE X hatch shape with cell High shows shape boundary error
2 `& {* R3 |" N; s1362641 ALLEGRO_EDITOR INTERACTIV Unwanted apostrophes are added to ads_sdart and few other variables under File_management in User Preference
: ~3 Y7 `( ?8 R; l* B1362771 ALLEGRO_EDITOR EDIT_ETCH Running AiDT displays an error; the tool crashes on subsequent runs
7 R+ M6 ] p1 w1363908 SIP_LAYOUT PLACEMENT SiP Layout crashes when refreshing symbols$ b7 B( v& }# {9 d9 ~: v! P
1364113 ALLEGRO_EDITOR MANUFACT NC drill output does not comply with NC Parameters if the unit is inconsistent6 ~8 }1 X) q) ?( U; g
1364146 PSPICE SIMULATOR Simulating the attached Design gives 'RPC Server is unavailable' Error. W+ g! i/ m- C# O9 c3 I
1364209 ALLEGRO_EDITOR INTERFACES STEP export: Allow for zero height and instance height change with PLACE_BOUND_TOP/BOTTOM
# y9 j% p7 |0 b! w$ ~1364329 CONCEPT_HDL CORE Show Physical Net Name causing netlisting errors
: _- o0 j0 |* V% o6 U. u1 d1364367 PCB_LIBRARIAN IMPORT_VIEWLOGIC viewlogic2con translator does not complete
2 G2 [1 E7 Y1 {# W7 y! |1364771 ALLEGRO_EDITOR MANUFACT Incorrect Gerber created for mounting holes8 z' l( F; P9 N: J7 b; M
1366415 CONCEPT_HDL CORE global navigation not working for few buses in the design
+ H& F8 T( ^1 @1367650 SIP_LAYOUT IC_IO_EDITING Add Respace command to Symed app mode for I/O drivers
9 x6 \' b" L0 n( F, b, _1368246 SIP_LAYOUT OTHER Cannot delete die(s) that were placed manually in a design
- g! Q: [6 ^( O a+ u+ E2 M1368889 ALLEGRO_EDITOR INTERFACES Unable to export incremental updates of the IDX baseline file& r" u6 l" P# n
1369177 SIP_LAYOUT OTHER Add a new command to create a bounding shape" _* M! v% B; o( g. d
% `, R6 z/ Z3 m: l& U* K+ _DATE: 01-30-2015 HOTFIX VERSION: 042$ C8 K- F# o o* N3 |# i
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; l7 C. K% f& t, q- j7 ?- OCCRID PRODUCT PRODUCTLEVEL2 TITLE
( m" n: y5 H Y! C; W* z4 l===================================================================================================================================
- N3 h0 p( C+ {5 i* s1334361 ALLEGRO_EDITOR INTERACTIV ZCopy should be able to copy multiple clines
' v, v' y& ~* P) p8 E1348389 CIS PART_MANAGER Update selected part status should re-query every time the command is run
I5 ]" ]% `: P( G: y* y1349342 ALLEGRO_EDITOR EDIT_ETCH Need information on how to resolve (SPMHA1-170): No available buffer identifiers.9 m4 ?0 M$ }2 h8 [6 \0 s
1349849 CIS OTHER Capture crashes on generating variant reports
. D6 c4 ~! q' o8 l7 X Z" v1349983 PSPICE SIMULATOR Simulation aborts if save data option is greater than 1 sec
! R& f' Y8 }! b% A# `1350477 PSPICE SIMULATOR RPC server is unavailable9 z. w8 y; X3 t4 E" L, m
1353830 SIG_INTEGRITY SIMULATION xtalk analysis leads to crash5 G* Q& k: K& z4 n
1354644 ALLEGRO_EDITOR EXTRACT Extracta does not extract a value for specific property r! n8 Q, S6 R5 N
1355337 ALLEGRO_EDITOR EDIT_ETCH Windows 8 Route Connect produces Buffer error.
! w; S, @3 C# a. B0 l' z* N1355522 SIP_LAYOUT IC_IO_EDITING Option to select reference point for alignment should be available when aligning single drivers8 h c9 E6 e$ j
1355737 ALLEGRO_EDITOR EDIT_ETCH No available buffer identifiers cause loss of control in a routing phase; X& V" l+ i2 H* D; I
1356373 ALLEGRO_EDITOR DRC_CONSTR Design is crashing when attempting to update the DRCs.
0 p9 o) @" S. T/ l8 j, E1356684 SIP_LAYOUT SYMB_EDIT_APPMOD Enhance highlight of swappable pins excluding the pin to be swapped to
, g" J! I6 c' f/ t1358383 ALLEGRO_EDITOR MODULES mdd file is not created correctly
% Q. W8 Q: a" f8 }8 x2 Z4 Q1358558 CONCEPT_HDL GLOBALCHANGE "Global Component Change" could not update parts.
& Z7 @4 a, D5 ~8 o6 ^3 G; |; U1359780 ALLEGRO_EDITOR EDIT_ETCH The board database crashes on using Route Connect after some editing of traces.. \/ F5 b9 S0 f: f
1360416 SIP_LAYOUT OTHER SiP Design Variant not being created on the design, ?' a0 f5 X4 I: h4 V# q
1360630 FSP ALLEGRO_INTEGRAT For Fixed Internal and Fixed External nets, FSP shows net schedule difference in PCB Editor
5 l5 G# Q" M+ ^" U- Q4 k2 B/ ~1361157 ALLEGRO_EDITOR GRAPHICS 3D view of footprint with STEP model not correct, although it shows correctly when footprint is placed on board file.
: x% i3 R% z/ N: I' B% L6 Y4 H1361925 FSP DE-HDL_SCHEMATIC Port is not connected for the nets having netname as NC.( A+ b' ]+ W8 g, C
1362865 CONSTRAINT_MGR OTHER Import logic is not creating model-defined differential pairs.
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发表于 2015-2-15 23:37
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