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标题:
Verilog 使用条件生成语句实现参数化乘法器错误
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作者:
www5201006
时间:
2014-12-2 14:41
标题:
Verilog 使用条件生成语句实现参数化乘法器错误
module multiplier ( product,a0,a1 );
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parameter a0_width=8;
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parameter a1_width=8;
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localparam product_width=a0_width+a1_width;
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output [ product_width-1:0 ] product;
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input [ a0_width-1:0 ] a0;
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input [ a1_width-1:0 ] a1;
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generate
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if ( a0_width<8 || a1_width<8 )
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cal_multiplier # ( a0_width,a1_width ) m0 ( product,a0,a1 );
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else
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tree_multiplier # ( a0_width,a1_width ) m0 ( product,a0,a1 );
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endgenerate
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endmodule
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& c" ~* m7 A5 u3 b' j' G0 p
Error: Node instance "m0" instantiates undefined entity "tree_multiplier"
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