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高速数字信号设计和高速互连0 ]# Z, L. ~ V
CHAPTER 1 Transmission Line Fundamentals.......................................... 1
/ `6 B4 N8 D3 i5 J4 h3 D3 I: z3 ?6 D* aBasic Electromagnetics.................................................................... 1
L3 S( v& d" u! }Electromagnetics Field Theory................................................... 1
4 o* B7 z! S" s+ |Propagation of Plane Waves....................................................... 6: E' _9 m! q" _" a* E
Transmission Line Theory............................................................. 10
- W, d! L- {5 S0 ]4 ]Wave Equations on Lossless Transmission Lines.................... 11
: M/ S* E& z& _1 Q3 [$ oImpedance, Reflection Coefficient, and Power Flow
1 g& m0 D! s# W: g) G* ?0 |on a Lossless Transmission Line......................................... 14
! X& w4 g1 t6 x8 dTraveling and Standing Waves on a Transmission Line ......... 16
; |; h( g' J! u7 u- ~9 U' t' jTransmission Line Structures ........................................................ 18) u. P, w6 }' F# F$ g
Stripline ..................................................................................... 19
% V* f/ v4 t" g# m: y! RMicrostrip.................................................................................. 20% I! R" m" k( r9 t% ]' R- A
Coplanar Waveguides ............................................................... 21
2 C, E* r7 [' j1 v( [# XNovel Transmission Lines ........................................................ 22
" x2 S- b/ m2 G! a) R1 ^& ~- OReferences ...................................................................................... 26) {0 V1 y4 H) m" R- O
CHAPTER 2 PCB design for Signal Integrity........................................... 27
: B; w5 ~ ~( UDifferential Signaling..................................................................... 27
5 J' c T* e8 M2 gImpedance ................................................................................. 28
" V! s& e/ o1 C9 K A/ q2 m# BTime Domain Analysis .................................................................. 315 f' v1 k& f" X
Eye Diagram ............................................................................. 31* V6 |! l$ |3 m% n0 l9 O4 F* C
Jitter........................................................................................... 33
' G0 M \+ G9 C# }Frequency Domain Analysis.......................................................... 42 C z3 g3 Y3 P2 a" I
Spectral Content........................................................................ 42
% y0 Q' m+ q# H1 m/ @( S5 @Insertion Loss............................................................................ 44
B' x# _! {8 Z" ` d) O5 Q8 t' {Integrated Insertion Loss Noise................................................ 46' L# v' `0 J: i- Y
Return Loss ............................................................................... 49
0 n! T/ r9 A3 K, @0 OCrosstalk.................................................................................... 51) K, B- D3 Q; N4 M' _
Integrated Crosstalk .................................................................. 54
% A7 ?+ R8 D3 a2 _) I( F- g, ~ vSignal-to-Noise Ratio................................................................ 55
& b2 |! v, L B- UStack-Up Design ............................................................................ 583 z4 {1 s: V; s/ k/ v7 j* b
Impedance Target (Routing Impedance) .................................. 59) Y5 U& |+ p& q2 }1 v
PCB Losses ............................................................................... 61
8 { C( z; g9 k" I, ]& ]Dielectric Loss .......................................................................... 62
: c% j, t9 I" D2 PConductor Loss ......................................................................... 65% n* L" ]7 f: S% Z6 D4 J9 o
Crosstalk Mitigation through StackUp..................................... 68( n6 `- h" I; q
Dual Stripline ............................................................................ 73
, V6 U# j9 i3 y$ L' g u/ [, xv
3 v ~0 Q) p/ o4 b/ V. }Densely Broadside Coupled Dual Stripline.............................. 84( S' F8 {7 A: @0 Z3 n
Via Stub Mitigation .................................................................. 86
9 ^- D- |& F9 WPCB Layout Optimization ............................................................. 95
( i- p$ ^ b/ m3 _Length Matching....................................................................... 96
w o4 @2 L) ^* pFiber Weave Effect ................................................................... 99. L' A! @& V' _3 {
Crosstalk Reduction ................................................................ 101) h/ h) i9 i" W: Z- ?4 k" v8 t
Non-Ideal Return Path ............................................................ 107
9 t7 }( V( I T+ Y2 G- W' t( k0 RPower Integrity........................................................................ 110
% e* r, I) {$ y. z8 a8 u- nRepeaters ................................................................................. 111
% s9 U( [& t! N/ X; ^References .................................................................................... 115
) v1 j* s! @+ A- Y# MCHAPTER 3 Channel Modeling and Simulation.................................... 117
' Y; w& ]+ n" o \& ]+ k! ^' q5 eTransmission Lines ...................................................................... 117
m- K$ u3 I. nCausality.................................................................................. 1177 p8 A( T& u2 E! N! f z) |9 [
Checking for Model Causality................................................ 118( N- B/ h. o) x/ {; |6 e( `
Causal Frequency-Dependent Model...................................... 120
" n; C$ g1 L5 A; N2 a1 m, p, jCopper SuRFace Roughness..................................................... 121/ e8 y; y5 ~7 l/ d2 z) s
Conductivity............................................................................ 1265 Q1 x2 [5 G8 f. J+ I7 I$ ^, j
Environmental Impact............................................................. 127
) D% T/ d! ]# {+ S; N2 {Model Geometries................................................................... 130
2 k- Q- u. ^7 u8 v+ t) S& V: |Corner Models......................................................................... 133* H9 g3 h% q4 E& P1 U( J5 ?
Ideal Assumptions: Homogeneous Impedance....................... 137! F8 Y6 h+ ^1 I5 F6 U9 O
Ideal Assumptions: Crosstalk Aggressors .............................. 137
) Q& T1 Z3 V, f( oTransmitters.................................................................................. 138
* x0 \+ [+ J" O2 i$ A9 }4 UIBIS Models ............................................................................ 138
8 ?% M5 g7 N" cSpice Voltage Source Model .................................................. 139
+ M, E2 w$ N% W" ]/ a2 S+ A% X3D Modeling ................................................................................ 141* |& N+ u, s6 n" j
Ports/Terminals ....................................................................... 142
: Q) U& O: q$ I/ d4 Z2 g" S0 MModel Analysis Settings ......................................................... 144
L; I4 D* {0 jPlated-Through-Hole Via............................................................. 1466 J7 s4 [2 B) q0 N5 Z4 i
Model Techniques................................................................... 147
2 u: `5 ~7 F5 x$ hPre-Layout Approximation ..................................................... 148
1 y$ Z7 @9 z5 X2 N2 M# |Pre-Layout Modeling .............................................................. 148* g" {4 _2 M8 p( X! a9 }# v
Post-Layout ............................................................................. 149
# F- G( Y8 m% a# c* WConnectors.................................................................................... 150
8 [( m2 r: w3 a: ]' X8 l. iConnector Variability.............................................................. 150
! |# z; V4 U3 {Signal Selection....................................................................... 150
& F& q0 v( y# B8 p* d0 rSeparated Via Models............................................................. 152
! V1 L, T2 g0 _& K) B# G2 k# NUnconnected Pins.................................................................... 153) r. K& B6 w2 D$ F
Physical Features..................................................................... 154# @3 @1 W2 r5 Y- y! H, d" {
Design Optimization ............................................................... 1547 |. ?5 U a) I
Packages....................................................................................... 156
2 h, ]2 W( f0 z* uC4 Escape................................................................................ 158
/ [, G) O" F+ ?0 N0 c! n5 G/ V3 ]+ C3 K6 @vi Contents
5 J9 [$ j5 M, T7 R. sTransmission Line................................................................... 158/ E; [' Q7 U5 U$ z5 S1 ]; }4 q
PTH Via .................................................................................. 1604 T; d, Z; t5 O; X% S
BGA Model............................................................................. 160
5 ]* u/ B% {- C2 ISignal Selection for 3D Package Structures........................... 161, T4 ]+ h" I9 l+ c5 v/ q
References ....................................................................................1614 ]; `9 w; p9 F! X
CHAPTER 4 Link Circuits and Architecture .......................................... 163' y% q! j' f: A7 D
Types of Link Circuit Architectures............................................163) x7 P( L$ Q* ~' b/ T# j+ e. i2 P: k" E7 N
Embedded Clock Architecture................................................ 163
d% n; x" {* W. f0 R aForwarded Clock Architecture................................................ 164
* V% N8 T* X2 S! gTermination ..................................................................................165* H' G K( }* _# Q1 c! E+ V2 a& `
DC and AC Coupling.............................................................. 165$ @3 b. V }/ u5 u4 Z
Termination Type.................................................................... 166& i: [- o' a+ \
Termination Circuits ............................................................... 167+ m7 }7 N" M$ F2 @, [% V% k: `/ b
Termination Calibration Circuits............................................ 168
& B, N y' l& [2 }5 f7 o# JTermination Detection Circuits .............................................. 169' F$ k3 w P9 k5 ]2 F" f
Transmitter ...................................................................................170) z' Z' f. b0 `3 I' L
Transmitter Equalization......................................................... 171
/ O4 H3 q. j8 d' E: P9 I4 YTransmitter Data Path ............................................................. 173
2 f$ r, C, K* B) i" k2 \0 |' o1 `8 lCurrent-Mode Driver .............................................................. 174
0 ]2 c+ ?" s# a* M" pVoltage-Mode Driver.............................................................. 1770 M' t: G* V5 A6 ]4 F
Receiver........................................................................................179$ @ r" o+ B' ^8 T% A1 i( ?
Receiver Equalization ............................................................. 180$ \: W7 p \- V4 k3 Y+ m
Receiver Data Path.................................................................. 182
# ~, B) t1 W$ ] aContinuous-Time Linear Equalizer ........................................ 184
5 M- |; v( y# i: n# N" gDecision Feedback Equalizer.................................................. 184: W4 T" e9 m8 D( ~
Data Sampler........................................................................... 186/ l% p: X Q1 ]% F
Error Sampler.......................................................................... 186* `7 }; h4 p( F4 S6 I
Receiver Calibration ............................................................... 1874 u4 t5 p+ Z" r; m# t/ O, D2 `- J4 n
Receiver Adaptation................................................................ 188
6 F5 g; T# h% o- U# TClock and Data Recovery............................................................190$ r9 G. g$ y5 B+ V5 Y# }
Clock and Data Recovery Loop ............................................. 191, J; h2 R) E0 D* ]( I
Phase Detectors....................................................................... 192
4 o m. h; {8 S9 JForwarded Clock Receiver ..........................................................195
I5 d2 F P, q0 D# yDelay-Locked Loop ................................................................ 195' J* D6 P! M- x$ \" c
Design for Test/Manufacture.......................................................1959 {+ Z5 z/ `) E P3 T7 R+ J$ X+ X* j
Analog DFx Features .............................................................. 196
) l% J0 F+ d+ H9 U8 IDigital DFx Features............................................................... 196/ ]% Z0 \' g. D- G
References ....................................................................................198
% _# \) \+ V- ~: s, C9 b9 xCHAPTER 5 Measurement and Data Acquisition Techniques............... 199+ H5 E3 j' c! t) i( E
Digital Oscilloscope Measurement..............................................199
; [! E* t6 d2 J! J; w- m7 x: VReal-Time and Equivalent-Time Sampling Scopes ............... 1993 s; E# A! W' f7 \! d
Contents vii
, g/ w$ w5 K" j/ z8 ]Bandwidth ............................................................................... 200
5 w+ \3 J2 Y7 j3 `. @Scope Digital Filter Applications ........................................... 202
( Y# I7 e7 R5 H n* ]: HTDR Measurements ..................................................................... 2041 j* ]8 r/ [6 O9 p2 I8 s
De-skew Differential Pairs with TDR .................................... 2051 a% u: D- t, U' G. Z/ S
Channel Characterization with TDR ...................................... 207
/ ?/ {9 o- ~2 p5 s* RReturn Loss Measurement with TDR..................................... 209! W3 G( X9 @! H
Vector Network Analyzer Measurement..................................... 211
3 u+ ~# V/ k# ~What is VNA?......................................................................... 211) {( x* ]3 t$ @! L
VNA Error Sources and Calibration....................................... 213* c, V& d; z7 K
Full Two-Port SOLT Calibration Procedure .......................... 217: C8 N6 r9 k/ z
Example of Measurement Using VNA................................... 217
/ l- T( b! @0 M' L+ e+ G, s; jVNA Measurement Procedure................................................ 218& ^/ o3 ^! h/ O
References .................................................................................... 219( a: L2 H: H9 p4 R3 W
CHAPTER 6 Designing and Validating with Intel Processors............... 2218 u; A! b* m/ M4 E8 C
Designing Systems with Intel Devices........................................ 221
- b; q( i* k; C, VInterconnect Model ................................................................. 2214 l. C2 m, d" e
Equalization Models ............................................................... 223( }1 e3 i$ x+ d# Q
Automatic Equalization Adaptation ....................................... 225
2 T' k: o4 t7 Z) u' q' }Performance Analysis ............................................................. 227$ Y2 F! z B( C9 f, E/ {4 I
Solution from Design of Experiments.................................... 232* M, b) g: O+ W
Solution from Typical Models................................................ 234
' z- J, h, w' k/ }- J$ u4 VSystem Validation with Intel Devices ......................................... 2372 ?( p. P& A0 ]. E# w4 N* t/ }
Power-on Preparations ............................................................ 237
# k) }- n+ \7 w1 e- m! ATypes of I/O Design Validation ............................................. 238$ R5 D! l5 C$ z$ T9 K
System Margining Validation Overview................................ 239$ s7 d8 r- T+ L( [% s
DDR System Margining Validation ....................................... 244
1 z$ F2 |9 [4 X4 J$ S DHigh-Speed Serial I/O Margining Validation ........................ 246: o1 r T7 K* [
Low-Margin Debug Guidance ................................................ 249& b! m1 O4 c0 m% N; z
Summary ...................................................................................... 250! ]: r) M2 w8 M7 i/ t
References .................................................................................... 250$ B; p) p' y7 b# w* c( p+ x5 P
Index .............................................................................................................% F- j( f1 B5 }" M; ]4 K* k7 a
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发表于 2017-7-6 14:49
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