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Introduction:8 ?# B5 W- J$ Q- @3 ?/ `, K4 t+ N
FPGA designers are faced with a unique task when it comes to designing power distribution4 A$ e* a6 s7 T+ l
systems (PDS). Most other large, dense ICs (such as large microprocessors) come with very: _' O" Z a& h
specific bypass capacitor requirements. Since these devices are only designed to implement
. F7 f/ c, X+ Q6 a5 mspecific tasks in their hard silicon, their power supply demands are fixed and only fluctuate) {( t* T# N W8 @; ^7 |
within a certain range. FPGAs do not share this property. Since FPGAs can implement an" L% } e% X. K! v7 _4 ~- E
almost infinite number of applications at undetermined frequencies and in multiple clock* L+ S0 p S' c* z& U
domains, it can be very complicated to predict what their transient current demands will be.! T+ O- i# _0 D" l8 z
Since exact transient current behavior cannot be known for a new FPGA design, the only
7 F4 V9 K9 {. W* _choice when designing the first version of an FPGA PDS is to go with a conservative worstcase
$ W; v' P- [; i- cdesign.
, c, d' {3 G- VTransient current demands in digital devices are the cause of ground bounce, the bane of highspeed
4 e! ~5 G a2 s9 r+ u+ w- d @digital designs. In low-noise or high-power situations, the power supply decoupling
8 o0 x! [% @ [1 n: nnetwork must be tailored very closely to these transient current needs, otherwise ground
, K5 o3 G% k( F! s' ]4 ?# t! \% Dbounce and power supply noise will exceed the limits of the device. The transient currents in an
+ Z* U" o4 t, T# h7 ?FPGA are different from design to design. This application note provides a comprehensive
9 A, E" x: a2 s$ |method for designing a bypassing network to suit the individual needs of a specific FPGA5 ?% }) C" e# a& E7 ]
design.- z* o# I# g$ L/ w% P7 N
The first step in this process is to examine the utilization of the FPGA to get a rough idea of its5 J/ g+ B" G5 J) W
transient current requirements. Next, a conservative decoupling network is designed to fit these
) F T# R" X3 r4 R2 prequirements. The third step is to refine the network through simulation and modification of
1 |* ]; } p( H- ~capacitor numbers and values. In the fourth step, the full design is built and in the fifth step it is" r! n" h* @1 A8 s+ P
measured. Measurements are made consisting of oscilloscope and possibly spectrum analyzer
, t3 D2 ~2 I2 F sreadings of power supply noise. Depending on the measured results, further iterations through0 V# d$ W6 j, M4 y7 ]5 N0 B. R
the part selection and simulation steps could be necessary to optimize the PDS for the specific
8 f9 l. `7 O4 i3 i: d# _& rapplication. A sixth optional step is also given for cases where a peRFectly optimized PDS is i7 z* u0 z+ O u# V1 p& u ?5 _
needed. |
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