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第二章 虚拟地址到物理地址转换* u% G( O# X6 u. `
. r1 ~' P8 D5 l# m6 s2.1 MMU 硬件VA到PA转换
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9850K 的cpu是Cortex A7的。
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3 j- w P* Q6 N7 LThe Cortex-A7 MPCore processorimplements the Extended VMSAv7 MMU, which includes the ARMv7-A Virtual MemorySystem Architecture (VMSA), the Security Extensions, the Large Physical AddressExtensions (LPAE), and the Virtualization Extensions.3 c. R N: A/ S7 S. _
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, F1 p% Z9 E; @/ W$ nVMSAv7 defines two alternativetranslation table formats:
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Short-descriptor format. _. Z6 V e; d1 j- t
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! L" k" T( r! o5 N1 X/ o' dThis is the original format definedin issue A of this Architecture Reference Manual, and is the only/ ]$ T- ?, R' c7 ~% X+ S7 q8 E
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format supported on implementationsthat do not include the Large Physical Address Extension. It
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/ d( J% G3 g% O0 w4 Zuses 32-bit descriptor entries inthe translation tables, and provides:
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1 U- T# c2 ?- X9 @! R• Up to two levels of address lookup.. U# R: T" g9 e6 @, X3 t
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, F; [2 _9 Y9 t `9 s, [• 32-bit input addresses.
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6 j) M* p- f) q# N5 S• Output addresses of up to 40 bits.* ?5 x; V5 P1 B
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• Support for PAs of more than 32 bits by use of supersections, with16MB granularity. F, I# p& @( R. N9 n/ w) M" o6 T
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. Q3 b8 v4 ?0 U& v# o6 {• Support for No access, Client, and Manager domains.
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. Z1 J: L2 P( m3 G! X! x9 R) h• 32-bit table entries.8 w1 Z. M8 R [1 T
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# O- z9 a( i- q' \( ?Long-descriptor format8 \$ j- f8 ~1 y7 I- j+ e
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