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补丁包更新列表!
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DATE: 11-20-2015 HOTFIX VERSION: 061
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CCRID PRODUCT PRODUCTLEVEL2 TITLE4 H: i( _$ w: j. t7 V' E2 d
===================================================================================================================================4 Y9 u y* m- D* [( W
1306441 APD OTHER The Minimum Shape Area option in Layer Compare uses an unspecified value4 w% ]7 y i# u; r, E) m* O$ ^, S% o7 Q( n
1342644 ADW COMPONENT_BROWSE Need directive or method for Component Browser to load a search criteria file upon init9 N0 T+ X# X: Q! y
1413248 concept_HDL CORE Import from another TDO project makes the block read-only
/ P$ `( K- t+ H1417429 allegro_EDITOR INTERACTIV Pick box only accepts 1 set of values. You need to close the box and reopen it to draw a rectangle2 _. g7 i6 M1 i" L: M0 Y# m
1417442 ALLEGRO_EDITOR INTERACTIV Spin via stack and only part of the stack spins" m5 Y# P/ m, Z3 ?$ z4 e/ q" I
1451977 CONCEPT_HDL PDF Origin of PDF mediabox not starting at (0,0) when PDF page_height and page_width are set
' }0 A. `# y3 M5 p0 i1 Y7 m: @1453527 ALLEGRO_EDITOR EDIT_ETCH Contour route hugs the outer edge of the route keepin
2 v, `" |2 |4 ]" f; i3 ?2 R1464948 PCB_LIBRARIAN VERIFICATION The errors/warnings do not match between the various tools0 C; v# [# n% ^% ^; c) o( j) l& K
1467826 CONCEPT_HDL PDF PublishPDF from Console Window creates a long PDF filename
0 g3 v9 `4 `( A! J1478639 CAPTURE OTHER Capture Browse Nets window does not display all nets
5 e0 z8 u' X, D# B. r1479177 SIP_LAYOUT OTHER Pin pair constraints do not appear to be supported in Sip Layout XL3 s0 a3 B$ E% c: t. c$ F
1479227 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule flagging invalid voltage in hierarchy
$ ~& {) l4 u/ K1479454 CONCEPT_HDL OTHER DE-HDL issue: locked DIFF_PAIR property is editable
^4 y1 G2 {- X' ~1480293 CAPTURE PROJECT_MANAGER Capture hangs when searching for all nets6 r9 E, R+ p1 H
1483894 CONCEPT_HDL CORE Import Design hangs when pull-down arrow is clicked twice3 B& ~( n" M7 m! G9 S# T! J
1484781 CONCEPT_HDL CORE Three different Hierarchical Viewer issues
' v" {: i$ x( L. k; X1485059 PCB_LIBRARIAN CORE Part Developer pin attributes are randomly marked as read-only! p& j) h, Z: i- q; b$ u ~
1485960 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule is crashing the project, V. y# p* D' T! }$ N/ v
1486086 ALLEGRO_EDITOR ARTWORK Cannot generate artwork.9 e0 S6 Q2 n! D/ q* R
1486834 CONSTRAINT_MGR OTHER Restore the Status column in cmDiffUtility$ ]9 J9 b4 V1 o$ f& P4 R C
1487085 CONCEPT_HDL CONSTRAINT_MGR Import Physical with the Constraints only option reports problems
+ I0 C, l7 _, l7 D6 W& U1487197 ALLEGRO_EDITOR DRC_CONSTR Drill to Via DRCs are not being reported3 n1 j% D% o+ N4 A0 q' S
1487265 CONCEPT_HDL CORE Replace command in Windows mode shows incorrect behavior/ L6 W) N5 H/ p( _( s
1487733 CONSTRAINT_MGR OTHER Running Export Physical - It takes over two hours to update the PCB Editor board7 N! K" U$ L4 F i4 P1 W
1488758 CONCEPT_HDL CONSTRAINT_MGR CM_VALIDATION_ON_SAVE should be a hard stop on Constraint Manager1 Y) B- k7 E+ Z; F$ b- n6 Y H
1490299 SCM OTHER ASA does not update revision properly0 ^- E/ ^: a' |' D9 Q# I
1490744 ALLEGRO_EDITOR skill axlChangeLine2Cline changes line to cline and places it on the TOP layer+ c& m" y* C) Z( b, A
1490924 F2B PACKAGERXL Save Design/Export Physical is resetting Via constraints
p" q/ T+ S. W) Y1491351 ALLEGRO_EDITOR OTHER Create Detail for bond fingers on a custom layer not working
; B7 v- q% D. d, X5 n1492595 ALLEGRO_EDITOR MANUFACT Dimension character substitution help is wrong# _4 q) ^8 ^+ s# q
1492777 ORBITIO ALLEGRO_SIP_IF OrbitIO import of customer mcm results in crash2 \3 m. t% D% _) L' c, A
1492901 CONCEPT_HDL CORE Cannot instantiate a multi-sections symbol (> 10 versions) in Design Entry HDL) Z& i$ K+ b' J6 A% ]
1495621 ALLEGRO_EDITOR INTERFACES Oval pins are placed with wrong orientation in IPC2581
2 e( m @* y/ b; O0 y1497597 ALLEGRO_EDITOR DATABASE Show Element on pin shows wrong drill size3 p0 G7 ]5 B/ Z- o. V
1497956 CONCEPT_HDL CORE ADW Library Flow test schematic generation crashes DE-HDL while saving the design when using customer adw_conf_root
% O" {: Y4 X: I5 T2 m: g$ E! }1498234 ALLEGRO_EDITOR ARTWORK PCB Editor fails to create artwork and no error is listed in the log file6 [. T2 V3 o9 i; B/ t
1499363 CONCEPT_HDL CORE Custom attributes under variant management stopped working in Hotfix60
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H5 ?3 W3 h, f最新破解包列表!
# A+ j* g; l5 I0 p------------------------------------------------------------------------------8 P+ e% d& J& Q- M: l8 W+ a
SPB 16.6 UPDATED KITS RELEASE: ISR 16.60.061 EST.DATE: 11-20-20150 ~4 O/ I3 F$ C5 M4 _' I
------------------------------------------------------------------------------
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DSCoreUtils16.60-s077wint) L" V: E6 r2 X" M2 C1 ~
DSCore16.60-s055wint
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DSTableEditor16.60-s018wint) U* E6 F1 H) C$ G
DSTextEditor16.60-s015wint
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adwLRM16.60-s033wint' J m# R; y: Z+ D, I- i
adwSDM16.60-s044wint
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algroArtwork16.60-s122wint4 |) D1 Q! g6 C6 F) T+ y
algroAxl16.60-s048
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algroCxt16.60-s077
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algroDsign16.60-s122wint" d5 u6 X, U- }5 [; r& B
algroF2B16.60-s122wint" O- U! S/ S' [- o: _
algroIDF16.60-s122wint
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algroNetin16.60-s122wint, `. b& b5 {; g2 S8 p: ?" K- G
algroPlace16.60-s122wint4 |/ w: I! B; }: t
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algroStrm16.60-s122wint' _6 A! |0 f. ~! t2 b; e- g
algroTextIndep16.60-s089
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algroUtlty16.60-s122wint" c" I1 y% c5 \3 N: U* C7 P
bom16.60-s030wint- q5 { v6 @, n3 ]
capPSpLibMAB16.60-s018wint
8 ]) J8 D. r5 VcapProg16.60-s044wint
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concptSetup16.60-s015wint
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desSync16.60-s019wint
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fetBase16.60-s034wint
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; Z0 Y8 j2 u( R. s* Q% Liff2hdl16.60-s010wint
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lman16.60-s023wint
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pspProg16.60-s043wint
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spbFPGAPlanner16.60-s065wint
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补丁包种子!5 R" c9 r' O: a9 w, {2 g: p& ]$ L
cadence.spb.orcad.16.60.061.hotfix.rar
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