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http://dl.vmall.com/c0fu1auqa8) V- |: B" m5 K9 j8 ~
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& S" a: h) b$ @8 o7 {) nDATE: 02-14-2014 HOTFIX VERSION: 023
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
0 k. ]! i1 R! I===================================================================================================================================
7 {0 |# Z4 ?7 x7 @3 V& {7 o; i- v1120183 F2B DESIGNVARI Variant Editor Filter returns incorrect results.0 k$ s$ E* A; O, X/ {/ M, f
1202715 SPIF OTHER Objects loose module group attribute after Specctra& ?8 g' a' C& R$ {; l4 U
1203443 ADW LRM LRM takes a long time to launch for the first time0 K- z9 z# f) H- C
1207204 CONCEPT_HDL CORE schematic tool crashed during save all( D# |! e4 W# \3 u
1222101 CONCEPT_HDL CORE Pins are shorted on a block by the Block's title delimiter
4 i- B& F7 o8 y1 t- e: f2 l" n; O$ c0 g1223709 FSP FPGA_SUPPORT Need FSP model of Altera 5AGZME3E3H29C4 FPGA
) @# ]4 i% h$ f! P5 I1224025 ALLEGRO_EDITOR INTERFACES The 3D viewer when working on a brd file shows package placed on BOTTOM side of my board while it is present on TOP side) ^: B+ i$ @+ o
1225591 F2B PACKAGERXL Aliased net signals starting with equals sign are not resolved correctly in cmgr: v+ N5 \/ m8 p" k1 U& e3 a
1226480 ALLEGRO_EDITOR EDIT_ETCH Routing time is took to double increase when using the Add Connect because DRC is Allowed.5 o4 g w" R8 p8 I* `6 s& o
1229234 FLOWS PROJMGR Can't open the part table file from Project Setup
' A: J. f1 K; L0 t" |& S1 Z1229555 ALLEGRO_EDITOR ARTWORK IPC-2581 not recognizing pin offsets correctly.
4 ?' f! k9 j& R; r1229610 FSP FPGA_SUPPORT New FPGA device request - Altera Cyclone V ST: 5CSTFD6D5F31I72 w7 w7 U( X% j5 a# `% j* Y
1229664 ALLEGRO_EDITOR SHAPE Shape not voiding different net pins causing shorts with no DRC's
, T6 J0 z( \# Y) D" s8 X1232601 ALLEGRO_EDITOR MANUFACT Cannot add test point to via on trace.8 v9 m( s: P: w2 I$ u0 G
1232772 ALLEGRO_EDITOR DATABASE When applying a place replicate module Allegro crashes
2 \* R6 z5 p r( x5 @7 P1233216 SIP_LAYOUT DIE_ABSTRACT_IF Allow more than 2 decimal places for the shrink facor in the add codesign form$ {5 m. l) n* v9 o+ [* K
1233690 PDN_ANALYSIS PCB_STATICIRDROP PDN IRDrop: Mesh mode in Report is incorrect.
$ t( I- U6 G8 N, X8 \8 C1233977 ALLEGRO_EDITOR INTERFACES single shape copied and rotated fails to create when importing IDX
; P) h/ P, b' d1234357 SIP_LAYOUT SCHEMATIC_FTB DSMAIN-335: Dia file(s) error has occurred.
2 N3 g& K! e* w& r" a1234450 ALLEGRO_EDITOR INTERFACES clines, pads, etch shapes to be at the same level with the board when viewed in STEP viewer.: P) U5 [1 F! s$ ~2 I
1235587 PSPICE MODELEDITOR PSpice Model Import Wizard does not display symbol graphics for DE-HDL Symbol e& b8 e& ]/ B) H4 o
1236571 ALLEGRO_EDITOR GRAPHICS Allegro display lock up and panning issues
8 q. Y/ ?8 A, C8 ]6 x* N1237415 ALLEGRO_EDITOR INTERFACES Multidrill pad is exported with single Drill in the STEP File6 x u W' h# A' a( Q ^
1237807 ALLEGRO_EDITOR SCHEM_FTB The line feed code of netview.dat |
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发表于 2014-2-18 16:44
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