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本帖最后由 partime 于 2016-3-15 20:20 编辑
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真是够了,这么快又出补丁了。这次还fix了不少bug,这个补丁还是需要打的。下面放出链接,回复可见
6 ~1 }8 H- N0 w( @# O2 y( o& Xhttp://pan.baidu.com/s/1gdRQM1l
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1 r( V6 t- ~) M; \( t Z" k( F* W& g这里是CCR。! b/ D- t+ K1 ^7 Y
) G' U8 J2 f$ C- K1 dDATE: 03-11-2016 HOTFIX VERSION: 0676 K+ |% @+ l1 F( \
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CCRID PRODUCT PRODUCTLEVEL2 TITLE: _) D4 N7 T2 p% _* x
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1482953 allegro_EDITOR DATABASE Part change disassociates parts from Group7 L$ |& R4 d5 G& ?9 P7 n# J
1484075 ALLEGRO_EDITOR pads_IN 'pads_in' imports ASSEMBLY_TOP and PLACE_BOUND_TOP outlines that are defined as shapes as lines
2 ^* o- [8 r1 U; c# Y, X1519155 ALLEGRO_EDITOR OTHER IPC-2581-B Negative Plane Error6 `0 w# G+ `* S8 B
1528075 concept_HDL OTHER Auto Generate: DML model assignment fails with error 'There is PHYS_DES_PREFIX property in PTF file.'
) w9 ^+ d$ u: N! f4 O3 V1528398 ALLEGRO_EDITOR SCHEM_FTB Problem with pin number format used in NC property2 c0 |; ~+ y+ U
1529178 SIG_EXPLORER OTHER Values not transferred correctly for PinPairs when created ECSET from a net
3 p" ~( d6 M5 d9 W3 Y1529720 CONCEPT_HDL COPY_PROJECT Running ADW copy project does not update the 'master.tag' file
3 k! R2 ^$ {5 Q- w+ _1530707 CONCEPT_HDL CORE Request to recover a 16.6 design after DE-HDL crashes
3 b. P, z2 {& `, c1532124 CONSTRAINT_MGR SCM 'File - Export - Technology file' in Constraint Manager crashes SCM if .tcf file is missing
* \- U" P" L" l3 m! t1532788 CONSTRAINT_MGR OTHER Pin pair is hidden when Highlight Filter is ON in Constraint Manager
6 |9 ?" M" C, z' f# ^) Z- n- |1536912 CONCEPT_HDL CORE Customizing keys in DE-HDL - Disallow mapping a command to alphanumeric characters. p2 i# F' E6 O' r; S& v1 h9 X
1537055 CONCEPT_HDL CHECKPLUS Rules Checker - POWER_PINS value not obtained when schematic instance has the POWER_PINS and POWER_GROUP properties
O7 Z, @! x+ A; j1 I1537278 SIG_EXPLORER SIMULATION SigXplorer (Allegro Sigrity SI) crashes when simulation is viewed in SystemSI Waveform Viewer9 g' D* p% `7 t4 x, z0 [! r; [3 k( T
1537339 CONCEPT_HDL INTERFACE_DESIGN No warning is flagged when moving a Net Group over a net
7 z8 p5 B( g; [8 @2 Q. v1537521 FLOWS PROJMGR Do not allow project creation if there are spaces in directory or file names on the Linux platform( m3 F: |7 n8 J; i
1539227 CONCEPT_HDL CORE Renaming a page from the hierarchy browser crashes the schematic editor.
3 E; ?# u& A' y' y* o! |4 `2 N8 I1541532 SCM SCHGEN Generate Schematics crashes with 'Out of Memory' error9 T# r# ^: r7 E) ^- J9 M: q5 O
1541589 ALLEGRO_EDITOR INTERFACES STEP model incorrectly shown in 3D viewer. Shows pins as angled./ v+ Z$ n( E6 f+ [
1541680 CONCEPT_HDL DOC A dot (.) or period in design name created 2 separate design folders in worklib
& Z) b" _$ C4 v9 H- u( _1541687 ALLEGRO_EDITOR PADS_IN PADS closed polygons are imported as lines4 P: F+ T9 `! r
1542722 ALLEGRO_EDITOR INTERFACES IDX export: RefDes and PART_NUMBER missing for mechanical symbols: G; ? r+ W! p2 e- X
1542817 ALLEGRO_EDITOR DATABASE Import Netlist not getting completed on specific board
8 L* j& n; N' D \1544060 SCM SCHGEN Generate Schematics causes Allegro System Architect to crash
1 S# }! \/ c7 s1544633 APD STREAM_IF The 'stream out' command causes Allegro Package Designer to crash9 W% C' F& w* W" }
1544698 ALLEGRO_EDITOR PLACEMENT 'place replicate' does not add clines and vias to fanouts if fanouts are marked; X/ l. V& x* V) G" g) Q
1544859 APD PARTITION Timing vision menu is missing in APD/SIP partitions.
3 a0 T# B+ x' ]1545136 ALLEGRO_EDITOR PLACEMENT All fanouts are marked as part of one symbol instead of the symbols they attached with
( V' G3 h& n1 c1545370 APD OTHER Pads in .mdd file getting placed on different layers as compared to the design
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补充内容 (2016-4-5 21:12):
, L. K/ P: T* k6 u- {! @068的hotfix已经出来了。这个就关掉了吧,链接已经失效~~~ D* S7 X, \9 M5 V
% Y$ k+ c* p) r5 t补充内容 (2016-4-11 19:50):* J0 h( e" s& [, k; z! Y
068的hotfix请移步到这https://www.eda365.com/thread-132946-1-1.html& M# t+ [3 s3 n8 o& X* {- q p
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补充内容 (2016-7-15 20:46):* k9 E4 G, e4 W! j+ N
https://www.eda365.com/thread-135499-1-1.html( C" k$ k2 r8 E0 [5 V* O
S071的补丁 |
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