请教一个关于modelsim仿真的问题，路过大神进来帮帮小弟，谢谢！

pipiliang · 发表于 2013-7-21 00:04

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我在用modelsim仿真按键去抖动的时候，仿真图形出现1ns的未知状态，下面上图，谁解释一下，谢谢

pipiliang · 发表于 2013-7-21 00:06

下面贴上源代码！
`define UD    #1

module KEY_TEST
(
//Input ports.
SYSCLK,
RST_B,
KEY_B,

//Output ports.
LED_B
);

//===========================================================================
//Input and output declaration
//===========================================================================

input    SYSCLK; //System clock, 50MHz.
input    RST_B; //Global reset, low active.
input    KEY_B; //Key input, low active.

output    LED_B; //Led output, low active.

//===========================================================================
//Wire and reg declaration
//===========================================================================

wire    SYSCLK;
wire    RST_B;
wire    KEY_B;

reg    LED_B;

//===========================================================================
//Wire and reg in the module
//===========================================================================

reg [19:0] TIME_CNT; //Counter, count press key time.
reg [1:0] KEY_REG; //Save the input one cycle every 20ms.
reg LED_B_N; //Next value of LED_B.

wire [19:0] TIME_CNT_N; //Next value of TIME_CNT.
reg [1:0] KEY_REG_N; //Next value of KEY_REG.

//===========================================================================
//Logic
//===========================================================================

//Count the time the key is pressed, free running.
always @ (posedge SYSCLK  or negedge RST_B)
begin
  if(!RST_B)
TIME_CNT  <= `UD 20'h0;
  else
TIME_CNT  <= `UD TIME_CNT_N;
end

//Count cycle 20ms
assign TIME_CNT_N = (TIME_CNT == 20'hf4240) ? 20'h0 : TIME_CNT +1'h1;

//Save the key value when some key is press.
always @ (posedge SYSCLK  or negedge RST_B)
begin
  if(!RST_B)
KEY_REG <= `UD 2'h3;
  else
KEY_REG <= `UD KEY_REG_N;
end

always @ (*)
begin
  if(TIME_CNT == 20'h0)
KEY_REG_N = {KEY_REG[0] , KEY_B};
  else
KEY_REG_N = KEY_REG;
end

//Output control.
always @ (posedge SYSCLK or negedge RST_B)
begin
  if(!RST_B)
LED_B    <= `UD 1'h1;
  else
LED_B    <= `UD LED_B_N;
end

always @ (*)
begin
  if((KEY_REG == 2'b01) && (TIME_CNT == 20'hf4240))
LED_B_N = ~LED_B;
  else
LED_B_N = LED_B;
end

endmodule

pipiliang · 发表于 2013-7-21 00:12

另外，此程序是利用延时20ms的方法实现按键去抖动的，它是每隔20ms采样一次键值，我的疑问就是，它会不会刚好在20ms的时候，按键正在抖动，恰好把抖动的键值给采样了？

pipiliang · 发表于 2013-7-21 10:48

来人啊！怎么没人哦！

zgq800712 · 发表于 2013-7-27 08:55

always @ (posedge SYSCLK or negedge RST_B)
begin
if(!RST_B)
***********************************

应该是和这个有关系

tsw446507564 · 发表于 2013-11-19 09:17

你检查一下always或者是initial这里面的敏感参数列表，如果一开始不能有触发状态可能导致未知状态出现

lvsy · 发表于 2014-1-22 09:58

你的设计是不是可以改成这样？
always @ (posedge SYSCLK  or negedge RST_B)
begin
  if(!RST_B)
TIME_CNT  <= `UD 20'h0;
else if(TIME_CNT == 20'hf4240)
TIME_CNT  <= `UD 20'h0;
else
TIME_CNT  <= `UD TIME_CNT +1'h1;
end

//Save the key value when some key is press
always @ (posedge SYSCLK  or negedge RST_B)
begin
  if(!RST_B)
KEY_REG <= `UD 2'h3;
  else if(TIME_CNT == 20'h0)
KEY_REG <= {KEY_REG[0] , KEY_B};
end

//Output control.
always @ (posedge SYSCLK or negedge RST_B)
begin
  if(!RST_B)
LED_B    <= `UD 1'h1;
  else  if((KEY_REG == 2'b01) && (TIME_CNT == 20'hf4240))
LED_B    <= `UD ~LED_B;
end

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请教一个关于modelsim仿真的问题，路过大神进来帮帮小弟，谢谢！

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