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高速数字信号设计和高速互连' k0 ]/ T, ~5 g* n1 \% X6 u. X$ N
CHAPTER 1 Transmission Line Fundamentals.......................................... 1
9 k$ Y- a7 t6 e. pBasic Electromagnetics.................................................................... 1
l% Y" [$ T% S& \5 _Electromagnetics Field Theory................................................... 1
$ \: g1 _' Y1 Y* ?1 |1 EPropagation of Plane Waves....................................................... 6$ Q3 y& N) K Y7 k8 L
Transmission Line Theory............................................................. 108 C8 X8 N% ]" h
Wave Equations on Lossless Transmission Lines.................... 11
4 Z/ R* a" C5 n9 ?8 a8 j* q' ZImpedance, Reflection Coefficient, and Power Flow
* D1 l& p5 R4 c. H- Yon a Lossless Transmission Line......................................... 14
F( U% A: L! E* \: JTraveling and Standing Waves on a Transmission Line ......... 16
0 I+ r) y% B$ K& S' ?/ E/ W' tTransmission Line Structures ........................................................ 18, o0 q# v$ n5 y
Stripline ..................................................................................... 19
5 U( o a$ v0 |$ SMicrostrip.................................................................................. 20
2 z; Q. U0 l# |& I5 U2 V4 hCoplanar Waveguides ............................................................... 21, ?$ j. R. Z9 y
Novel Transmission Lines ........................................................ 22; u1 b3 A: E# S# ?
References ...................................................................................... 26! m3 D& v* Z V* ?) |2 u2 k: G
CHAPTER 2 PCB design for Signal Integrity........................................... 27
/ V3 N" x8 ~( dDifferential Signaling..................................................................... 27
- H8 ^+ b7 Y# e# }: A8 }: N' UImpedance ................................................................................. 28; b* w0 I& Y; o2 t P" s
Time Domain Analysis .................................................................. 319 S! M z# v y% X+ Q" Q. \3 d
Eye Diagram ............................................................................. 31
7 x) L. ^9 N- C/ _% g$ {$ j) jJitter........................................................................................... 33
& |0 A' l. T* N9 c4 W7 M. KFrequency Domain Analysis.......................................................... 42$ Y+ s, |& f; s0 I
Spectral Content........................................................................ 42
9 O+ |& ^0 z9 w6 N' |8 p* l8 xInsertion Loss............................................................................ 44& p0 Q% x/ {. ~9 Y* P/ y
Integrated Insertion Loss Noise................................................ 46/ f- C8 v8 ?) P6 G- m* `, N$ o
Return Loss ............................................................................... 49
9 d. ~) ]7 D, f7 K5 N/ ?Crosstalk.................................................................................... 51$ O0 h# M- l; E1 p& k
Integrated Crosstalk .................................................................. 54! |( K, t, N" h1 \
Signal-to-Noise Ratio................................................................ 55
/ E# Q. V! b8 ?2 K: u( z1 _/ PStack-Up Design ............................................................................ 58
% f6 H0 c9 ]2 C* K q+ R* F+ WImpedance Target (Routing Impedance) .................................. 59, d% s z" C- ]
PCB Losses ............................................................................... 61
4 W, ?+ l3 p% a4 K6 y5 r1 WDielectric Loss .......................................................................... 62
4 O7 f4 F3 c6 D! o+ E* v& F, N, GConductor Loss ......................................................................... 652 p5 f5 o( U+ N( H' z
Crosstalk Mitigation through StackUp..................................... 68: {; K$ [) J% C7 K7 [- p
Dual Stripline ............................................................................ 73
: a3 {1 ^' j+ p0 m- qv
9 a; q! _9 L) ]: dDensely Broadside Coupled Dual Stripline.............................. 84
- N4 |$ V6 `2 WVia Stub Mitigation .................................................................. 86. @( V; t5 U9 v
PCB Layout Optimization ............................................................. 95
+ j( P5 T8 K, OLength Matching....................................................................... 96
( ~5 ]: S) ~2 |# p9 b7 X8 h8 w3 IFiber Weave Effect ................................................................... 99; r C2 D0 e& r7 u/ i
Crosstalk Reduction ................................................................ 101
6 L+ T& e# i: t1 @Non-Ideal Return Path ............................................................ 107. o+ F3 u4 X& j) {
Power Integrity........................................................................ 110' P7 ?4 x! N1 q2 a; T1 l6 B
Repeaters ................................................................................. 111& ^3 b) ], @8 ]# D
References .................................................................................... 115' F, S6 [( e0 ^) r6 p, p6 g3 }
CHAPTER 3 Channel Modeling and Simulation.................................... 117
( C8 s2 Z! Q* w8 C2 x$ ATransmission Lines ...................................................................... 1179 Z( w% ?6 d4 {* h
Causality.................................................................................. 1176 g9 S& i) v3 T3 ?1 k8 s8 h
Checking for Model Causality................................................ 118
2 b6 `* P2 v. R/ I3 @( ICausal Frequency-Dependent Model...................................... 120
3 A6 p: D) k% p+ p# z. PCopper SuRFace Roughness..................................................... 121! _$ s/ H2 P% {) k% y6 |
Conductivity............................................................................ 126
" a/ S$ n! D9 }* m. ^7 `8 SEnvironmental Impact............................................................. 127
4 W9 J8 v9 T Q. b( G9 eModel Geometries................................................................... 130
! x6 F& u9 v B4 A2 E' ZCorner Models......................................................................... 133; _. V: Z( {5 v8 B& X
Ideal Assumptions: Homogeneous Impedance....................... 137/ O) L( V2 O4 l4 s8 r
Ideal Assumptions: Crosstalk Aggressors .............................. 137
( m0 y3 c' f+ G% I$ _Transmitters.................................................................................. 138
2 y" d( u3 R* BIBIS Models ............................................................................ 138
/ O% D/ ]; ?& D+ k8 K, i; DSpice Voltage Source Model .................................................. 139
1 ~0 b h4 {: Y( z0 `, `3D Modeling ................................................................................ 141$ S! R+ g. s V3 w6 X/ F; S
Ports/Terminals ....................................................................... 142
. f2 c( q1 }5 O* e A( q8 m) kModel Analysis Settings ......................................................... 144' r L0 G/ k+ |8 t6 X; b
Plated-Through-Hole Via............................................................. 1465 F4 o4 Z$ `. v: z0 b$ c
Model Techniques................................................................... 147
, U9 y# @# U" E4 V9 \Pre-Layout Approximation ..................................................... 1483 I/ z; D; X) s
Pre-Layout Modeling .............................................................. 1482 @, V: _! c7 R7 N
Post-Layout ............................................................................. 149
- t4 \' i* ^9 u; i: `Connectors.................................................................................... 150
, G {) d% P: c" [' [Connector Variability.............................................................. 150& Z( Q" ~0 X) R% s7 _0 L" g( t& A0 r- R
Signal Selection....................................................................... 1500 g2 P) Q: f2 h5 j0 p2 |; q
Separated Via Models............................................................. 152
2 M" \% u+ B% E8 uUnconnected Pins.................................................................... 153+ w% K# _) d( |. F
Physical Features..................................................................... 1543 p' B) @0 Q% ~: x0 p
Design Optimization ............................................................... 1542 D V; z G. \0 g
Packages....................................................................................... 156
' \' W& d4 m/ {C4 Escape................................................................................ 158. h) y, {! n: X# r- O
vi Contents/ Y+ i( P% e7 p' d% Y [
Transmission Line................................................................... 158
! t' J* t: j/ u9 v+ d! ~PTH Via .................................................................................. 1604 B) @/ e% O: X1 S ^
BGA Model............................................................................. 160
2 S( y# R, e. l: VSignal Selection for 3D Package Structures........................... 161
0 j% B6 b3 B. H! g! N+ YReferences ....................................................................................161, K! h2 d$ m" g
CHAPTER 4 Link Circuits and Architecture .......................................... 163
$ C( M& ^% |+ nTypes of Link Circuit Architectures............................................163
: ]5 a- B: p/ n1 {! ]3 X& W- XEmbedded Clock Architecture................................................ 163- C; [& J8 m) f& J: u
Forwarded Clock Architecture................................................ 1649 ^$ [6 O- V" ]: V! U
Termination ..................................................................................165
4 U. L* D$ _- s9 f3 VDC and AC Coupling.............................................................. 1650 R2 n& \, o% y1 N$ D( d, T
Termination Type.................................................................... 166
* o1 E/ r Y" QTermination Circuits ............................................................... 1677 o( z( h9 i- ]9 n9 X
Termination Calibration Circuits............................................ 168
8 V4 I. W+ B7 |+ B2 PTermination Detection Circuits .............................................. 169
; ~' l$ `$ k4 L8 c1 G# rTransmitter ...................................................................................170/ ~, o$ Q; a: A0 B
Transmitter Equalization......................................................... 1711 P) }$ w! ?+ _: N' M# V0 S
Transmitter Data Path ............................................................. 173
% a/ V' b; h N k4 j% ]Current-Mode Driver .............................................................. 174: b' C2 n( L! K$ M- S
Voltage-Mode Driver.............................................................. 177
' S: [0 Z) g+ e4 e2 f3 ^) lReceiver........................................................................................1792 @2 G: ?! d% }' ~6 v
Receiver Equalization ............................................................. 180
- H, {) C8 S, e# F8 R1 JReceiver Data Path.................................................................. 182
* n3 S# L8 N. \/ D# [Continuous-Time Linear Equalizer ........................................ 184) o2 o6 E) D1 k4 v) G
Decision Feedback Equalizer.................................................. 184
+ x( X. h9 Q% B4 M/ j1 qData Sampler........................................................................... 186
" `1 @ M$ z m4 L0 ~1 gError Sampler.......................................................................... 186+ |/ U6 R+ G; y! `- `) c
Receiver Calibration ............................................................... 1871 K! M& E4 ?+ q1 Q: W! v
Receiver Adaptation................................................................ 188
+ Q4 l6 x+ V4 S" l" bClock and Data Recovery............................................................190
5 a+ r( U4 X" U( _/ QClock and Data Recovery Loop ............................................. 191, ~" [2 N. Q/ n7 ~
Phase Detectors....................................................................... 192
z& w# A3 S# v% a6 rForwarded Clock Receiver ..........................................................195) Q+ Z% \% J2 j! x3 f" o
Delay-Locked Loop ................................................................ 195
. i7 H4 z3 x* \0 T- \Design for Test/Manufacture.......................................................195- v% d: U, _; `7 J4 o, B; L6 b+ Z
Analog DFx Features .............................................................. 196
; f" h9 e: U! _2 ]6 c3 v: NDigital DFx Features............................................................... 196
( f1 i% p$ c0 f$ Y/ qReferences ....................................................................................198+ d T: x: t% h2 K9 D8 q
CHAPTER 5 Measurement and Data Acquisition Techniques............... 199
7 ~9 j7 m: @: Z: w$ C* {+ GDigital Oscilloscope Measurement..............................................199$ W% y3 x' h( g& y" X3 g' P
Real-Time and Equivalent-Time Sampling Scopes ............... 199
) g* j" U7 m* n8 f8 yContents vii: {" C5 T* [3 o1 m! D" c4 B- a
Bandwidth ............................................................................... 200
, M$ G1 d) L7 l0 IScope Digital Filter Applications ........................................... 202
2 d4 V, C f1 I. }TDR Measurements ..................................................................... 204
) w8 g: E# P! ?5 h% ~De-skew Differential Pairs with TDR .................................... 205+ ], N. r$ I0 `" v
Channel Characterization with TDR ...................................... 207
) {# t0 w. T e. x) {Return Loss Measurement with TDR..................................... 209
# e& C g t M6 r2 x7 w0 [! |; IVector Network Analyzer Measurement..................................... 211
: ?& h T# j3 O2 _What is VNA?......................................................................... 2118 ]! ~/ d& ]/ p
VNA Error Sources and Calibration....................................... 2130 L) t' w C/ ~$ h
Full Two-Port SOLT Calibration Procedure .......................... 217, E7 J0 c) K+ C; A0 K2 d7 C, N1 K4 r
Example of Measurement Using VNA................................... 217
7 n5 Y7 M4 H' C2 [VNA Measurement Procedure................................................ 218% a1 w* U$ X2 K, Z' g0 _* q
References .................................................................................... 219
, L$ @$ g# B+ ~CHAPTER 6 Designing and Validating with Intel Processors............... 221' A' @" R8 R3 z q$ g; U7 q. I6 g: O
Designing Systems with Intel Devices........................................ 221
) C3 g4 E) A0 m$ ?0 P" h8 J+ i6 o+ V. vInterconnect Model ................................................................. 221 P4 e9 \2 J+ N0 R
Equalization Models ............................................................... 223" j" a- B* Y7 g% x
Automatic Equalization Adaptation ....................................... 225! a0 L! M' L5 H' Q
Performance Analysis ............................................................. 227
& j% ?9 A% S- L" v) @+ a4 S3 lSolution from Design of Experiments.................................... 232
" ^: n1 f1 g( @! n0 TSolution from Typical Models................................................ 234
1 K8 q5 O: ?: a( P4 @System Validation with Intel Devices ......................................... 2378 A) p$ K6 ]: p; b* f% X
Power-on Preparations ............................................................ 237
6 R+ g9 Y* M; c' y6 A; uTypes of I/O Design Validation ............................................. 238
( O( Y4 U4 s, }6 Q' YSystem Margining Validation Overview................................ 239$ J' J( L. U5 M: k1 n
DDR System Margining Validation ....................................... 244
. K: E7 i: W' p, H( b, k2 W0 y; eHigh-Speed Serial I/O Margining Validation ........................ 246
0 c. w1 u* U( |: t0 G: x. MLow-Margin Debug Guidance ................................................ 249: [( T; U* X& H+ \
Summary ...................................................................................... 250( X+ a7 N1 S; N8 Z3 Y* s$ L
References .................................................................................... 250" B) B0 g: u/ q. d/ `# A, f
Index ............................................................................................................./ G7 {1 y$ z E
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