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Introduction:
" N r' T/ b' z. l% d" P FPGA designers are faced with a unique task when it comes to designing power distribution# n, M. E' b% L" s3 n
systems (PDS). Most other large, dense ICs (such as large microprocessors) come with very
- I2 u+ I& h1 V5 y* k; o8 tspecific bypass capacitor requirements. Since these devices are only designed to implement2 V3 w/ v( ]& k# {2 n
specific tasks in their hard silicon, their power supply demands are fixed and only fluctuate
+ ~- o& |1 K( \% b4 r% A" Q' {within a certain range. FPGAs do not share this property. Since FPGAs can implement an! K# C: |+ V4 I# m8 ~ i- |! k9 Q
almost infinite number of applications at undetermined frequencies and in multiple clock
" I/ ^: T# K( e& L; D# Udomains, it can be very complicated to predict what their transient current demands will be.
, j- F$ o4 ^$ P' D( E$ [$ gSince exact transient current behavior cannot be known for a new FPGA design, the only2 B, \3 a/ ]4 Z/ k9 u/ R0 S
choice when designing the first version of an FPGA PDS is to go with a conservative worstcase8 [& k n2 C2 D; R2 c% y. g8 `
design.$ b- y3 x" R/ ^
Transient current demands in digital devices are the cause of ground bounce, the bane of highspeed
/ b& r. G' |' xdigital designs. In low-noise or high-power situations, the power supply decoupling
8 r3 t7 G" _7 u8 f8 v& A# M8 a7 Anetwork must be tailored very closely to these transient current needs, otherwise ground
2 S8 E+ h; v* z5 a4 abounce and power supply noise will exceed the limits of the device. The transient currents in an/ i& z+ r4 K' [
FPGA are different from design to design. This application note provides a comprehensive# P8 _) S+ B! v, E1 p4 F, f
method for designing a bypassing network to suit the individual needs of a specific FPGA' z. ~# b/ W4 ?9 F) R
design.
- Z- ?' h: U! m7 N( SThe first step in this process is to examine the utilization of the FPGA to get a rough idea of its
) c& ~! l8 U$ q4 |+ Q8 htransient current requirements. Next, a conservative decoupling network is designed to fit these
0 X. e, p' z8 ]requirements. The third step is to refine the network through simulation and modification of
3 q8 V) x9 Q' H- I; @capacitor numbers and values. In the fourth step, the full design is built and in the fifth step it is
5 k% ~: S2 D! |- B. n$ o2 l" ^measured. Measurements are made consisting of oscilloscope and possibly spectrum analyzer
: s* t% ?# m* ?: lreadings of power supply noise. Depending on the measured results, further iterations through
6 `2 h U A# ?2 q& R! t& Sthe part selection and simulation steps could be necessary to optimize the PDS for the specific1 o- f# n1 t* ^
application. A sixth optional step is also given for cases where a peRFectly optimized PDS is8 p' a) L5 |7 ~4 M" j' b
needed. |
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