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Introduction:
. m0 ^. A: h/ j- o& p% u FPGA designers are faced with a unique task when it comes to designing power distribution
% L" s. }" F8 D) V# tsystems (PDS). Most other large, dense ICs (such as large microprocessors) come with very) E% k, @; u; D. J
specific bypass capacitor requirements. Since these devices are only designed to implement+ g2 l: }* t( _, Y: o/ {+ e2 o
specific tasks in their hard silicon, their power supply demands are fixed and only fluctuate
, }2 s3 u$ j4 M* M* k* awithin a certain range. FPGAs do not share this property. Since FPGAs can implement an* b* v9 t) m' Q4 F. y, F
almost infinite number of applications at undetermined frequencies and in multiple clock
8 @2 Q, h, T. ^) U9 l; {* g- T {domains, it can be very complicated to predict what their transient current demands will be.# m+ k+ g; N3 p$ f( z* V* M0 |
Since exact transient current behavior cannot be known for a new FPGA design, the only' D$ f/ E/ E. W. {4 q- D6 v7 a7 X
choice when designing the first version of an FPGA PDS is to go with a conservative worstcase
( ^7 E/ R; ^6 K; @design.
6 _9 h; }5 F+ M) \- ]7 E( k' [Transient current demands in digital devices are the cause of ground bounce, the bane of highspeed k9 s7 p9 P; x9 ]# F8 O0 S1 t+ h
digital designs. In low-noise or high-power situations, the power supply decoupling
. `$ }$ P6 F4 d# C$ T9 z5 q3 Unetwork must be tailored very closely to these transient current needs, otherwise ground
1 ^+ ]* J% L) Wbounce and power supply noise will exceed the limits of the device. The transient currents in an
' {5 e( |5 R3 t# l+ SFPGA are different from design to design. This application note provides a comprehensive
' _1 _( U7 I; Fmethod for designing a bypassing network to suit the individual needs of a specific FPGA. E( I1 H! N7 P' N3 ]
design.# D0 o. x1 K3 v. A% w$ B
The first step in this process is to examine the utilization of the FPGA to get a rough idea of its
" T6 Q1 r- ]* O9 ~# Etransient current requirements. Next, a conservative decoupling network is designed to fit these
% U- h( l' [7 _9 Qrequirements. The third step is to refine the network through simulation and modification of& b3 C7 g( Q1 m0 |' A: u' a
capacitor numbers and values. In the fourth step, the full design is built and in the fifth step it is
2 C: h2 G' E- j: kmeasured. Measurements are made consisting of oscilloscope and possibly spectrum analyzer
2 ^+ C, I( w6 Y0 b/ Vreadings of power supply noise. Depending on the measured results, further iterations through
$ C# c0 u3 J, X) Uthe part selection and simulation steps could be necessary to optimize the PDS for the specific8 p4 W: Y0 b4 @2 H6 B
application. A sixth optional step is also given for cases where a peRFectly optimized PDS is4 b2 h3 G" o5 S8 B2 ]
needed. |
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发表于 2007-9-17 09:11
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