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第二章 虚拟地址到物理地址转换
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2.1 MMU 硬件VA到PA转换
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9850K 的cpu是Cortex A7的。7 h1 w& |/ D7 ?
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- \! `: u! w! M1 E4 M1 N- aThe Cortex-A7 MPCore processorimplements the Extended VMSAv7 MMU, which includes the ARMv7-A Virtual MemorySystem Architecture (VMSA), the Security Extensions, the Large Physical AddressExtensions (LPAE), and the Virtualization Extensions.
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VMSAv7 defines two alternativetranslation table formats:
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* L* ~% T( @7 J$ A6 J( MShort-descriptor format
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& ^6 \/ W" y U7 L5 H. y j3 tThis is the original format definedin issue A of this Architecture Reference Manual, and is the only6 m2 ?' y, C! K
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]8 N8 e$ G- d m3 gformat supported on implementationsthat do not include the Large Physical Address Extension. It0 U, h* U0 n# U2 @: D
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uses 32-bit descriptor entries inthe translation tables, and provides:
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• Up to two levels of address lookup.; \9 G3 H, N% O7 K9 b
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• 32-bit input addresses.$ _4 y* s$ w, ]
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& |/ K) J! K1 M• Output addresses of up to 40 bits.( y, W8 k; h" M; S% m
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- M) D" F6 s, T o3 ]* g" T5 G! a& A• Support for PAs of more than 32 bits by use of supersections, with16MB granularity.' L8 h9 A/ U& g
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• Support for No access, Client, and Manager domains.0 v. u6 h: J% |4 O X
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5 y7 n" u# d2 k9 g2 A: s! ^: I. S• 32-bit table entries.
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8 h0 C+ |5 K9 e7 B( vLong-descriptor format: H1 m# N! {" a7 P2 @+ Q
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