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本帖最后由 auto1860 于 2017-7-3 15:25 编辑 / n' S! W8 w1 j% D
- J: T& A9 t9 l3 S7 T$ I. u- Y2 zFixed CCRs: SPB 17.2 HF0224 Q( S" X+ B0 \6 J$ v
06-16-2017- Y, E. K3 ^; z+ g) b8 t
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CCRID Product ProductLevel2 Title
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. i1 ^; i2 @# {8 S1755789 ADW DBEDITOR Checking in HSS Block returns 'Failed to create archive'
: x' m) Z' S& _6 m1731459 ADW FLOW_MGR Cannot open LRM from Flow Manager% D5 t1 R6 Z2 V. M* d( P& o
1731460 ADW FLOW_MGR Cannot open LRM from Flow Manager
# o3 P# d7 d/ A1744081 ADW FLOW_MGR Error regarding configuration file when trying to open Workflow Manager- N0 C9 c+ w) T
1756727 ADW LIBIMPORT EDM Library Import fails with java exceptions when merging classifications
! j2 W" D6 u& f8 K$ Z( ~1743763 ADW SRM Find filter is grayed out when allegro PCB Editor is opened from EDM Flow Manager
8 X |/ n2 @! E# y1748399 ALLEGRO_EDITOR DATABASE In release 17.2-2016, end caps not visible for certain clines in PCB Editor0 \7 N3 P5 T$ z5 Q+ Y$ ]' K2 ]( c
1748522 ALLEGRO_EDITOR INTERACTIV A component mirrored using the 'funckey' command jumps to (0,0) position when the 'move' command is used on it; o/ I/ l. z8 G$ m
1734983 ALLEGRO_EDITOR INTERFACES Secondary step model does not stay mapped after drawing is reopened
4 o9 F: K" N0 D. ?3 N# o+ _1753704 ALLEGRO_EDITOR REFRESH Refreshing symbols crashes PCB Editor
( j2 a# y0 s9 G) m0 g1493721 ALLEGRO_EDITOR SHAPE Voids on negative planes are not adhering to constraints
: Q( D5 H2 C! n$ g0 N: E- P, a$ S1711242 ALLEGRO_EDITOR SHAPE Route keep out leads to partly unfilled shapes with gaps# S4 [! j5 @( E2 m2 O
1726865 ALLEGRO_EDITOR UI_GENERAL Pop-up Mirror command does not mirror at cursor position6 q& D5 ~/ B' `. C
1752987 ALLEGRO_EDITOR UI_GENERAL axlUIViewFileCreate zoom to xy location not working while in user created form.( M9 B5 P* Z4 y$ U; U
1755638 ALLEGRO_EDITOR UI_GENERAL In release 17.2-2016, zoom operations using mouse button not working when axlShellPost() is run: n' x7 O6 C' M v8 x) m& L
1719792 ALLEGRO_PROD_TOOLB CORE Productivity Toolbox Z-DRC hangs or crashes PCB Editor
" B2 `" |5 J* ?6 X5 S) k1624869 ALTM_TRANSLATOR CAPTURE A structure file is required to translate a third-party schematic to orcad Capture
1 C4 A# U, E+ X( |% r+ }1707416 ALTM_TRANSLATOR CAPTURE Missing components and pins in the OrCAD Capture schematic translated from a third-party tool, i2 l$ e5 K# F* w" Z7 Z/ Y9 X
1708825 ALTM_TRANSLATOR CAPTURE The third-party translator fails to translate the schematic. o# r$ H8 W8 ]
1719200 ALTM_TRANSLATOR CAPTURE The third-party translator fails to translate all the pages of a schematic
- t4 P" W* A2 {# j1546070 ALTM_TRANSLATOR CORE Third-party to DE-HDL schematic translation fails& a5 Z7 d: X9 q: E7 I, u
1700508 ALTM_TRANSLATOR CORE Third-party PCB translator does not work in release 17.2-2016- K" k9 D+ a7 K! m3 F2 a) o
1699340 ALTM_TRANSLATOR DE_HDL Unable to import third-party schematic into DE-HDL using Import menu in PCB Editor1 k. D0 e4 \: B: s% ]
1630379 ALTM_TRANSLATOR PCB_EDITOR Third-party translator is not importing clines and vias
6 h! [) G& h# X" [; ^1708615 ALTM_TRANSLATOR PCB_EDITOR All items of third-party PCB not imported in release 17.2-2016
8 x8 w# y" P: h" g1758296 APD DXF_IF DXF OUT: Rounded rectangle pads mirrored incorrectly
" E* L V. c4 k. ~& a1756040 APD IMPORT_DATA The 'die text in' command ignores values after the decimal point
1 l' _/ n; \* I& a0 W0 |1727206 APD SHAPE Merging two shapes results in an incorrect shape. @! Z- N' M+ F/ P6 L4 j
1753682 concept_HDL CONSTRAINT_MG Constraint Manager stops responding while cross probing DE-HDL
1 |6 f! A; G5 q' r4 M1721334 CONCEPT_HDL CORE dsreportgen not able to resolve gated part on schematic V% b1 {! G! r6 N6 k# i9 y( a
1747559 CONCEPT_HDL CORE Copying a logic symbol without a part table entry results in ERROR(SPCODD-53), [# C: A7 }4 V6 ~2 N9 C
1749644 CONCEPT_HDL CORE In release 17.2-2016 Hotfix 019, 'align components' is not working on Windows 8 and DE-HDL crashes: K* T. G% m; ^# k" L! d
1746910 CONCEPT_HDL GLOBALCHANGE Global Component Change unable to identify part data when using schematic pick option
! Q7 m+ s( Y4 Z5 `: n3 J* _/ Q' ]6 @1743572 FLOWS PROJMGR Project Manager displays incorrect values in Project Setting
3 x0 l0 p e3 y1724124 FSP DESIGN_EXPLOR Provide TCL command to filter design connectivity window
; ~( l. Q- s' y# Z1719105 FSP GUI Tabular sorting not working in FPGA System Planner
) o, ?' ~' \! |! J5 p8 L1755750 PCB_LIBRARIAN GRAPHICAL_EDI In release 17.2-2016, unable to delete _N pins in PDV Symbol Editor
0 `0 f. v; A2 V$ q( p H. x* l' _1722993 PCB_LIBRARIAN IMPORT_CSV Part Developer crashes while importing part information stored in a .csv file; B4 r8 k: A: S- X% e
1758856 SIP_LAYOUT 3D_VIEWER Correct the spelling error in the 3D Viewer Design Configuration window" ?: \6 l. f" \) ^5 w2 W( C
1755179 SIP_LAYOUT ARTWORK PCB Editor crashes when creating Gerber files4 ~# w, \3 @) K, Z# L7 B
1743511 SIP_LAYOUT MANUFACTURING Package Design Integrity shows non-redundant padstacks in the Redundant Padstacks check
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发表于 2017-6-29 13:23
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