死铜在哪里啊？？

jackyard · 发表于 2011-2-23 15:49

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我画了一个四层的板，中间两层中，其中一层是地，一层是电源，我把电源分切了好几块，为什么在电气检测中老是出现面的问题：

Un-Routed Net Constraint ( (All) )

Isolated copper: Split Plane (GND_SIGNAL) on GND02. Dead copper detected. Copper area is : 2.4E2 sq. mils

Isolated copper: Split Plane (GND_SIGNAL) on GND02. Dead copper detected. Copper area is : 1.7E2 sq. mils

Isolated copper: Split Plane (GND_SIGNAL) on GND02. Dead copper detected. Copper area is : 1.2E2 sq. mils

Isolated copper: Split Plane (GND_SIGNAL) on GND02. Dead copper detected. Copper area is : 1.1E2 sq. mils

Isolated copper: Split Plane (3V3_VDD2) on PWR03. Copper island connected to pads/vias detected. Copper area is : 1.3E3 sq. mils

Isolated copper: Split Plane (1V0_TXRX) on PWR03. Copper island connected to pads/vias detected. Copper area is : 1.1E3 sq. mils

Isolated copper: Split Plane (1_2V_DVDD) on PWR03. Copper island connected to pads/vias detected. Copper area is : 2.1E3 sq. mils

Isolated copper: Split Plane (1V0) on PWR03. Copper island connected to pads/vias detected. Copper area is : 9E2 sq. mils

Isolated copper: Split Plane (3V3) on PWR03. Dead copper detected. Copper area is : 1.5E4 sq. mils

Isolated copper: Split Plane (3V3) on PWR03. Copper island connected to pads/vias detected. Copper area is : 5.3E3 sq. mils

Isolated copper: Split Plane (3V3) on PWR03. Copper island connected to pads/vias detected. Copper area is : 1.2E3 sq. mils

Isolated copper: Split Plane (3V3) on PWR03. Copper island connected to pads/vias detected. Copper area is : 9.4E2 sq. mils

Isolated copper: Split Plane (3V3) on PWR03. Dead copper detected. Copper area is : 9.1E2 sq. mils

Isolated copper: Split Plane (3V3) on PWR03. Copper island connected to pads/vias detected. Copper area is : 7.9E2 sq. mils

Isolated copper: Split Plane (3V3) on PWR03. Dead copper detected. Copper area is : 4.4E2 sq. mils

Isolated copper: Split Plane (3V3) on PWR03. Dead copper detected. Copper area is : 1.7E2 sq. mils

而在PCB中也看不到绿色的出错指示，请高人指点一下。

SSDMA · 发表于 2011-3-31 14:16

via太多，太密了。内电层的死铜，可以通过调整via的位置或其他方式去除。
表层铺铜的设置是没有用的

kgsz · 发表于 2011-2-23 16:29

覆铜的时候不是有除去死铜这个选项么？

rongsun1123 · 发表于 2011-3-23 18:11

二楼的看法是对的。

jackyard · 发表于 2011-3-31 16:13

回复 SSDMA 的帖子

你说的对，后来在rule里改了就好了。哈哈

sunlin0112 · 发表于 2011-3-31 17:02

恩不错

zdh_054 · 发表于 2011-4-2 23:14

呵呵楼主估计也困惑好久吧以前我也碰到过，找了好久才发现的。其实AD中的错误是有颜色标记的就看眼力怎么样了

stupidboy · 发表于 2011-4-8 23:07

重新生成一下内电层就可以了

dashuszhl055 · 发表于 2012-12-17 08:04

你好这个主题的问题你是怎么解决的我也是遇到一样的问题画的是六层电源层和地层你是怎么通过修改规则来去掉那些提示检测的谢谢了~

wrh · 发表于 2012-12-17 16:30

可以设一个room区域规则，即在孔比较密集的地方画好room区域，把区域内的内层隔离环改小

dashuszhl055 · 发表于 2012-12-17 21:44

wrh 发表于 2012-12-17 16:30
$ l! @2 C2 H, S2 W. U# v+ m7 F可以设一个room区域规则，即在孔比较密集的地方画好room区域，把区域内的内层隔离环改小

挺不错的谢谢~

糖人 · 发表于 2024-4-30 18:12

SSDMA 发表于 2011-3-31 14:16/ u) r9 A; L* k- J
via太多，太密了。内电层的死铜，可以通过调整via的位置或其他方式去除。( H7 O% Z6 I- k! G+ m$ g+ H
表层铺铜的设置是没有用的

有效的方法是啥啊

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