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DATE: 02-13-2015 HOTFIX VERSION: 043
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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4 k& Y. q/ I( [- l. o, @$ B" ~1259909 ADW DSN_FLOW Unlike Project Manager, parts cannot be copied from one design to another using ADW, J4 f, e9 ]2 T5 g$ F
1341092 ALLEGRO_EDITOR MANUFACT Export > PDF should show drill holes if the Filled option is selected4 [4 a5 i& L! |* m6 E7 V) L* {
1356711 SPIF OTHER Unable to use PCB Router function with PA5700 license.
1 T0 j3 `# e+ T' ]$ O1357880 ALLEGRO_EDITOR INTERFACES Incorrect Step model view in Step Package mapping window* L; ]2 ?- J; e/ b( |
1362132 ALLEGRO_EDITOR DATABASE X hatch shape with cell High shows shape boundary error) v# K; `" d0 o# H! h: h
1362641 ALLEGRO_EDITOR INTERACTIV Unwanted apostrophes are added to ads_sdart and few other variables under File_management in User Preference5 D/ S/ c" O/ f. I4 D2 c( B
1362771 ALLEGRO_EDITOR EDIT_ETCH Running AiDT displays an error; the tool crashes on subsequent runs
- C+ i8 w! Z3 t1363908 SIP_LAYOUT PLACEMENT SiP Layout crashes when refreshing symbols( H# ?; t* N5 n
1364113 ALLEGRO_EDITOR MANUFACT NC drill output does not comply with NC Parameters if the unit is inconsistent
1 ?' A+ r Y: I1364146 PSPICE SIMULATOR Simulating the attached Design gives 'RPC Server is unavailable' Error.
$ {, H/ r$ N* a1364209 ALLEGRO_EDITOR INTERFACES STEP export: Allow for zero height and instance height change with PLACE_BOUND_TOP/BOTTOM
: S# p* z6 p9 }1364329 CONCEPT_HDL CORE Show Physical Net Name causing netlisting errors# M" B( p5 i$ Y+ t1 n
1364367 PCB_LIBRARIAN IMPORT_VIEWLOGIC viewlogic2con translator does not complete. x+ [( }0 g B7 C! h- L
1364771 ALLEGRO_EDITOR MANUFACT Incorrect Gerber created for mounting holes
* F1 D$ B# a; ?! H c( I1 H1366415 CONCEPT_HDL CORE global navigation not working for few buses in the design
; A6 t, F4 {" z0 U2 x5 H% k: z- d, \$ P* Z1367650 SIP_LAYOUT IC_IO_EDITING Add Respace command to Symed app mode for I/O drivers& Q$ W7 G, D% i4 o! p
1368246 SIP_LAYOUT OTHER Cannot delete die(s) that were placed manually in a design2 ?3 E( P) Y6 l: s8 q
1368889 ALLEGRO_EDITOR INTERFACES Unable to export incremental updates of the IDX baseline file! D2 |; ]0 Z- `" [' Z- n' r! }! @
1369177 SIP_LAYOUT OTHER Add a new command to create a bounding shape
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2 p: \+ k- |+ I3 Z( h2 Q/ IDATE: 01-30-2015 HOTFIX VERSION: 042
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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) N- s a% q x" \) L1334361 ALLEGRO_EDITOR INTERACTIV ZCopy should be able to copy multiple clines
! o3 i: a l- i% D6 }# Q; K& L1348389 CIS PART_MANAGER Update selected part status should re-query every time the command is run
( s M) Q2 ~$ Y/ T" s1349342 ALLEGRO_EDITOR EDIT_ETCH Need information on how to resolve (SPMHA1-170): No available buffer identifiers.
6 ^' {% i2 o. j1349849 CIS OTHER Capture crashes on generating variant reports
% T$ B- N |9 Y6 x, V- b0 O1349983 PSPICE SIMULATOR Simulation aborts if save data option is greater than 1 sec
6 x& W* s4 Y$ a) H: A' e1350477 PSPICE SIMULATOR RPC server is unavailable
) t7 F* d6 h" g, R2 G; o1353830 SIG_INTEGRITY SIMULATION xtalk analysis leads to crash: R8 C3 o" `; {+ ^% x' W
1354644 ALLEGRO_EDITOR EXTRACT Extracta does not extract a value for specific property! e/ i7 W2 q! U4 _4 h5 H
1355337 ALLEGRO_EDITOR EDIT_ETCH Windows 8 Route Connect produces Buffer error.4 V( a3 c- ?4 C% ~5 d* D4 f
1355522 SIP_LAYOUT IC_IO_EDITING Option to select reference point for alignment should be available when aligning single drivers* z( }4 E. g( f$ O! W1 }8 K
1355737 ALLEGRO_EDITOR EDIT_ETCH No available buffer identifiers cause loss of control in a routing phase, r/ e, P4 E0 Y
1356373 ALLEGRO_EDITOR DRC_CONSTR Design is crashing when attempting to update the DRCs.5 Y0 C/ v) y5 Z1 Z0 M# U0 u
1356684 SIP_LAYOUT SYMB_EDIT_APPMOD Enhance highlight of swappable pins excluding the pin to be swapped to
" L8 t; H/ C5 L0 U5 r; U1358383 ALLEGRO_EDITOR MODULES mdd file is not created correctly* g( H S) K" y3 {2 \
1358558 CONCEPT_HDL GLOBALCHANGE "Global Component Change" could not update parts.* h1 W! [8 E& s
1359780 ALLEGRO_EDITOR EDIT_ETCH The board database crashes on using Route Connect after some editing of traces.' t( {- V( f/ X2 K9 X7 w+ e# X
1360416 SIP_LAYOUT OTHER SiP Design Variant not being created on the design
" V7 |* l2 G9 N: i6 G- W1360630 FSP ALLEGRO_INTEGRAT For Fixed Internal and Fixed External nets, FSP shows net schedule difference in PCB Editor
' t1 D& J! }% r. o1361157 ALLEGRO_EDITOR GRAPHICS 3D view of footprint with STEP model not correct, although it shows correctly when footprint is placed on board file.
* n" j9 f0 y; R$ U H* O) u0 Q1 p1 Q1361925 FSP DE-HDL_SCHEMATIC Port is not connected for the nets having netname as NC.# v% S0 {* k) E9 I
1362865 CONSTRAINT_MGR OTHER Import logic is not creating model-defined differential pairs.
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发表于 2015-2-15 23:37
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