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Introduction:; \. u9 R. {9 O! o$ B* ~4 T
FPGA designers are faced with a unique task when it comes to designing power distribution/ B# x# v- }" U% X9 j
systems (PDS). Most other large, dense ICs (such as large microprocessors) come with very2 w g1 F8 |8 Q
specific bypass capacitor requirements. Since these devices are only designed to implement
. ]. H) _* Y9 I& lspecific tasks in their hard silicon, their power supply demands are fixed and only fluctuate+ `$ u$ [. c* V- w' b7 J4 \8 x
within a certain range. FPGAs do not share this property. Since FPGAs can implement an
; N* \; N; n2 B1 Z* ]almost infinite number of applications at undetermined frequencies and in multiple clock
" Q- ~. X! O0 U& `$ @: ]2 R8 n! ldomains, it can be very complicated to predict what their transient current demands will be.
& e: i }) V# M& d, y% z$ dSince exact transient current behavior cannot be known for a new FPGA design, the only; d1 U5 b6 Y6 G( q$ O
choice when designing the first version of an FPGA PDS is to go with a conservative worstcase
- d; i/ c- J/ }2 J% R4 Gdesign.
2 k6 S" o. R- i, ~ RTransient current demands in digital devices are the cause of ground bounce, the bane of highspeed
1 ]9 u$ V; ` u: j+ Q& I0 K2 @digital designs. In low-noise or high-power situations, the power supply decoupling
% ^9 H& O$ ?, g7 O# [" q* n$ qnetwork must be tailored very closely to these transient current needs, otherwise ground- M- l# x c4 a* I+ M q. Q
bounce and power supply noise will exceed the limits of the device. The transient currents in an8 O9 t1 {! @1 r2 H5 H: N% \
FPGA are different from design to design. This application note provides a comprehensive* b Y3 s( l8 _& M
method for designing a bypassing network to suit the individual needs of a specific FPGA
6 v4 n" u2 N* i: v* K- Jdesign.) H& i) r. a" P
The first step in this process is to examine the utilization of the FPGA to get a rough idea of its# l: ~% [# Q. V: M b
transient current requirements. Next, a conservative decoupling network is designed to fit these+ B, Y( c- v' o7 ]& M6 ~
requirements. The third step is to refine the network through simulation and modification of3 g9 N; p! w% r% Z" A5 [
capacitor numbers and values. In the fourth step, the full design is built and in the fifth step it is
& @5 K, {8 _% Z% }measured. Measurements are made consisting of oscilloscope and possibly spectrum analyzer
- Z* s) D, }( m3 ireadings of power supply noise. Depending on the measured results, further iterations through* P' G7 t/ A! B0 u
the part selection and simulation steps could be necessary to optimize the PDS for the specific! Y6 k7 G0 R# b& ^% |2 x
application. A sixth optional step is also given for cases where a peRFectly optimized PDS is) K$ Y1 k! `; g4 K
needed. |
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发表于 2007-9-17 09:11
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