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Introduction:: U' P1 Q2 D) | S
FPGA designers are faced with a unique task when it comes to designing power distribution, J6 C; E) a8 A9 f+ r$ A: }! D
systems (PDS). Most other large, dense ICs (such as large microprocessors) come with very9 P* ?4 ~1 L2 [* y
specific bypass capacitor requirements. Since these devices are only designed to implement
# a8 _- O, }; `8 ?6 v$ c* uspecific tasks in their hard silicon, their power supply demands are fixed and only fluctuate
! u$ r- U9 H7 g9 u$ Jwithin a certain range. FPGAs do not share this property. Since FPGAs can implement an6 Y, X$ G/ y' x: x1 q& R3 a5 B# ?: }
almost infinite number of applications at undetermined frequencies and in multiple clock3 U1 T6 O" f6 a' S
domains, it can be very complicated to predict what their transient current demands will be.
0 s, M; v& ^. ISince exact transient current behavior cannot be known for a new FPGA design, the only
* M$ B0 H+ ]4 q* K# O* o: Uchoice when designing the first version of an FPGA PDS is to go with a conservative worstcase
( ?8 x! N8 e* {1 J3 |1 |1 L$ Tdesign.+ C" {% U% ~) v! g& ]
Transient current demands in digital devices are the cause of ground bounce, the bane of highspeed/ g$ e8 k) j' B, E1 g4 O
digital designs. In low-noise or high-power situations, the power supply decoupling3 a T$ p m4 r9 ~
network must be tailored very closely to these transient current needs, otherwise ground
0 E e% k) }7 P [9 z/ \bounce and power supply noise will exceed the limits of the device. The transient currents in an
% P/ j1 M: S$ O* ]% Z; K7 EFPGA are different from design to design. This application note provides a comprehensive
! j+ o( z9 f* e: Jmethod for designing a bypassing network to suit the individual needs of a specific FPGA
5 a+ w6 @. q' f' }3 z: P' S9 Bdesign.
) d( V2 ^! Q' h3 IThe first step in this process is to examine the utilization of the FPGA to get a rough idea of its
# ^+ l& u3 A/ ]* L; N3 btransient current requirements. Next, a conservative decoupling network is designed to fit these9 z" e$ H; n; B4 h
requirements. The third step is to refine the network through simulation and modification of. o! o3 F$ W5 w1 _
capacitor numbers and values. In the fourth step, the full design is built and in the fifth step it is
: p, c% J1 w0 m5 q+ F1 cmeasured. Measurements are made consisting of oscilloscope and possibly spectrum analyzer! q/ W5 `+ I2 c, w8 L6 N1 N4 X
readings of power supply noise. Depending on the measured results, further iterations through! d# t' |" u% K8 P' m2 ^/ e
the part selection and simulation steps could be necessary to optimize the PDS for the specific
+ A* C- K2 N) k8 i) a8 O1 Capplication. A sixth optional step is also given for cases where a peRFectly optimized PDS is
' K2 l2 z6 j$ r5 s lneeded. |
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