标题: Hotfix_SPB16_60_032_补丁发布 [打印本页] 作者: wangye_123 时间: 2014-7-31 09:06 标题: Hotfix_SPB16_60_032_补丁发布 下载链接：https://www.sync.cloudbox.hinet. ... zRkMTI4ZTQzN2UxODY=% Q) ~& `, c+ c4 l
更新说明： / x) _! M2 X6 BDATE: 07-25-2014 HOTFIX VERSION: 032+ w7 ^% @' ]8 ]$ g2 u
=================================================================================================================================== 3 O0 L: D& r, m/ ~7 ]1 k0 {# m, vCCRID PRODUCT PRODUCTLEVEL2 TITLE# C. ^! T# f8 b% A, P5 ~& H
=================================================================================================================================== 2 ?; E, T: m, e4 m6 q4 Q381127 SPECCTRA CROSSTALK Specctra xtalk reports aren't correct5 p( _! y; b" _$ M$ u
616770 ALLEGRO_EDITOR COLOR Remove the APPLY button in the Color Dialog window.! q( p0 j7 i. K
982944 ALLEGRO_EDITOR COLOR seperate the Etch to the Shape and the the Cline in the visibility window 8 {) P2 L) c# a7 M* L982995 ALLEGRO_EDITOR INTERACTIV Shown infomation for the selected physical symbols f8 N/ u9 S4 C7 x3 C1024832 PSPICE PROBE Shows wrong data & header when exporting trace to .txt0 U) w. X4 R b, p/ z
1063258 PSPICE AA_OPT curve fit fails with error same data works in 16.5 Simulation error: out of range of data # X! m2 a) Y3 A2 }1112360 PSPICE AA_OPT Advacne analysis gives runtime error while using Optimizer in attached design 1 r4 t' @5 F& m$ d1154323 PCB_LIBRARIAN VERIFICATION Con2con is choosing incorrect Primitive from Chips file and failing FTB Checks 1 k A! p) T* N: R1 v1184690 CONCEPT_HDL CORE Weird behavior of genview for split hierarchical blocks ! S8 H, e" L0 K R% v5 p; ]0 f7 d8 C1212577 PSPICE MODELEDITOR IBIS translation fails without any information in log file 7 f7 G2 B) D2 Q; t+ b2 w+ Z1213204 ALLEGRO_EDITOR PLACEMENT Place Manually with existing fixed net behaving incorrectly% Y9 i1 w }: { Y/ V
1213837 ALLEGRO_EDITOR INTERACTIV When copying a stacked via the temp highlight does not display on the last layer of the stack. 7 E8 `) O6 \; t2 `1216519 SPECCTRA ROUTE Autorouter will not add BB via between uvia within the BGA area 5 X# ~% v4 Z% e3 ]- x. a1220655 PSPICE DEHDL_NETLISTER Support for automatic addition for Power source and Ground Node for Globals in DEHDL PSpice netlisting9 e3 |) R# ?# Q: \) v8 i$ W
1223018 CAPTURE OTHER Diff pair Auto Setup not working for the buses. . c/ t. H- W9 i- M C: y2 C0 Y1225689 PSPICE AA_SMOKE Smoke analysis crashes with attached testcase5 J6 e. u# L7 l2 `- c
1232124 CONCEPT_HDL COMP_BROWSER unable to generate ppt_options.dat file in first go - B* A$ j, G1 a# b3 o1235059 PCB_LIBRARIAN IMPORT_CSV pin_delays not being imported into PDV1 n1 h8 e4 h% v* H& m
1238815 CAPTURE OTHER Capture doesn?t retain more than 191 library in add part/capture.ini under part selector configured libraries / L9 o5 G1 k2 D6 h. {) ~/ B1239241 ALLEGRO_EDITOR INTERACTIV Via replacement doesn't replace with correct via but right padstack name. 1 c4 P& _1 @. \) y' k6 J: U5 }- m1240201 ALLEGRO_EDITOR EDIT_ETCH RPD DRC unresolved evenif HUD turns Green . ?0 J$ f* n. q9 `/ w1240314 PSPICE SIMULATOR Getting internal error,overflow for the second run) f# @3 P8 j; ^1 m7 Z9 c
1242805 ALLEGRO_EDITOR DRC_CONSTR no_drc_progress_meter variable hangs allegro after running update drc : O6 Z; u3 X) t q2 o `' D7 A1243267 ADW TDA URL to TDO-SharePoint should be defined in CPM File 7 R: Z9 X% l Z2 J) W$ g( |& T1244857 ADW TDA Policy File Variables not working correctly in policy file# M R3 I1 a" T9 ~0 R9 a
1245779 CONCEPT_HDL CONSTRAINT_MGR Obsolete objects in DEHDL CM J5 y/ x( Q) S1246811 CIS EXPLORER Option to keep the part type tree in CIS explorer expanded on every invoke3 ]3 M" r- r( m4 V9 ?2 b6 ^) ^5 O
1246964 PSPICE PROBE Simulation Crashes in 16.6 but running successfully in 16.5 # ^) G1 T" l5 i% O8 t4 X) n1248782 CONCEPT_HDL CORE Display winning physical bus names (occurrence mode) in the the lower block of an Hierarchical design 4 V; h( r, j5 Q& a0 u" W3 O5 Q1 b1249238 CONCEPT_HDL CORE Uprev from 16.3 splatters text around sch page , V5 j2 [! N' C$ V8 h2 ~1249692 ALLEGRO_EDITOR GRAPHICS 3D Viewer is wrong when resizing its window.# T7 q" l& Q$ @. C* |$ I' e# q
1249850 ALLEGRO_EDITOR SHAPE With shape_rki_autoclip Route Keepin to Shape DRC is created/ U$ b0 y( w% N
1250683 ALLEGRO_EDITOR INTERACTIV devpath corrupts if edited from user preferences.4 E7 j+ k. V, R! [
1252059 ALLEGRO_EDITOR INTERACTIV Preference Editor is unable to delete a previous path entry for library paths6 @' h& a2 o" m! X4 f* a
1253563 SIP_LAYOUT DEGASSING Not getting degassing voids when close to shape in center of design+ @0 b f" H$ ]' ^: d
1254319 ALLEGRO_EDITOR GRAPHICS ENH: Functionality to change the 3D Model color for more realistic view + [& G; _, {# x8 ~1 R; n% P) j% x) A. W1254562 ALLEGRO_EDITOR DATABASE Unable to delete a subclass that exist only on classes Package Keepout, Package Keepin and Route Keepin." {! i/ ?* N! F. u2 b
1255169 CONCEPT_HDL OTHER ADW (BPc) Packager should report the specific corrupt directive in the .cpm file $ ]. d1 s* C/ x! u' A D) I4 ~1255573 ALLEGRO_EDITOR DRC_CONSTR Need soldermask DRC checks when same net via and smd pad overlaps& N4 V' v% o& j+ J/ T5 S
1257950 CONSTRAINT_MGR SCHEM_FTB Changing xnet name on Allegro CM.& A2 l0 d( F" w; f. Z3 P/ f& {
1258165 F2B DESIGNVARI changing visibility of Probe_number in variant schematic changes it to $Porbe_number " c" e0 Z% M% i$ K# o$ T! C1258274 PCB_LIBRARIAN VERIFICATION con2con crash with no notification or error message1 e1 H+ }3 a! \
1258860 CAPTURE PROJECT_MANAGER Bug: Text Editor (File> New> VHDL File) filters characters from Text ; h+ s7 l5 S, v# t: h+ b1258872 CONCEPT_HDL CORE Objects are copied (instead of moved) when moved from sheet to sheet 9 v: m/ f0 W9 d: H- G* P1259284 CONCEPT_HDL PDF HDL_POWER ( global) net does not get transferred to the published pdf ( U: ~% }5 d; G9 F* w% f1259375 CONCEPT_HDL CORE Help link to cdnUsers.org needs to be changed & l( R4 N' ~8 g: G' S( Z1259860 ALLEGRO_EDITOR INTERACTIV Edit > Mirror does not display asymmetrical pad correctly when the footprint is attached to cursor. / D0 f- X w0 D( k2 _0 V$ p1260002 ALLEGRO_EDITOR INTERACTIV Alt sym hard is not obeyed when using Edit > Move > Mirror( Q+ x6 h( x! ^% s; Y
1260006 ALLEGRO_EDITOR PLACEMENT funckey r iange 90 rotation issue2 v8 Y! Q- M9 B+ F
1260667 ALLEGRO_EDITOR EDIT_ETCH Allegro crashes when running AICC command on few Diff Pair traces. . ~2 @7 V% {6 _1260763 CONCEPT_HDL CORE Export Physical fails with $TEMP entry in Setup-Tools 1 d' G# j6 `% G D+ |" ^: v1260847 SIP_LAYOUT SYMB_EDIT_APPMOD Border texts seen as triangles. * y4 s# p Q% l, W- b2 O9 M1260948 ALLEGRO_EDITOR SHAPE Dynamic ground shape is shorting to via of a different net at layer 4 & 5 in this design- }' e3 i9 I% K% I' l+ C, |6 `
1262011 ALLEGRO_EDITOR PLACEMENT Key Properties on Component Instance/ Definition on available to use with Quickplace by Property % G! {5 f7 G2 ~% E9 r2 ?1262322 ALLEGRO_EDITOR PADS_IN Pads_in can not translate route keepout which specified for the all layers.! B: L! P$ H& [ @! w+ v
1262626 CONCEPT_HDL CORE PROBE NUMBER attributes lost from the nets after upreving the design ! |" q$ p0 i3 L3 g1263592 PCB_LIBRARIAN VERIFICATION Unable to check in Schematic Model due to pc.db file 6 _) E! g/ Y W; X) e1263685 ALLEGRO_EDITOR INTERACTIV Editing Photo Width value from non zero to zero allegro gives warning- Value must be greater or greater to zero; y5 H7 n8 k/ Q3 t: Z1 W
1263704 ALLEGRO_EDITOR EDIT_ETCH Bug - AiTR wrongly deletes blind vias and do reroutes. 5 Z9 M: M. X: E6 {: q1265120 ALLEGRO_EDITOR SHAPE Require voids in dynamic shapes to use pad value w0 Y% D* _. }4 h
1265275 ALLEGRO_EDITOR DRC_TIMING_CHK When XNETS are dissolved by removing the Models all Physical and Spacing NetClass associations are lost* [; W+ D6 |: l; Z
1265633 PSPICE SIMULATOR Bias point result is different in consecutive simulation run of the attached project 2 [1 b% Z8 k% g; W6 p/ D5 w; C, Q1266349 ALLEGRO_EDITOR PLACEMENT Rotating symbol while placement show wrong angle of rotation than the placed angle when Angle is set in Design Parameter% J2 i; k1 ^7 Q$ V& r q6 L7 U
1267541 PSPICE PROBE pspice.exe does not exit when run from command line. e: w' K# q$ w6 a
1267707 ALLEGRO_EDITOR PLACEMENT Mirror Command - preselect/postselect bug with general edit mode ( w* s$ }7 H5 w1 j- |1268299 PSPICE STABILITY Pspice crash on attached design ; b9 ]& Q& n: q# d/ u" K& V) y1270879 ALLEGRO_EDITOR COLOR Color view save creates .color file using older extension' U1 k1 R/ C+ C5 B
1271295 SIP_LAYOUT DIE_STACK_EDITOR Die stack editor support needed for large variant combination designs." }" E" d) y, o
1271385 CONCEPT_HDL CORE Locked property can still be added : X1 M, u. S* o# v0 e! z* y6 ^! x# W1271853 APD OTHER When using the beta "shape to cline" command, add improved messages and partial completion of individual segs in error. * i7 d/ z" `/ V1272197 CONCEPT_HDL CORE concepthdl_menu.txt contains invalid Variants menu6 K9 y! t, G! H
1272318 CAPTURE GEN_BOM BOM_IGNORE not working for Capture BOM on hierarchical designs. , Y% Z* L s0 u, ^( M1272743 ALLEGRO_EDITOR PADS_IN PADS Library Translator does not open the Options dialog window.8 h* S9 s) r: E& ^
1273517 F2B PACKAGERXL Netrev error - ERROR(40) Object not found in database6 |9 j$ v7 H* }2 h
1274000 ALLEGRO_EDITOR DATABASE PCB layer can't be removed , \8 R9 m$ M1 U& u; M1274530 ALLEGRO_EDITOR INTERACTIV Add Circle radius value changes next time using this command1 u/ [) i5 m6 ?
1274697 PSPICE AA_MC pspiceaa crashes when running Advanced analysis monte carlo for the attached design - M0 B: g! v4 x. j1275154 CONCEPT_HDL CORE Hierarchical Blocks lose ref designators when moved to another page/ v y1 c1 Y: v: g, `$ s
1275724 GRE CORE AiDT delete another clines( e1 {/ F2 m+ T; X8 g
1275831 ALLEGRO_EDITOR DRC_CONSTR Waived DRCs return when using multi-thread DRC check + `* H, X0 O7 I X8 \: A& E1275834 CONCEPT_HDL CORE ERROR (SPCOCD-569) on global bus $ p% j; ?, v o9 G* F, D1276334 ALLEGRO_EDITOR PADS_IN PADS Library Import problem with outlines / X4 S7 F1 T) A; S- g1277062 ALLEGRO_EDITOR PLACEMENT Swapping parts from top to bottom Orientation changes) F8 O" ?8 D9 g
1278746 ALLEGRO_EDITOR DRC_CONSTR Package to package DRC allows place_bound_top in 0 spacing has drc in 16.6 version.# @3 G H8 [) u0 e! D( B
1278804 CONCEPT_HDL COPY_PROJECT Copy project crashes ; G+ O6 R% L' J' [& Z1279362 ALLEGRO_EDITOR INTERACTIV User SKILL file makes Allegro Icons gone away * d, w" {1 @/ Y, R- \% r1279619 ALLEGRO_EDITOR DRC_CONSTR Netgroup in a Netclass doesn't inherit Spacing Cset 3 ~% c! c+ n) Z6 Q; c- \# g1279815 CONCEPT_HDL CORE Text > Change and RMB Editor does not allow multiple text edits % V! E& \6 L9 U1279876 ALLEGRO_EDITOR DATABASE Using the Curved option in Fillets results in a pad to shape DRC: D" {& Z8 |) f" |
1280435 F2B BOM BOMHDL with variant repeats the PART_NUMBER value* X* ^+ [8 S( W
1281669 CONCEPT_HDL COMP_BROWSER Match Any radio button in Component Browser didn't work.* u+ P! T: \. {! M7 I% H2 G
1282001 ALLEGRO_EDITOR DRC_CONSTR Updating the DRCs on this design cause the DRC count to change on every update $ g# n6 ~; O, h5 E( A1282480 SIP_LAYOUT WIREBOND Info on the Wire Count property needs to be updated indicating that it is a User Defined Property- M/ d% K m \- b
1283952 ALLEGRO_EDITOR PLOTTING Published pdf does not show dotted or phantom lines " O3 o, W+ ~" s5 f3 ^0 F b s1283957 ALLEGRO_EDITOR INTERACTIV Replace padstack in "Single Via Replace Mode" is changing netname of the vias with the latest hotfix of Allegro 16.6 6 U' h, }% z$ k/ W1285588 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase control has wrong analysis result when add rectangle test bead in Clines.- q" y- [/ m/ E
1286743 ALLEGRO_EDITOR SHAPE Getting copper islands in the design after running the Delete Plating Bar command! S7 P: f6 R- T& ^( G$ ~8 ?# Y
1287215 ALLEGRO_VIEWER OTHER Allegro viewer plus does not support constraint regions ) P- Z6 q: n: \4 v( n6 M! q6 ?& e1288808 APD LOGIC Derive Assignment stalls out or won?t finish and appears to run out of database room. 6 J! S# w1 t7 W1289251 ALLEGRO_EDITOR SCHEM_FTB Pin escapes (clines and vias) not inheriting new net name from a pin with a new net name.: m! ]1 E. O0 F( a6 }1 h
1289293 F2B DESIGNVARI Warning 04: Cannot merge the variant properties on variant instance C119 component with same canonical path not present$ n0 R7 T- G9 B2 P# C* X( E
1289809 SCM VERILOG_IMPORT User not able to import a verilog netlist into SCM / _$ U8 g; T1 }& r; ]. q1290696 CONCEPT_HDL CORE Copying a net name repeatedly causes it to go off grid. j9 D5 V3 g2 w9 c
1291162 CONCEPT_HDL CREFER crefer crashes when selecting generate cross refernece for all nets selected 5 f @6 V5 ~& i5 J5 @1291285 SIP_LAYOUT IMPORT_DATA Replacing a Die with the Die Text in Wizard causes some Clines to Shift, creating new DRCs. W' y" S* I4 W' D1291658 ALLEGRO_EDITOR INTERACTIV Cannot add Frectangle to Group 8 K( b, I6 ?' W( s& b1292180 ALLEGRO_EDITOR SKILL Allegro Crash while performing query contents of "Maximum_Cavity_Size" with the skill command 'axlDBGetPropDictEntry'$ K4 r, [% }& V
1292210 CONCEPT_HDL CORE DEHDL crash if design was opened with -nonetlistuprev option. 7 W# C- M7 t/ A1292278 SIP_LAYOUT WIREBOND When creating Wirebonds by Importing a Wirebond File, (wbt) the wirebonds are not on the correct Die layer9 Z: U9 l( u2 d8 w$ G( ~
1292282 SIP_LAYOUT INTERACTIVE Getting Multiple GUIs when the Wirebond Import is open and we select outside the command GUI. 9 }- P/ ]5 q1 n' p' `6 K& e$ h1293381 SIP_LAYOUT IMPORT_DATA Import SPD2 error9 p( b( t- ?( Y
1293889 CONCEPT_HDL PAGE_MGMT page name regression result deleted by netassembler y4 T' D u, E M
1294124 ALLEGRO_EDITOR INTERACTIV Samsung Mobile division wants to disappear the grids in the display window when zoom-out function executes in the allegr # t2 @7 `2 O( U. b( r1294749 ALLEGRO_EDITOR ARTWORK Null pad is flagged as an error that break Thales automatic tape out! [8 H) r8 H1 V0 j5 Z' B
1294777 ALLEGRO_EDITOR SYMBOL Mechanical symbols missed on STEP result " m: U) Q. H V, `! g" z7 q( v" `$ \! c" ]
DATE: 06-20-2014 HOTFIX VERSION: 0319 _4 c3 k3 A9 h- l: Q! ]5 s
=================================================================================================================================== ! c) P; b/ T* E5 U3 W u0 TCCRID PRODUCT PRODUCTLEVEL2 TITLE $ F k& u( a C& I$ k$ r6 ]% C===================================================================================================================================7 ~6 \% X$ t0 k0 c( I% `
726553 FSP CAPTURE_SCHEMATI Method to select bus bit?s order while generating Capture design from FSP. . b: K8 l4 e6 N: q1257631 FSP DE-HDL_SCHEMATIC Schematic Generation selects incorrect symbol version 9 ?" [6 v5 i, L: N; Y. v5 ~, i1273456 ALLEGRO_EDITOR PLACEMENT Place module instance causes Allegro to crash- W' r# K. ^+ O" V- ?* R Z- s8 G
1277099 ALLEGRO_EDITOR INTERACTIV Clines and pins are disconnected even though they are at the same x, y coordinate. 8 b, F+ [ a% k5 ?+ i$ t8 n3 G/ U1280913 ALLEGRO_EDITOR EDIT_ETCH Add Connect should be able to be made by go straight even though the cursor is not exist on straight line 2 Q' t4 d, T7 T9 l1 {1282491 ADW PURGE ADW PURGE is removing Page Name data in DEHDL * I1 i6 A Z0 _3 Q! y( V! s1283045 ALLEGRO_EDITOR DATABASE Ecset not getting downreved. 9 G* D) ^8 r9 E$ R1283138 SIP_LAYOUT IC_IO_EDITING symed app mode chooses wrong text block sizes for I/O driver inst names9 V4 d6 i2 K( b0 E5 ]
1283227 PDN_ANALYSIS PCB_STATICIRDROP Enhancement request to add 32 bit files for IRdrop # }0 w% G9 O" u) }9 V1284656 CONCEPT_HDL CREFER Crefer fails on large design + l: p5 R6 f) u( \ c$ G" [! ^1285814 CONCEPT_HDL CORE DEHDL crash on opening the Design, o$ D. Z4 T0 {( }
1285967 ALLEGRO_EDITOR EDIT_ETCH Slide via in circle pad9 c/ R# G! H% I3 s3 \, j( v- f( m
3 |. A! {* m% G: ?2 BDATE: 06-12-2014 HOTFIX VERSION: 030 ) y. t" T0 r0 Y7 m, T! R' E* i===================================================================================================================================9 |; d) q$ g! n1 D k& Q- ^
CCRID PRODUCT PRODUCTLEVEL2 TITLE , k' \( b3 {5 F=================================================================================================================================== ; W8 C2 |% N: Y3 A8 B$ k982961 ALLEGRO_EDITOR PLACEMENT Show the Rats when one selects physical symbols to place them! U) @2 M( \! X3 l9 c* F/ U) P* t
1138680 FSP POWER_MAPPING Ability to assign decoupling capacitors in spreadsheet like application1 `$ M$ a( ]8 U9 c4 k. W) z
1243410 SIG_EXPLORER EXTRACTTOP Circuit topology extract failed in case of CLASS+ Z" q6 S5 ~! M) q/ J, G/ [6 ]
1262977 ALLEGRO_EDITOR TECHFILE When importing a certain tech file into an empty .brd Allegro crashes. 2 G2 ?* i( p- s9 p5 x1267558 ALLEGRO_EDITOR INTERFACES Arc part of symbol pin missing in 3D view of step model9 z. D8 v/ x* m
1268252 ALLEGRO_EDITOR GRAPHICS step place bound issue(3D View) e; K: t0 r2 K6 z, a4 Y
1270450 ALLEGRO_EDITOR INTERACTIV footprint add line on line crash 0 C& c# w+ k M; k- t% Z6 y4 d1270962 CONCEPT_HDL PDF PDF Publisher command line does not print pdf file if double back slash is present6 V- n% x" K& y% Q0 E5 K) G
1270964 ALLEGRO_EDITOR MENTOR Mentor translation crashes with no errors in log file " f( @% Z6 c: D9 x9 B: ^( _1270999 MODEL_INTEGRIT TRANSLATION ibis2signoise Issue & m* I5 ^2 {) H! c1 ?8 V3 G1271543 ALLEGRO_EDITOR PAD_EDITOR Library import reporting missing padstacks; G3 C5 Z/ {- k- M
1272099 ALLEGRO_EDITOR GRAPHICS Plotting does not fill shapes ! C, z. M8 O7 C1272406 ALLEGRO_EDITOR DRC_TIMING_CHK SKILL command 'axlDBTextBlockFindName' returns 1 when nil is expected , I5 @- n8 M$ k/ T" q% A1272748 ALLEGRO_EDITOR GRAPHICS 3D viewer crashes on this specific testcase 6 m7 q% H) J1 o2 H6 j1272793 ALLEGRO_EDITOR GRAPHICS 3D view doesnot displays hole with offset correctly2 S% ]. x/ Q/ K( V3 ^& i
1272863 ALLEGRO_EDITOR INTERFACES Ability to find the origin of STEP File in order to place it exactly where it needs to be on footprint during mapping.1 D- T; S0 _. D
1273264 ADW COMPONENT_BROWSE hyperlinks not recognized in the component browser5 o. h8 s' I) Q7 B- t" W6 ?
1273304 CONCEPT_HDL PDF Publish PDF from commandline does not work if there are spaces in the Path $ z k# I- T' d# H1274661 CONCEPT_HDL CORE I can't copy a property from one component to another- D- N' i; n; ^* O$ e* o E
1275237 ALLEGRO_EDITOR DATABASE Allegro Crash on running DBDOCTOR for a board& E5 v. h1 I0 L. f0 s& g
1275345 CONCEPT_HDL CREFER The Xref information page number values are incorrect9 i6 p2 X( E1 x& y; @$ r
1275748 APD IMPORT_DATA WireBond starts away from the Die Pin after importing Die using Die Text In Wizard / h I a0 e4 d! u" F/ T4 ?1276270 CONCEPT_HDL CORE DEHDL crash by Zoom In > Ctrl+A > Move; o5 H: u3 ]* |6 |
1277735 SIP_LAYOUT IMPORT_DATA sip layout spd2 translator issues with offset die and mirroring 8 ~! m! T w8 q1 A6 O3 e, G/ o |8 b1279258 CONSTRAINT_MGR OTHER Import logic stops with error 4 a8 S" ?$ L; O& f: y1279694 ALLEGRO_EDITOR SKILL axlCNSSpacingMin('via nil) crashes Allegro PCB Editor- Q8 o+ U' K$ h6 `- D+ E2 i6 [
! H+ E% i: ^- K+ A+ k, B/ oDATE: 05-23-2014 HOTFIX VERSION: 0294 z. a/ ~" _4 M1 d3 ] }6 c6 O
=================================================================================================================================== 4 M+ o1 u4 E8 _1 NCCRID PRODUCT PRODUCTLEVEL2 TITLE ; g( T# U! u0 X% }9 L=================================================================================================================================== " u" H, F* s& ]7 ~1 M: U' }1209461 FSP DE-HDL_SCHEMATIC Hierarchical Block Size not automatically adjusting to text needs% {- s; I( f- Z; H
1217832 SIG_EXPLORER SIMULATION S-param generated by SigXP doesn't match with HSPICE/ADS.# P% q5 p: ]/ A& @
1263575 CONCEPT_HDL CORE Copy-Pate makes Components Off-Grid' u' A/ L# b4 P% Y5 N1 v
1267602 SPIF OTHER Route Automatic hangs" m \" n$ X B; R
1268022 FSP PROCESS FSP is not respecting the use banks for attached design. P; S G0 {! u( k4 u" j4 B1268587 ALLEGRO_EDITOR INTERFACES Enh. Preserve relation between hole and padstack in IPC-2581& i, J9 T5 D/ ~2 b! O
1268918 SIP_LAYOUT DIE_ABSTRACT_IF SiP - DIE export from co-design object to XDA results in missing data6 d- T5 ^6 s4 h% }6 a
1269232 CONCEPT_HDL INFRA While pspice uprev the design crashes e7 H7 D( Q7 @1269825 SIG_INTEGRITY SIGNOISE PCB SI hangs when running crosstalk simulations ; f$ Y5 Y+ a7 ~( y P, m& T1270963 ALLEGRO_EDITOR GRAPHICS Add Circle lint font hidden/Phantom has resolution problem3 ?$ ?+ F; ^: d: F+ F# |+ i4 s" b
1270990 ALLEGRO_EDITOR GRAPHICS Allegro response is slow when added circle : s6 N7 D1 r2 p$ ~$ u1271655 ALLEGRO_EDITOR MANUFACT Dimension option causes a generic crash, reproducible in any design. f8 r# J" t2 r b" D( f* F+ T
1272495 ALLEGRO_EDITOR MANUFACT Filtered Part numbers in IPC-2581 still pass actual part number for references onutide of BOMItem 9 j2 S/ n5 c9 B1272839 ALLEGRO_EDITOR MANUFACT Kindly explain the drill legend behavior when padstack rotation is 45 degrees and mirrored ? 9 J' J1 Z3 w$ o3 q& o* p. @, q1274518 ALLEGRO_EDITOR ARTWORK Artwork does not create void correctly.( X/ P H9 p# j$ c4 z" ^
% j& O: z8 P0 i" A1 g, ^DATE: 05-10-2014 HOTFIX VERSION: 028) |) y. t T0 u- c0 M# q
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CCRID PRODUCT PRODUCTLEVEL2 TITLE 2 y5 s* }! n" n===================================================================================================================================; M0 B' M" L, h& b C, D. B/ U+ q
1199256 ALLEGRO_EDITOR INTERACTIV DFA bubble does not appear when moving a symbol to within another symbols dfa bounds on specific symbols # ]/ X7 r9 u- O! t3 w! x0 H1 O1220196 ALLEGRO_EDITOR OTHER create xsection chart results in ERROR(SPMHA1-73): Text line is outside of the extents./ }7 f) s, i* {, R+ U) b0 k
1259520 ALLEGRO_EDITOR EDIT_ETCH Allegro will crash when adding connections to a differential pair. 7 h7 ?3 M) e* K' m; J1260446 ALLEGRO_EDITOR VALOR Creating odb output the xhatch shapes where arcs are will become inverted. Difference in the geoms.out extraction?- H, ~' m9 {: ~8 M5 E0 S* r9 d
1261313 ALLEGRO_EDITOR INTERFACES Step mapping does not show all Available Packages # k9 g' K0 c# A1 }" T4 s% t1261356 CONCEPT_HDL CREFER crefer is crashing with generate for all nets option ! _! L; z9 M9 U: A$ I* X1 p1261514 ALLEGRO_EDITOR ARTWORK Exporting raster artwork with overlaping voids fails. 9 U) J' K. {4 l/ U, o5 y1261735 ALLEGRO_EDITOR ARTWORK Presence of Smaller shapes inside bigger shapes is crashing artwork generation.3 E1 C+ O: q7 G! ^# X
1262019 ALLEGRO_EDITOR INTERFACES Artwork control form hangs if we close PDF publisher gui6 z; N5 Q4 O& M x1 J/ `; j6 V
1262246 CONSTRAINT_MGR ANALYSIS Constraint manager shows ALL PASS when Adding members to a NetClass and adding parallelism rule; t+ K+ @( T5 _# ~
1262560 APD WIREBOND bondwire can't connect to GND ring directly; x5 Y3 j" {* f/ v0 \" C# l6 `+ q& C
1263275 CONSTRAINT_MGR OTHER Import of constraint file hangs in this design+ y7 d# z6 Y, h3 M+ o) z
1263358 SIP_LAYOUT OTHER SiP Layout - Void adjacent Layer enhancement to merge voiding for PADS without changing shape params7 M8 o$ X: v7 `/ R/ j
1264109 ADW LRM LRM error - WARNING(SPDWREV-7): Unable to read the design x; t. |& I' B
1265580 APD MANUFACTURING Icp_soldermask_allow_pins cannot create correct solder mask when the pin rotate. 2 } X& o- i' \ E& V% |4 a0 I1266391 APD LOGIC SPB16.6 Derive assignment : want to select 1 DRC marker only. ! ?2 ^$ j% a' v% m0 e" g1266687 ALLEGRO_EDITOR SKILL The SKILL p4 M6 ?: H' |7 T5 V: w/ g+ f+ W
1267267 SIP_LAYOUT WIZARDS Attempting to create a die using the die text in wizard but the tool is not creating the correct die outline ) w8 C& u# H) t) L* a1267308 SIP_LAYOUT OTHER When updating a BGA with the Symbol Spreadsheet tool it will start, update a few pins then stop. 0 y% i! R/ c8 |/ k O. \0 \; w0 _2 A1267639 ALLEGRO_EDITOR PARTITION Allegro crashes when partition is created and opened from a location that contains "!" in its path.' B) ?9 J6 g; O$ a( p
1267704 SIP_LAYOUT STREAM_IF Cannot import stream file, the tool starts scanning the file and never stops. ; H& O8 U. f' Z* W1267907 CONCEPT_HDL CORE Ctrl+RMB Context Menu Option doesn't work.+ Z1 i0 l3 W( S6 Q
5 n) j5 Y: l' MDATE: 04-25-2014 HOTFIX VERSION: 0274 W z, z. U! L9 ^5 C
=================================================================================================================================== # R* u( g( E, LCCRID PRODUCT PRODUCTLEVEL2 TITLE % t( D+ f5 G2 G3 L4 b=================================================================================================================================== & f* |+ d6 x: |; R2 `( |308701 CONSTRAINT_MGR OTHER Needs to delete user defined schedule in CM ; u# T3 { L$ p5 d481674 ALLEGRO_EDITOR PADS_IN No board file saved from PADS_in: G3 p. v# W `' r
982929 ALLEGRO_EDITOR EDIT_ETCH can't route on NC pin and other that are not pin.# |4 f. Y* L$ t7 O
1012783 FSP OTHER Need Undo Command in FSP 2 @+ H* r) K" i1 t3 z6 G1017381 ALLEGRO_EDITOR DRC_CONSTR Need Dynamic Phase to be able to measure back to the Drive Pins." h, m% C6 l9 Y: {0 E Z: F B" K
1072673 PCB_LIBRARIAN GRAPHICAL_EDITOR Copy paste goes offgrid if mouse is moved" F+ n7 D1 L- }- C2 c8 [7 w0 O% D
1073231 CONCEPT_HDL CORE Copy-paste of signal names goes off-grid in Windows mode. 4 K @$ C! E3 a' x1105371 CONCEPT_HDL INTERFACE_DESIGN Strange behavior when shorting two Net groups, e7 f" J3 p) G. h$ f3 D
1116498 CIS LINK_DATABASE_PA link database with modified part results in Capture crash ; n8 m* F2 v; F1118632 ALLEGRO_EDITOR GRAPHICS Text display refresh issue while in Edit > text command( S! B( q2 E- G# q1 z6 |* E! w$ {
1155821 SIG_INTEGRITY LIBRARY Xnet are not recalculated correctly when model is changed on the Series switch part defined as discrete with Espice mode$ H" E2 A$ E/ R9 `
1157372 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase for Diff Pairs not reporting back to Driver pin if pin escapes present ' ^- v5 r2 L j3 @8 B- C% ~) ^1171951 ALLEGRO_EDITOR CREATE_SYM Jumper has a limited of count when it add to list.! f- l" J/ y3 {
1180871 CAPTURE LIBRARY_EDITOR Copied parts don't retain pin name and pin number settings 8 k5 S7 f- `# l6 K1185575 SIP_LAYOUT DIE_STACK_EDITOR Updating symbols causes the graphics for the Assy layer to change from Bottom to Top. ' M' V. L' }9 l1185772 PCB_LIBRARIAN CORE VALID_PACK_TYPE warning when cell was opened in PDV8 A) t! O4 `, X: ^3 q# k/ s6 E
1192377 CAPTURE SCHEMATIC_EDITOR Pin name/number position is incorrect on schematic if it is changed for a rotated part. 2 C7 S( p; [( c% T, N4 c1202654 ALLEGRO_EDITOR GRAPHICS Zoom using mouse wheel shall maintain the center co-ordinates % d# E) U% c" _- p# h2 O% R/ [1208031 ALLEGRO_EDITOR INTERACTIV Snap to Pin for via during Copy command do not snap to connect point everytime: k8 D9 N; S( P) N- e9 ^
1208478 PSPICE PROBE Attached project gives overflow error with marching ON. : f) r8 B) b. v6 H1210015 CONCEPT_HDL CORE The value of $PN should be not turned on spin or rotate symbol 4 |- D* G5 x* M1 E, v1210425 CONCEPT_HDL CORE When moving a circuit tool reports that connectivity has changed / D+ B, _4 f" x- x+ V, p W1215858 ALLEGRO_EDITOR SHAPE Force update does not void cline with the shape* j( c% ?8 @2 p9 a. {
1215906 ALLEGRO_EDITOR SHAPE Dynamic shape fill smooth failed when copying to other layers% u) P1 O3 c+ ?2 d* G+ w
1216358 CONCEPT_HDL CORE Can we improve our export BOM function to check if user did export physical function before exporting BOM?& M6 c! }: t9 i, Q1 s) O
1217364 CONCEPT_HDL OTHER Netlist reports fail because error: GScald failed. : C; k! ^7 m) O- x; B0 b9 i0 u1217529 CONCEPT_HDL CORE ADW checks do not catch single quotes in PTF values * V$ |2 q' M! H9 L1217556 F2B PACKAGERXL signal name change not sent to Allegro after packaging & s% }* b$ E1 C" E* w/ p1 X' T1219283 ALLEGRO_EDITOR DRC_CONSTR Show constraint is inconsistent when displaying region information / I' L; f# ?6 Z4 ?' u1220078 F2B PACKAGERXL Export Physical crashes when ALL the part pins are added0 P O9 |5 c4 E( K0 s) k4 F
1220393 CONSTRAINT_MGR CONCEPT_HDL HDL import physical from board file will annotate CM data back to HDL which includes cross-section thickness.1 L0 O3 |6 q2 E" H
1220540 ALLEGRO_EDITOR GRAPHICS Need an option to see the pads inside the internal plane shapes " `" R# q6 `5 [; x1220936 CONCEPT_HDL CORE About crash by vpadd/vpdelete command on Linux ' N7 B) y# U7 D1221059 ALLEGRO_EDITOR DRC_CONSTR Get a "Shape to Thru Via Spacing" DRC error only the first time when the shape is manually voided. E& G' A& I: ^' B% {1221182 ADW TDA Team Design with SAMBA 4 F; Z* c, u" J. ?6 H8 @ k# R1222442 CONSTRAINT_MGR UI_FORMS Duplicate pin pairs appear in DiffPair 7 i& M4 f4 s2 i) a8 Z9 `3 R1223175 CONCEPT_HDL CONSTRAINT_MGR Schematic crashes when opened) U" k+ g+ Y9 u$ h9 \+ F
1223533 ALLEGRO_EDITOR GRAPHICS Why the through pins for STEP models are shown at an offset when viewed in 3D inside Package Symbol?7 j9 P4 s& d# f
1223680 CONSTRAINT_MGR ECS_APPLY Improve ECSet mapping by allowing user to address ambiguity of Parts / L, X$ U! ~; _+ i9 h6 |1224156 SIG_INTEGRITY SIGWAVE Exporting spreadsheet with filter Subitems in SigWave exports all waveforms4 _& m9 r; m: u6 H1 ?% |7 s* }7 v/ D
1224417 ALLEGRO_EDITOR PLOTTING Hidden font pattern is not showing correct in 16.5 version also 16.6 version. ' f6 v. b2 C0 T2 }( K1224704 F2B DESIGNVARI There is no lock for the variant.dat file - multiple users can open the editor7 R- ^ a. `( L+ R3 Q/ g# l" N# u. V6 u% r
1224968 ALLEGRO_EDITOR INTERACTIV Delete >(RMB click) Cut> Snap Pick to>off grid loction does not work for lines. 8 y( Z% ^2 p8 e2 ?1224982 CONCEPT_HDL PDF commandline publishpdf does not work when there are spaces in the path 9 Z2 [: r- `( V; w+ }1225114 CAPTURE GENERAL H-pins added after netgroup pin get color as of netgroup pin 5 C- H. D* Y7 x1225494 CAPTURE DRC Different DRC results for Entire design and selection# N+ O4 M0 R+ H* F# C
1226153 ALLEGRO_EDITOR INTERFACES Export STEP should include PART_NUMBER property ; P( b: W' a/ d- U. f1 |- q1226235 ALLEGRO_EDITOR EDIT_ETCH Enhancement to include Pin_delay of descrete forming Xnet 3 b+ z* V" a3 m& J! |1 k% z2 B1226372 CAPTURE GENERATE_PART ENH: Functionality to add pin spacing in New Part From Spreadsheet , F: K6 Z/ x4 d! j+ g1226477 CONCEPT_HDL CORE DE HDL縮 `Allowed Global Shorts� function is inconvenient for Global Signal : U5 T5 G! O0 N6 W% Q" r% G, F/ i1226813 SIP_LAYOUT LEFDEF_IF ERROR SPMHLD-120 when importing a DEF file. Request to increase the number of characters/line in a .cml file. m0 Y; ^/ r' c
1227453 ALLEGRO_EDITOR SHAPE Addition of Fillet generate Pin to Shape Spacing DRC errors and DBDOCTOR errors; U# W, s' R7 \; f4 b, `* L6 A/ R
1227461 ALLEGRO_EDITOR SHAPE Sliding a cline for certain net changes the thermal relief connects for pins connected to another net from 4 to 5,6,7,8 ' M8 ^' p2 b/ H1227469 CIS DBC_CFG_WIZARD Oracle Views not visible on Step2 of CIS Configuration; d ?, i- \8 q; {) ]8 D
1227780 CAPTURE ANNOTATE Inconsistent behaviour when annotating heterogeneous part 7 g+ [0 N. n% d8 f1227831 CONCEPT_HDL CORE Pin text and H-block name in upper case5 H* n+ S M$ ?* t
1227954 CONCEPT_HDL OTHER supress check for global signals when wires are unconnected to pins ' ~1 L: Y+ A0 @- l1228190 ALLEGRO_EDITOR OTHER Unable to close the 'usage' window during license selection ; }+ Z* E, j5 W) i/ ]! _5 E1228899 CONSTRAINT_MGR INTERACTIV Export/Import constraints in "overwrite" mode from same design shows different results when imported second time. 9 g" i% `$ O6 G6 n3 X) {1228934 ALLEGRO_EDITOR EDIT_ETCH The "View Active Layer" option like the Board Station should be provided for dynamic layer visibility. 9 |) t: j5 h6 K7 X! l9 `1229316 ALLEGRO_EDITOR EDIT_ETCH When routing with Hug only enabled we were able to route through other routes(sometimes Hug).' _5 R: G e; e8 }! ?, B
1229545 CONSTRAINT_MGR OTHER Allegro indicate bundle scheduled nets in CM * F( d0 q7 @& h9 H) T- ^, q+ ^( ]3 y1230056 ALLEGRO_EDITOR GRAPHICS Bug: 3D View of Mechanical Symbol with the drill hole defined% K. G+ E# d- e* i, Q. E) I
1230432 CONCEPT_HDL CORE No Description information in BOM) {, Q2 X9 G0 D) j+ d
1231148 F2B DESIGNVARI The variant.dat file is not updated with library PTF changes& l3 w* B( l2 @4 S
1231625 F2B DESIGNSYNC VDD at command line needs to support sch2sch and test variable to write out report files ' p# b6 t( v9 R6 k0 x1231697 CONCEPT_HDL CORE If any locked files exist force a pop-up dialog restricting certain commands ' c9 H$ m7 h) ~5 e1231767 CONCEPT_HDL OTHER Unable to find under the search options single bit vector nets' G- t* O/ y" p) }2 T ]
1231961 ALLEGRO_EDITOR SHAPE Shapes not updating to smooth unless we use force update and as a result false DRC's appear in board.* B' C6 o0 U: f! o7 R6 o
1232100 CONCEPT_HDL SKILL Unable to execute the SKILL commands in viewer mode ' s' w' l* I1 ? ^0 W4 s+ I1232336 CONSTRAINT_MGR CONCEPT_HDL cmFeedback takes 5hrs to complete during Import Physical7 P2 q: J) w* X6 j) ^" S' Q; a3 C
1232710 F2B DESIGNVARI Dehdl crash while moving component in variant viewer mode0 [7 e- p9 s# ?/ g% a/ j+ I
1233894 F2B PACKAGERXL The page data is missing in the pst* and PCB files' y! }1 t$ d1 C4 C' s
1235785 CONCEPT_HDL CREFER cref_from_list custom text is not subsitituted in complex hierarchy 6 X% t0 k4 i3 ~2 S3 C1235928 CAPTURE SCHEMATIC_EDITOR OleObject modifications not saved ) P+ L" Q. r1 C; k3 K' m1236065 CAPTURE PART_EDITOR Mirrored part after being edited get pin name locations incorrect ; T( O! Z! q- X2 S1236071 ALLEGRO_EDITOR SHAPE Airgap for Octagonal Pads ignores DRC Value when Thermal set 7 Q& o+ F( m$ m1236072 CONCEPT_HDL CORE Page 122 cannot be saved as logical page 119 has different page mapping in connectivity data and schematic7 _" f4 z( H# \
1236161 CONCEPT_HDL CORE Import Design shows the current project pages( C( y! a2 P: H! a
1236432 ALLEGRO_EDITOR PADS_IN pads_in doesnot translate via and shape in some instances.7 z v* `0 I2 }+ r5 h- ?
1236557 CONCEPT_HDL PDF Running Publish PDF on command line in linux doesn't output progress until completion0 [& @4 N3 H# R" Y: a
1236589 CONCEPT_HDL PDF Enhancement license failure error should appear in pdfpuplisher log file / N A4 e; {! {: P: Y9 [, i) B5 Q1236644 ALLEGRO_EDITOR EDIT_ETCH create fanout deletes shape 2 ?6 ?5 H2 w0 H& B4 m- A2 e1236689 ALLEGRO_EDITOR GRAPHICS Graphics displays extraneous lines when panning or zooming7 j; S+ l0 A8 q" w
1236781 F2B PACKAGERXL Export Physical produces empty files ; K' |, f8 g# h1 y2 W3 p+ }1237331 PSPICE ENVIRONMENT pspice.exe <cir file name> - hangs when run 4 I9 d4 w* M D6 R9 g Z1237400 CIS EXPLORER Capture hangs on 2 consecutive runs of `refresh symbol from lib� command 2 \0 c3 U- B) v1237437 CONCEPT_HDL CONSTRAINT_MGR CM Crash when saving after restore from definition + s) J: m7 p) L7 s+ B( S/ a; W# K* I1237862 CONSTRAINT_MGR OTHER A way to remove the RAVEL markers from the Constraint Manager.% n2 e& I) n# y
1238852 CAPTURE GENERAL signal list not updated for buses, _2 a2 O& Z, {+ h7 v. h$ o
1238856 FSP DE-HDL_SCHEMATIC FSP schematic generation crashes 5 }* Y& y' k" k1239079 ALLEGRO_EDITOR INTERACTIV The 16.6 Padstack > Replace function leaves old padstack. ( T$ w3 C2 P- d1 W0 n1239706 CONSTRAINT_MGR ANALYSIS The reflection result on a differential signal in the CM when Measurement location is DIE, `! k! n* c. y4 R/ u' @% {
1239763 PSPICE PROBE Cannot modify text label if right y axis is active ! v/ T; @9 o" Z2 I! e' u1240276 ALLEGRO_EDITOR GRAPHICS Printing to PDF from SigXp is giving unreadable images* {8 u" n* A/ ~* n( d% j% g6 W9 `% U
1240356 CAPTURE IMPORT/EXPORT Can縯 import SDT schematic to Capture. 7 m# N5 w; j: `( @" K1 e% j1240502 F2B PACKAGERXL Corrupt cfg_package does not stop PackagerXL from completing j. a& I* D* y" H, I w; O9 ?0 d1240607 ALLEGRO_EDITOR OTHER Footprint of screw hole got shift in DXF file+ v3 `2 T) G1 ]* N0 @. p' q1 t
1240670 ALLEGRO_EDITOR PLACEMENT Select multiple parts and Rotate makes them immovable) }2 X3 [; M1 I7 I) P% W3 h
1240773 CAPTURE DRC DRC check reports error for duplicate NetGroup Reference in complex hierarchy4 I' Q1 n( N: i
1240845 SIG_EXPLORER EXTRACTTOP Narrowband via models for Mirrored BB Vias not extracted in in the interconn.iml and this gives bad ringing in waveforms $ u& x! r0 S. n B, |# u$ l1241634 ALLEGRO_EDITOR OTHER Netshort for pad-pad connect not working ( {- a/ I$ h/ } ?5 {/ U1241776 CONCEPT_HDL CORE In hierarchal design not all pages are getting printed. ! J0 c! B8 S6 g1241788 CONSTRAINT_MGR CONCEPT_HDL Issues with changing focus in Constraint manager using keys on keyboard+ I7 Y1 I8 Q* p3 U4 C! K7 I7 R
1242683 ALLEGRO_EDITOR INTERACTIV Color View Save replaces file without warning & O% Q# v3 O8 ^ T3 ^" ~6 v1242818 ALLEGRO_EDITOR PLACEMENT Placement edit mirror option places component on wrong side+ ~0 A% g! U0 W' H; Z$ |9 z
1242847 ALLEGRO_EDITOR GRAPHICS Need an option to suppress Via Holes in 3D Viewer6 P: w; K# t: R. r. f
1242923 ADW COMPONENT_BROWSE UCB reports Missing From DB only after selecting the Row in the search results# }6 ^! S; e% w0 X- R4 ^( U! r; l
1243609 CONCEPT_HDL CORE autoprop for occurrence properties& W3 g8 U. e! }3 @) V7 O' e
1243682 F2B DESIGNVARI after undocking variant icon cannot be redocked back to GUI+ l% `+ D1 Y/ P: v
1243686 ALLEGRO_EDITOR GRAPHICS Invoking Edit->Text, the infinite cursor disappears until edit mode is changed. 2 k) O2 [, r9 M# a% h. r1243715 CAPTURE PART_EDITOR Pin name positioning get changed after rotating or mirroring + g R+ T) o* S1244945 CONCEPT_HDL PDF PDF Publisher does not include image when file is not located in the root folder ! K+ c! Z% u2 O+ {1245568 CONCEPT_HDL CORE Dual unselect needed for wires attached to other net/source and property is not deselected when component is - ?) M" M* q& r8 |: F# P. p7 _( I1245819 F2B PACKAGERXL wrong injected properties information passed during packaging of the design 2 ~0 J4 a$ W7 d9 M1245916 SCM CONCEPT_IMPORT Where does the folder location reside for DEHDL imported blocks? $ o2 u0 A+ p* y' `& T1246347 CONSTRAINT_MGR CONCEPT_HDL DEHDL crash if environment variable path has trailing backslash character - |. ^+ s1 O9 G0 v* b+ z3 C$ K1246896 ALLEGRO_EDITOR DFA DFA_UPDATE on Linux reports err message if the path has Upper case characters- `$ n4 m( w2 g+ d! j$ w6 ]5 U
1247019 SIP_LAYOUT DIE_STACK_EDITOR SiP Layout - refresh/update symbols is mirroring the assembly drawing data on DIE that is placed ChipDown0 i* q" r) _) P$ X
1247037 CAPTURE LIBRARY_EDITOR Copy & Paste of library parts resets pin name and number& w9 \& L4 \' }9 _1 {
1247089 CONCEPT_HDL CORE Group Align or Distribute > Left/Center/Right crashes DEHDL5 C+ v6 U) h& @, z- I6 P
1247163 CONCEPT_HDL PDF Physical Net Names in PDF not maintained 7 \7 j- B- Z+ Q) H1 z+ O1247462 CONCEPT_HDL CORE Text issue while moving with bounding box* |, V5 R1 D) V3 r. K
1247464 ALLEGRO_EDITOR UI_FORMS When using the define B/B via UI the end layer dropdown arrow is partially covered0 u. ^ T1 {) z! C
1249063 CONCEPT_HDL CONSTRAINT_MGR CM and SigXP doesn縯 respect PACK_IGNORE at components 6 z1 Q; c. b+ r3 m; B) A1250270 CONCEPT_HDL CORE Part Manager Update places wrong parts 1 X) \: x) ?4 W+ z# T' d1251206 ALLEGRO_EDITOR ARTWORK Aperture command cannot create appropriate aperture automatically from design.5 y+ {1 ^) @% Z$ e' g- ?5 A7 c
1251356 ALLEGRO_EDITOR INTERFACES Some STEP models are missing in 3D view of footprint, although all components have STEP model mapped in footprint0 f% u/ V# n' Q# `& j5 K
1251845 ALLEGRO_EDITOR EXTRACT Crosshatch arcs do not extract correctly( W% P G" x) u {9 T) W0 Z
1252143 APD OTHER When using the beta "shape to cline" command the tool is removing the shape instead of converting it. + G/ A7 m* R# i0 N0 b1252737 SIP_LAYOUT OTHER SiP Layout - Option to create shapes from Pins for WLP wafer level packaging technologies ) m ^5 p. u( {0 |4 q- j" x. v* Q+ Y/ F1253424 SCM SCHGEN Export Schematics Crashes System Architect8 N5 ~7 k; L) v
1253508 ALLEGRO_EDITOR INTERFACES Bug - Export IPC2581 exports Crosshatch shapes as filled : g" X: {% h3 i- I9 W9 q/ D1253554 SIP_LAYOUT OTHER SiP Layout - Add Netlist Spreadsheet export to SiP layout to help with connectivity auditing 3 f8 T1 v) f% _5 `# }( h3 V1254578 SPIF OTHER Specctra crash with Error -1073741819 for Auto router2 I& Z# Y/ X4 P8 r- A
1254637 ALLEGRO_EDITOR DRC_TIMING_CHK adding nets to a net group causes constraint assignment error ) |1 i& q+ G& C7 R3 |- T1254676 GRE IFP_INTERACTIVE Rake Lines disappear when Auto-Interactive Breakout is enabled. 2 l5 Y$ c; e* d. { [) b9 |( [1255067 SIG_INTEGRITY REPORTS Allegro hangs on Net Parasitc Report generation' J9 w! z: n2 D4 I, B
1255267 ALLEGRO_EDITOR SKILL axlDBGetPropDictEntry does not return a list of all objects + y4 A0 K% G# {- ^7 n1255383 SIP_LAYOUT IC_IO_EDITING cant move bumps or driver in app mode , x* _$ s3 T p9 @1255703 ALLEGRO_EDITOR SKILL axlCNSSetPhysical and axlCNSGetPhysical return nil if a constraint set name is provided 4 [# ^- C3 i, I4 V" I ?. ~1 [2 X1255759 ALLEGRO_EDITOR INTERFACES Change the silkscreen OUTLINE from layerFunction DOCUMENT to layerFunction BOARD_OUTLINE6 ~6 q% s. F2 G G. O2 s; ^& ?
1256457 CONCEPT_HDL CONSTRAINT_MGR Extracting a XNet from CM crashes the tool9 |& a! i3 P) o
1256597 GRE CORE Allegro GRE crashes while running Plan Spatial, on a particular design7 e$ C# O" U/ |
1256650 ASI_PI GUI PFE - Cannot generate model file error when using company decap library 3 c8 V# |0 C1 [- V* [7 {1256837 SIP_LAYOUT DIE_EDITOR Open and close of die editor takes too long4 E! a2 {% q. k! a" J7 n# J7 j( q. c9 X
1257732 CONSTRAINT_MGR OTHER Bug - Export Analysis Results in CM makes Allegro crash $ a4 T: A0 S) f1257755 ALLEGRO_EDITOR OTHER Editing time in Display > Status seems to be logging wrong time 3 C7 h; ]* }7 u, j; H1258029 APD WIREBOND The bondwire lost after import the wire information % _) \( v" Y' Q$ j4 R; C1258979 APD NC NC Drill: There is difference of number of drills. 9 Y; v' q8 P% L7 p1259484 SIP_LAYOUT OTHER SiP - calc min airgap calculate minimum airgap beta feature improvement $ C1 y8 t& A7 v# T8 {7 e( W1259677 CONCEPT_HDL CORE hier_write -forcereset cause component prop change.* V' f- b, I/ E8 M
1259913 ALLEGRO_EDITOR UI_FORMS Unable to save setting of "use secondary step models in 3D viewer"4 E8 [! \! K {1 r
1261758 ALLEGRO_EDITOR EDIT_ETCH Auto Interactive Delay tune (AiDT) is deleting clines7 G7 Z0 N3 _8 g7 {
1262543 ALLEGRO_EDITOR MANUFACT merge shape results in moved void & Q; Q5 k) O0 x1 y- l" R4 @1264767 ALLEGRO_EDITOR DRC_TIMING_CHK XNET is choosing to resolve to a different name from 16.5 to 16.6 and is causing constraint loss7 t0 ]' x# u x p
/ Z+ F4 Y$ Q0 l2 q+ |
DATE: 03-28-2014 HOTFIX VERSION: 026 7 d' Q; f3 u, @9 [=================================================================================================================================== ( z5 y" \! f2 |# Y: v: nCCRID PRODUCT PRODUCTLEVEL2 TITLE) q; J. x e3 g% H8 b
=================================================================================================================================== 3 X5 R: |" ]5 p6 `# K1190942 CONCEPT_HDL CORE Cannot copy locked .xcon files: V# u% g/ p, o+ r [
1226085 F2B PACKAGERXL Winning net NC shorted with loosing net due to PACK_SHORT6 F# K* \, q1 y! I
1244894 SCM SYSTEM_OBJECT Get packaging error when adding a pullup/pulldown resistor, b9 l7 x9 N5 G( `1 M( u
1247432 CONSTRAINT_MGR OTHER PCB Editor crash5 I! F' G& \7 l) g$ G& p) f6 K9 f; k
1248560 F2B DESIGNVARI Variant Editor > Help about for S024 says unreleased ? $ H, Q% V* c; ?5 i1248712 SIP_LAYOUT WIREBOND Changing the charecteristics of a Bond Finger causes it to shift position ! H! k, i! O+ |. O* C/ ^. A1248839 ALLEGRO_EDITOR OTHER 16.6 S023/024 crashes on Logic Change Parts command.- L) c# H( e2 O
1249000 SIP_LAYOUT DIE_EDITOR unexpected shift of instances/pins by co-design die editor1 V& {) G" _4 L8 T
1249186 ALLEGRO_EDITOR INTERFACES Bug - Export IPC2581 ignores property UNUSED_PADS_IGNORE " X5 I3 X w1 f* k8 p" Q1249272 SIP_LAYOUT IMPORT_DATA film resistor pins/pads are created on the wrong layer. Always synthesized on top cond layer regardless of config file 9 e2 I+ @$ |3 _7 D% H$ x M7 F1249792 ALLEGRO_EDITOR INTERACTIV Cannot place rectangular shape as per included width and height. E; F/ a) r% M2 I1249801 ALLEGRO_EDITOR INTERFACES Bug - Arcs in IPC2581 export are corrupted0 ]; J o8 B0 l
1251006 ALLEGRO_EDITOR INTERFACES IDX does not recognize PKG_PIN_ONE property# n4 X) l! @9 o( t- u: s2 V
1252142 ALLEGRO_EDITOR INTERFACES Remove inappropriate Conductivity specs from the dielectric layers from the IPC-2581 output2 ]+ c3 i+ n- L/ K& I6 ?
1253047 ALLEGRO_EDITOR SCRIPTS Bug: SAV file when creating symbol# q1 |7 h. [0 f7 D
5 U, i ?$ Y0 ^5 ^" tDATE: 03-13-2014 HOTFIX VERSION: 025 % \" M4 f5 |, N4 A4 z/ m=================================================================================================================================== ) b4 ^- g; a8 q: @( bCCRID PRODUCT PRODUCTLEVEL2 TITLE! J; D4 @( T/ C& m
=================================================================================================================================== + N) B8 p. z7 b: p7 m# d1194646 CONCEPT_HDL GLOBALCHANGE Global Update > Global Component Change does not work* V7 K& i, u, U8 |
1227843 SIG_EXPLORER EXTRACTTOP Cannot extract the topology correctly. j2 H8 @% }$ S( w4 ^
1231510 ALLEGRO_EDITOR INTERFACES IDX exchanges with CREO 5.0 issues* d/ W" p) L* t1 W& \
1233030 SIG_INTEGRITY GEOMETRY_EXTRACT Net Parasitic of ground Connection6 Y' ?! q; E" W# i5 {& P, `1 X$ e4 H
1236961 SIP_LAYOUT OTHER Moving component using Place Manual -H causes mirror_geometry. , |1 R% E; f9 l Z3 [6 e1241456 ALLEGRO_EDITOR EDIT_ETCH When creating Die pins or changing their attributes an oval is placed on the pin. e. D7 }" ]/ B2 j- S5 o* c# y
1242461 SIP_LAYOUT OTHER SiP Layout - DIE is being mirrored when placing2 m8 q) L1 N& N& o
1242682 CONCEPT_HDL PDF PDF Pubisher crash DEHDL on design / l1 J. C$ t0 I1242685 SIG_INTEGRITY SIGNOISE Incorrect net name was displayed/output if the net include consecutive underscore. & T& U8 G. }' {2 c3 l( m8 T; s1243357 ALLEGRO_EDITOR INTERFACES Ability to add any new name , I1 \, {) A8 Q* U" X1243758 ADW COMPONENT_BROWSE I don't see an option to switch between database and cache mode 5 ]1 A8 l9 T8 c" v# k1244325 ALLEGRO_EDITOR INTERFACES Merge all the BOMItems with same part number into one single entry in IPC2581B.1 A- H# Z- B! U2 L! w" s' N( k
1245363 CONCEPT_HDL CORE Design Entry HDL program crashes upon save+ F/ o; g& g* _) @2 h! g: S: M6 D/ F
1245790 ALLEGRO_EDITOR PADS_IN Bug: PADS Translation with 16.6s023 gives parse error ' q' [% r8 t: u# @: i1246343 ALLEGRO_EDITOR SKILL axlAirGap command is broken in s022) x8 X# Y8 G% S
1246419 CONSTRAINT_MGR OTHER Netrev fails with SPMHGE-268 on existing design 2 C0 m" [% x+ a2 c2 o- r1246878 CONCEPT_HDL CORE Changing Symbol in Variant Editor makes schematic page crash - Z7 r( s- T9 Q1 `0 w8 W8 U1246884 ALLEGRO_EDITOR GRAPHICS Infinite cursor disappears from the canvas after step package mapping GUI is closed. 1 t: W# Q8 [$ O2 {+ F# k1247016 ALLEGRO_EDITOR INTERFACES STEP Model of connector cannot be zoomed sufficiently after mapping it to symbol dra file.: A, ~$ R; M6 p# ]( \7 x- w
1247107 ALLEGRO_EDITOR INTERFACES Incorrect Spelling in IPC-2581 EntryFillDesc field8 f- U5 k1 V$ Z w4 E
1247177 SIP_LAYOUT WIREBOND Bondfingers not aligning to wire when tack point on the other wire end is moved from center ' E' O2 Q7 K( G; w1247400 ALLEGRO_EDITOR INTERFACES option to Export optimized PDF in color / [* d. w1 p1 l k! h5 ~ ) b" C- C! t: l. M0 kDATE: 02-28-2014 HOTFIX VERSION: 024 _) V5 Y0 [& @3 ~0 K=================================================================================================================================== ( }5 \1 `# O r$ W" F" lCCRID PRODUCT PRODUCTLEVEL2 TITLE 5 C/ q% n, @1 g, ]6 [===================================================================================================================================8 G8 x! K, m' G3 ~) l8 T* Q t6 [3 s7 u
1207753 CONCEPT_HDL OTHER The Variant Name with a dash is represented by #2d. p& u& p5 w E& G; h8 e5 v/ X' R
1234991 ADW TDA Team Design does not remove deleted page files from zip files2 L$ ^* B3 @: ?5 }& C P/ V
1235919 CONCEPT_HDL PDF DNI crosses are not printed on the correct components z: D2 Y2 r( Z4 i
1238007 ALLEGRO_EDITOR PARTITION Import partition removes properties from RKO that were on the exported partition , Q' p' ^" p" i- Y* W1238140 CONCEPT_HDL CORE Design Entry HDL Crashing' D$ E( z; I2 M* \
1238195 ALLEGRO_EDITOR DATABASE Via's losing net idenity after being mofifed or replaced.+ V B' R# ~" |, h) V
1238478 ALLEGRO_EDITOR ARTWORK IPC-2581 negative artwork layers does not recognize shape bounding box value5 c+ V9 U1 q" {# d& t" {- e c3 m5 O
1238483 ALLEGRO_EDITOR ARTWORK IPC-2581 not drawing negative artwork correctly with traces in voids.. ?8 r+ l5 k" v% F6 M7 I" D0 {
1239070 SIP_LAYOUT WIREBOND When importing wirebond data onto a Die rotated 90 degrees the WB data is placed in the wrong locations ; @: X) h( a" b: p) Z3 J/ D Q: h9 N1239433 SIP_LAYOUT WIREBOND Need the Wirebonds to lock to the die aftter importing wirebond data( u% C- p4 K2 W
1239952 ALLEGRO_EDITOR SYMBOL Allegro crashes with a component rotation of 45 or 135. 2 I, G6 c& ]& o3 J2 P5 @1240205 SIP_LAYOUT DIE_EDITOR Crash occurs when trying to "oops" for a moved driver in co-design die editor in SiP+ E& b* D9 R; E/ c5 ]* O& g; a$ `
1240288 ALLEGRO_EDITOR INTERFACES Why are some of the mechanical holes not showing up in Step output of thi design, while others are ? $ d& ~3 Z( V7 F7 f# v6 J- U8 X1240305 ALLEGRO_EDITOR INTERFACES STEP Export gives some errors which are not documented ) s) ~ ? i I' Z* Q& G; v1240425 ALLEGRO_EDITOR DATABASE Export ODB is not working on 16.6 HF 22 " V/ u5 n6 u* N1 w! O7 Q' T1240879 ALLEGRO_EDITOR NC NC ROUTE file is not correct using hot fix 22 of v1664 X# i5 Q3 D4 f6 }4 b% r3 D8 c E
1241904 ALLEGRO_EDITOR INTERFACES IDX baseline import displays false DRC with Package_height Offset until DRC update is run. 7 k2 D! k: D s3 ]( O$ d$ p1242266 ALLEGRO_EDITOR INTERFACES IPC2581 crash on HF22 and HF23" A; q1 _ u; V
1242433 ALLEGRO_EDITOR INTERFACES ipc-2581B incorrect LayerRef values in BOTTOM side RefDes elements + f7 }6 f8 [, X. u0 A) _: Q4 i/ c1242988 ALLEGRO_EDITOR SKILL Allegro crashes on skill command axlDesignFlip ' v5 ^7 O! p* q1243845 FSP FPGA_SUPPORT FSP design created in 16.6 s018 will not open in 16.6 s021 j) Y3 o/ T. L6 Q( i2 ~( ]6 k. `
t! E0 F _6 E' C+ {DATE: 02-14-2014 HOTFIX VERSION: 023/ V. c! \5 p0 ^7 Q3 C7 c5 z
===================================================================================================================================2 y" ?9 y% N5 S ]8 E" U
CCRID PRODUCT PRODUCTLEVEL2 TITLE' A8 t3 a& I- }" ~7 A! X1 m
=================================================================================================================================== ) y3 e% U7 P2 S- h4 j3 m1120183 F2B DESIGNVARI Variant Editor Filter returns incorrect results. . z: F/ P- V- |5 X5 _5 N' [# r1202715 SPIF OTHER Objects loose module group attribute after Specctra+ a5 q/ G8 e, Y& m
1203443 ADW LRM LRM takes a long time to launch for the first time - }/ X. O- g+ L: K1 Y, W* ]% Q1207204 CONCEPT_HDL CORE schematic tool crashed during save all" y9 C4 w1 R. X$ [. E1 }$ [# a
1222101 CONCEPT_HDL CORE Pins are shorted on a block by the Block's title delimiter; z7 t" C! p) q1 _) a, @9 u
1223709 FSP FPGA_SUPPORT Need FSP model of Altera 5AGZME3E3H29C4 FPGA ]& P, k* k; X- B( m1224025 ALLEGRO_EDITOR INTERFACES The 3D viewer when working on a brd file shows package placed on BOTTOM side of my board while it is present on TOP side 5 ?& W; q) R) F s2 {& U0 z: {1225591 F2B PACKAGERXL Aliased net signals starting with equals sign are not resolved correctly in cmgr / O# |$ ^+ U/ Q: P1226480 ALLEGRO_EDITOR EDIT_ETCH Routing time is took to double increase when using the Add Connect because DRC is Allowed. 1 P# E* B8 `" X( S) [; q2 s1229234 FLOWS PROJMGR Can't open the part table file from Project Setup, K% d7 @5 @2 y" G* n4 ]: d
1229555 ALLEGRO_EDITOR ARTWORK IPC-2581 not recognizing pin offsets correctly. : U" G/ I+ g/ k0 x; I0 t. r, a+ B1229610 FSP FPGA_SUPPORT New FPGA device request - Altera Cyclone V ST: 5CSTFD6D5F31I7& p K: S% F, n: j
1229664 ALLEGRO_EDITOR SHAPE Shape not voiding different net pins causing shorts with no DRC's2 A3 M: O4 u9 J- w: n4 j2 H/ L0 U
1232601 ALLEGRO_EDITOR MANUFACT Cannot add test point to via on trace. 0 g5 ~$ a' u6 h/ v$ L1232772 ALLEGRO_EDITOR DATABASE When applying a place replicate module Allegro crashes : L3 H5 ~2 c+ w' T+ M1233216 SIP_LAYOUT DIE_ABSTRACT_IF Allow more than 2 decimal places for the shrink facor in the add codesign form% ?1 q1 ?- u, ?3 _, v0 C
1233690 PDN_ANALYSIS PCB_STATICIRDROP PDN IRDrop: Mesh mode in Report is incorrect. ; M4 Y8 ~+ y- b* S: U) j1233977 ALLEGRO_EDITOR INTERFACES single shape copied and rotated fails to create when importing IDX/ Q5 K$ v" l, W$ i, k' | \) D
1234357 SIP_LAYOUT SCHEMATIC_FTB DSMAIN-335: Dia file(s) error has occurred.- ]! X6 ]/ i+ m2 C0 ~! f: v
1234450 ALLEGRO_EDITOR INTERFACES clines, pads, etch shapes to be at the same level with the board when viewed in STEP viewer.( e) l3 ~+ A: p9 h: {
1235587 PSPICE MODELEDITOR PSpice Model Import Wizard does not display symbol graphics for DE-HDL Symbol: U! t6 x0 b+ F2 L* s
1236571 ALLEGRO_EDITOR GRAPHICS Allegro display lock up and panning issues 6 B- ?3 ~4 q& m* }( U) \8 I: e* H1237415 ALLEGRO_EDITOR INTERFACES Multidrill pad is exported with single Drill in the STEP File ; V1 V4 b" X3 I( ?# H1237807 ALLEGRO_EDITOR SCHEM_FTB The line feed code of netview.dat& s _: l, Y% }8 t8 h0 P
8 L+ j. x3 o U. zDATE: 02-7-2014 HOTFIX VERSION: 022 ( X F& W) x- ?1 n M% G===================================================================================================================================2 Q+ k# }/ a( u) L8 M/ D
CCRID PRODUCT PRODUCTLEVEL2 TITLE3 d) i1 D/ T# F1 F
=================================================================================================================================== - ^1 N) n6 Y+ W- g192358 ALLEGRO_EDITOR PADS_IN Pad_in does not translate some copper shapes( O C& V( I! f# O7 u2 P: o5 G
222141 ALLEGRO_EDITOR PADS_IN PADS_IN: Extra shapes are created when importing PADS design. E4 S2 V" g. [8 ?$ l( x N
274314 ALLEGRO_EDITOR PADS_IN PAD_in boundary defined for flooded area be translated DYN ! E/ a% J! n4 B7 ~! S) Z9 H413919 ALLEGRO_EDITOR PADS_IN pads_in cannot import width of refdes.. m! h- q9 v0 C
609053 ALLEGRO_EDITOR PADS_IN "Mils to oversize" of "pads in" did not work correctly for MM data.. |7 K% f2 B+ C$ ~5 A, u
666214 CONCEPT_HDL OTHER Option to increase Line thickness in publishpdf utility. V& r. T9 x3 M1 x
738482 ALLEGRO_EDITOR GRAPHICS Export image creates black image with Nvidia GeForce 8400M GS Graphics card; A! Y' z& c2 T% u9 b
982950 CONCEPT_HDL OTHER change the mouse button for the stroke to have same function with in pcb editor% |5 o- y' W4 B
1020886 SIP_LAYOUT LEFDEF_IF a quicker way to promote die pins (by importing macro_pin list) 3 u1 H% [" U4 I( Y! x7 m1032678 CIS VIEW_DATABASE_PA View Database Part gives incorrect result in complex design with variants. T( ]- T1 `$ `9 c6 H$ B$ ?
1033864 ALLEGRO_EDITOR PADS_IN pads_in doesnot translates teardrops present in design1 _& I# L$ y) Y/ q# q
1054862 CONCEPT_HDL OTHER Option to increase Line thickness in publishpdf utility5 c' M) H3 i8 Q, X0 E
1055252 FSP PROCESS Add a synthesis option to target a group to contiguous or consecutive banks2 V( R8 Q; Y! R7 l3 E( m
1100772 CONSTRAINT_MGR OTHER In Constraint Manager > DRC > Spacing the Show Element DRC totals are wrong.. [3 a/ O& d7 V+ J/ ?$ F7 e
1135020 CIS DESIGN_VARIANT Variant list is showing wrong results for hierarchical designs 3 ?4 z* x9 k% H4 T1138951 SIP_LAYOUT DIE_ABSTRACT_IF Fix die abstract r/w to properly support pinnumbers on ports! G# U I( {6 _. `- v1 G
1140042 CONSTRAINT_MGR OTHER Diff_Pair lengths and analysis are lost after closing and opening Constraint Manager.1 \! y/ J1 ^! E7 |: N6 i0 ?6 J; M9 i7 K
1143662 ALLEGRO_EDITOR INTERACTIV Enhancement Request for RMB - Snap Pick to options increased to include Pin edge : }3 \& v3 P& |9 i! k" N+ y1147961 PSPICE SIMULATOR Simulation produces no output data & }, c( c1 p( E0 Y1150874 ALLEGRO_EDITOR PADS_IN Dimensions in PADS are not translated correctly during pads_in translation 7 G J+ L2 C! ?, n1154184 CONSTRAINT_MGR CONCEPT_HDL Difference in the way topology is extracted in 16.3 versus 16.6 7 g9 s$ V2 z, p+ D6 e1154770 CAPTURE PROPERTY_EDITOR Variant Name property doesn't show value in Variant View mode 1 Y q: w, g5 N8 a2 r: r/ g0 _& G1158350 CONCEPT_HDL CORE Need a warning Message while importing a 16.3 sub-design in a 16.6 Design8 g) L9 P. V9 W9 m: e
1162347 ALLEGRO_EDITOR EDIT_ETCH Enh- Allow new option in Move command such that it allows stretching etch using only 45/90 degree segments directly% {# |1 l/ y0 N. c% u. Y
1165553 ALLEGRO_EDITOR INTERACTIV Subclass list invoked from the status window does not represent correct colors.& ]; ?& S9 A* w; F3 u- o0 I. U
1168079 FSP MODEL_EDITOR Clicking OK or Save As in rules editor allows user to overwrite the master with no warning O" |. H+ z! U; K# b, ^8 ?1172043 SCM OTHER : in pin name causes SCM to crash 9 t2 d; |' r" p) B4 `) x) v7 z1172207 CAPTURE STABILITY Capture crash while adding new part from Spreadsheet, j' g: D8 K9 C6 v
1172743 ADW TDA Allowed character set for the check-in comments is too limited* C0 S" P, ]( k K; ^% N1 B! Y
1174099 SIP_LAYOUT WIREBOND Option to reconnect wire based on 縫in name� in the Wire Bond Replace ( C! J0 g6 H6 d$ o7 X+ A) H/ N1177672 APD IMPORT_DATA Netlist-in wizard didn縯 provide detail information about what columns have been ignored by import process ; E2 G& Y: E- R; N8 J( d* d1177714 CONCEPT_HDL RF_LAYOUT_DRIVEN RF component's LOCATION property can not be set to invisible+ K9 L( m8 M7 ^7 ^6 s" X
1177820 CONSTRAINT_MGR INTERACTIV Done the Allegro command when attempting to launch CM & ~' [8 e/ p* d5 X( \& V' ?' B4 n1178586 ALLEGRO_EDITOR EDIT_SHAPE Number of digits displayed after the decimal point of Shape Creation function does not match the Accuracy of BRD. p. Q9 p3 C$ r5 H
1179688 PSPICE STABILITY pspice crash for particular HOME variable vlaue ) @- d/ _: Z2 X8 i# ~' w4 U C1179827 SIP_LAYOUT OTHER SiP Layout - Spreadsheet to Symbol export - enable field to add Keywords for data fields to excell cells: S: [- u" z1 O+ K/ y
1179879 SIP_LAYOUT STREAM_IF Data file corrupt when exporting Stream data from SiP database.1 L, {: ^* J7 Q m. B0 o
1180164 F2B BOM BOM csv data format converts to excel formats, d# h% y5 a. V* M6 j
1180477 ALLEGRO_EDITOR INTERFACES IPC-356 output is listing a duplicate location in the comment section 0 N& L# j" v' ?- G" \1180932 SIP_LAYOUT OTHER SiP Layout - Symbol to Spreadsheet add option for writing to existing spreadsheet: z7 v' H5 x \, G9 V, t$ T; _1 y
1181377 ALLEGRO_EDITOR INTERACTIV Pick Releative does not work correctly with RMB-Move Vertex 6 O9 C: P/ Z8 m0 L* s2 o# D% i1181516 ALLEGRO_EDITOR DRC_CONSTR Getting a "Thru Pin to Route Keepout Spacing" when there should not be one. $ F" T! K0 c/ v* l0 d4 H1181739 GRE CORE Running Plan > Spatial crashes GRE 6 d0 A( z( i1 M4 A1181935 ALLEGRO_EDITOR DATABASE Enh. Property that allows internal C-C DRC errors & h0 k- d0 N* P4 X; ]1182185 SIP_LAYOUT OTHER SiP Layout - Import symbol spreadsheet - suppress Family for the font in the XML spreadsheet5 G6 a; w# X+ m( n
1182566 SIP_LAYOUT OTHER SiP Layout - Spreadsheet to symbol - Enhance ability of spreadsheet exchange to allow for a portion of a full pin map* S; y$ A5 o. D; K0 X
1182599 CONSTRAINT_MGR DATABASE CM Prop Delay Actuals do not update after Z Axis option is turned ON or OFF and Analyze is run./ n& r) u. H/ c0 a
1182892 CAPTURE SCHEMATIC_EDITOR Pspice marker rotation before placement u/ N7 l" ~1 y' ]1183682 ALLEGRO_EDITOR DRC_CONSTR Implement Nodrc_Sym_Pin_Soldermask & Nodrc_Sym_Pin_Pastemask to symbol level ; f6 }2 F2 K& |" t4 L. h1185445 SIP_LAYOUT DIE_ABSTRACT_IF Die abstract export needs to be able to select xda file type when browsing # K+ K0 t+ A \, G1185932 ALLEGRO_EDITOR SHAPE Soldermask in solder mask void DRC3 U' A# Z p/ a
1185946 CONCEPT_HDL CORE Ericsson perfomance testing report 5 sept 2013 0 ]/ j; m' M7 l) D0 b3 |8 G$ r1187213 FLOWS PROJMGR Unable to lock the directive: backannotate_forward : B/ W: y: N1 z7 z+ |' s1187444 ALLEGRO_EDITOR DRC_CONSTR With this design Database check prompts error "SPMHGE-47: Error in call to batch DRC" 5 I) r4 p. }# ?! G+ [1187597 ALLEGRO_EDITOR DRC_CONSTR No Package to Package Spacing DRC error, when symbol overlap sideways at 45 degree.* D# q) j$ E3 }
1187723 FSP PROCESS Synthesis can fail depending on component placement2 T' ~3 P; y- N: T5 z) D# f
1188164 SIP_LAYOUT OTHER SiP Layout - Spreadsheet interfaces Import Export and Add Component - include Keyword for NET_GROUP h: ]5 Z( q0 a5 U& C* n
1188245 CONCEPT_HDL CORE INFO(SPCOCN-2055): You cannot run the CHANGE command in a read only schematic 7 P1 l a/ j B" X5 v1190927 CONCEPT_HDL CORE Check sheet does not report shorted signal/power nets if power symbol is connected to a pin % i7 i* C; U; d2 d8 E0 l1191497 ALLEGRO_EDITOR INTERACTIV ENH: Adding names to the text block parameters numbers3 i% _! W! w' y
1192005 SIP_LAYOUT IMPORT_DATA Import SPD2 is missing 1 smart metal shape from file0 _6 f, B9 I) ~1 G- w i
1192204 ALLEGRO_EDITOR EXTRACT Need ability to extract vias that are labeled as microvia! U$ k6 O# D9 C+ U# `
1193063 ALLEGRO_EDITOR MANUFACT TestPrep log displays "Pin is not accessible from bottom". The component is through hole. 1 t4 m1 \7 _3 D5 b3 Z- X1193418 ALLEGRO_EDITOR GRAPHICS 3D Viewer can`t export image in both SPB166S015 and SPB165S047# n5 p: a% O$ n2 B; A
1194305 SIP_LAYOUT EXPORT_DATA export package overlay creates file with no package info) @' y' w2 f* t
1194418 APD IMPORT_DATA issue when do File->import->netlist-in wizard " I5 n4 w) h: j7 z( J: \1195279 F2B PACKAGERXL Ptf files are not being read when packaging with Cache ; n1 g$ F( [6 X& ~1 L$ }1195374 ALLEGRO_EDITOR INTERACTIV Modules are not showing up in Tools > Module reports ! H3 v5 ~4 }1 M4 a c2 b1196603 SIP_LAYOUT EXPORT_DATA Change form for "Write Package Overlay..." to better support longer lists of routing layers 0 m3 `- n5 E( q' _0 \ g1197302 CONSTRAINT_MGR UI_FORMS Inconsistancy in selection of object for Spacing Constraint Worksheet% C" e2 F- }1 L
1197399 CAPTURE OTHER Draw toolbar disappears when using Print Preview9 v4 L$ c! Y; K! l
1197543 ADW TDA TDO does not correctly show deleted pages % ]4 D. |1 k8 i( x1198033 CONCEPT_HDL CORE Signals do not get highlighted when Show Physical Net Name is option enabled( ]" u( L) T# g% c/ f9 S6 j/ C4 ]& z9 p
1198468 ALLEGRO_EDITOR GRAPHICS 3D_step model does not show the correct view in 3D_Viewer when symbols have multiple place_bounds.1 s9 f# B; |0 W3 U+ Y
1198617 CIS GEN_BOM Mech parts are showing with Part reference in CIS BOM" _! U+ P9 M. |' f% i6 E0 Z
1199764 ALLEGRO_EDITOR SHAPE Allegro crashes when trying to delete small island on POWER layer.$ Q1 N$ _$ g) g, W1 x+ `
1200232 ALLEGRO_EDITOR INTERACTIV Moving all items including board outline which is made of lines does not move the board outline in General Edit Mode.- T9 I4 j; ~ W/ q9 s+ h
1200748 ALLEGRO_EDITOR INTERACTIV Additional pin edge vertex object to snap pick t( o6 Y$ A" B' q# R6 @5 P1201056 ALLEGRO_EDITOR DATABASE Unsupported functionality strip design creates a .SAV file1 J1 \5 K3 ?: `
1201638 CIS PART_MANAGER Part retains previous linking inside the subgroup $ {6 \4 Q' z" O1201834 ALLEGRO_EDITOR PLOTTING Bug: Import Logo command changes resulting imported object ( X F! h* s& p1202406 SIP_LAYOUT OTHER enable the dynamic display of component pin names for co-design dies in Sip Layout! A" Z7 W% f1 Q" _) e
1202431 CONCEPT_HDL PDF The publishpdf -variant option should have a "no graphics" option3 F3 k$ c# L1 B
1202717 ALLEGRO_EDITOR DATABASE About Warning(SPMHA1-108):Illegal line segment ... end points. " q7 P9 r. f9 Z* a7 [, y/ H5 n6 {1203459 CONSTRAINT_MGR INTERACTIV Object Report has no mechanism to output information for a specific design. 0 ^* u, K9 v2 i1204544 F2B DESIGNVARI Variant Editor does not warn on save if no write permissions are on the file! D, a0 v$ t" q8 g# U: w- K
1205500 FSP CONSTRAINTS MAPP FSP FPGA port mapping VHDL syntax1 @! u! @% G" l' |, x
1205952 ALLEGRO_EDITOR GRAPHICS Step Model for Mechanical Part is visible in 3D viewer only when Etch Top Subclass is enabled) H- V& v* D1 z6 k" ?" T& s
1206103 SIP_LAYOUT IC_IO_EDITING add port name property to pins, and add Skill access I/O driver cell data5 A. F8 [* |( }
1206546 CAPTURE ANNOTATE User assigned refdes are resetting when 緼nnotation type� is set to 縇eft-Right� or 縏op-Bottom� 4 d* B ? X8 @' f5 y1206561 ALLEGRO_EDITOR GRAPHICS Not all mechanical symbols made with Step files are displayed in the 3D View ; ?9 b2 E: g, z& u6 n1207125 SIG_INTEGRITY ASSIGN_TOPOLOGY ECSet mapping wrong for 2 bit in a 4bit bus/ `9 G# s) A" j& ~ b8 U% E7 r
1207386 CAPTURE GENERATE_PART Altera pin file not generating the part properly1 E5 {/ `' J, ~ {4 l0 m. W
1207629 CAPTURE TCL_INTERFACE Bug: GetMACAddresses tcl command not working ) ]( T1 `* o; N/ |1207994 CAPTURE TCL_INTERFACE TCL pdf export in 16.6 fills DOT type pins with black color7 W% d/ d f- [( p) m" S
1208017 F2B DESIGNVARI sch name is not same when updating Schematic View while backannotating Variant 3 q0 o" g: l! F1209363 ALLEGRO_EDITOR INTERFACES When placing pins using the polar command the tool returns 4500.00 for 45 degrees.4 `: w1 f4 N: ?8 u }* a* `
1209769 CONCEPT_HDL CORE Top DCF gate information missing9 {5 R2 u( l; t- e; O+ y* X
1210194 CONCEPT_HDL CONSTRAINT_MGR HDL crashes with Edit Via List dialog box , y, [- G! k8 T, l. l6 t+ p1210442 CONCEPT_HDL INFRA Save design gives ERROR(SPCOCN-1995): Non synchronized constraint property found in schematic page : I0 Z% @. d- G# S- ~6 h$ x% e1210685 ASI_PI GUI User can't edit padstack in PowerDC-lite7 r6 ~& |& U/ c7 f# C. C6 `' F
1210744 SIG_INTEGRITY SIGWAVE SigWave: FFT Mode Display unit seems not to be correct 8 K% j7 r6 o$ }" f( ~2 ?& F4 [1210829 CAPTURE NETLIST_VERILOG Shorted port is missing from verilog file3 c, P. D2 _2 v- k$ V
1210850 CONCEPT_HDL CORE DE-HDL backannotation crashing after instantiating specific cell from Ericsson BPc Library * p Y4 P! F, |- U- [% a1211620 ADW COMPONENT_BROWSE Component Browser Performance 8 [ c$ S5 ]2 v/ [& e% {% z1212102 ALLEGRO_EDITOR INTERACTIV Shape edit boundary adds arc mirrored to the highlighted preview. ; m( ]% I5 r9 M% n( o7 ^% Z& u1213294 CONCEPT_HDL SECTION DE-HDL windows mode multiple section fails to section first contactor pin from column of individual pins5 L& K) Z8 o3 l
1213402 APD DATABASE The old "ix 0 0" fix is now causing the features to lose nets entirely. ) b$ e5 F2 P2 w6 h; z6 }0 O7 l1213694 ALLEGRO_EDITOR PARTITION Via connected to Dummy Net pin in Partition gets connected to shape on the board after importing partition4 B P# x( J: X2 y" W
1214247 CONSTRAINT_MGR UI_FORMS Selecting the "All" folder in Spacing Constraints in CM does not automatically select the first column for editing 9 T! }) t" h' f+ ~) r( |" v1214320 SIG_INTEGRITY SIGNOISE signoise command with -L and -k option ! z b* _% Y! C* z1214433 CONCEPT_HDL CORE Genview does not update sym_1 with ports added to the schematic" _7 B( j, V$ o: v/ f' z
1214909 ALLEGRO_EDITOR NC NC Drill Legend show extra rows for drills : Y, g5 A# Y& t5 M1214916 SIP_LAYOUT OTHER package design integrity check for via-pin alignment with fix enabled hangs 1 w; i" B6 ^* r5 w/ }6 B, N1215954 SIG_INTEGRITY SIMULATION Cycle.msm does not exist error when simulating extracted net " B0 @3 d0 o* P* j1216328 CAPTURE STABILITY Capture crash5 p% Z5 ?2 ~! p0 c9 L0 D" R$ z0 W
1216993 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro crash on SPB16.50.049; b' ]9 Y) v7 {3 B8 w9 O/ l
1217450 F2B BOM ERROR 233: Output file path does not exist 3 O* m$ O, E2 K" @1217612 ALLEGRO_EDITOR INTERACTIV Replace padstack will not replace padstacks that have multiple alphabetic characters in the pin name - AB21-AB370 w7 X* y/ G& T9 i' H/ I
1217823 ALLEGRO_EDITOR INTERACTIV Compose shape fails with SPMHIS-473 9 [" h8 c9 T- O) c2 X1217887 ALLEGRO_EDITOR INTERFACES An undo option to be made available in the STEP Package Mapping window 0 N2 y6 x& i7 U8 Y9 G" k1218665 ALLEGRO_EDITOR INTERFACES In step viewer, the bottom side parts are placed above the pcb board surface) C' B0 r- h' e5 o# j7 }
1219053 PSPICE PROBE PSpice crash with the attached Design1 y; s4 M( y# k, b/ Q% R
1219067 ALLEGRO_EDITOR EDIT_ETCH dynamic fillets behavior is unstable0 ?9 P: x7 P7 }! d& ]
1219095 ALLEGRO_EDITOR MANUFACT Design Cross section chart is tapered for two layer board / ?: R8 o! r1 D Z t; T' j; V1219126 ALLEGRO_EDITOR SKILL Skill issue with axlRefreshSymbol()+ [. _$ R8 H, d- I7 _$ ?& ]
1220701 ALLEGRO_EDITOR INTERACTIV View > Windows > Worldview (showhide view command) fails with command not found 9 } e7 W. p' A& h* ~2 g( T; \& N( V1221057 ALLEGRO_EDITOR REPORTS Units in Cross section report for spacing is not synced with the design% F- _0 B% n7 \
1221139 ALLEGRO_EDITOR EDIT_ETCH Delay tune is not tuning differential pair( H- j i, X2 c* Y* x2 E8 Q
1221157 SIP_LAYOUT IMPORT_DATA import spd2/na2 file is not importing data correctly into sip1 s; F5 J9 O+ p1 p
1221163 SIG_INTEGRITY GEOMETRY_EXTRACT Simulation aborts with severe convergence issue when coupled vias is enabled. ( y. E! k/ E( u( z7 f# i4 e1221416 ALLEGRO_EDITOR DATABASE strip design for function type; ~+ r1 m z2 G; t5 N. T! S# N
1221931 ALLEGRO_EDITOR DATABASE Fatal software error when embedding component: L% K# q9 r* I3 F8 N
1222105 CONCEPT_HDL CORE Moving Pins around the edge of a Block causes the text of the pin to change its text size.$ i8 o) g) d: s+ |
1222124 APD DATABASE Same Net DRC's exhibiting inconsistent behavior. & `8 o& a6 p. ^) _( c; }3 H1222272 SIG_EXPLORER EXTRACTTOP Cannot extract net or open SigXplorer after selecting a netgroup% x4 P1 a) X4 U p# U! I6 X+ G
1222329 ALLEGRO_EDITOR SHAPE STEP-Model Symbol which has place bound bottom is on Top& u) Q7 N8 I# C' F0 I, n4 H
1223183 SIP_LAYOUT BGA_GENERATOR Getting an incorrect error message when using the BGA generator with a long BGA name.+ }3 N) W. l! u% d$ A
1223662 ALLEGRO_EDITOR REFRESH Allegro crashes when trying to refresh symbol& j( Z4 a+ N* f; K' V% v
1223932 CONCEPT_HDL CORE DEHDL block desend does not find 1st page if its not page1 + }% B, s$ A% X( ?+ B1223940 CONSTRAINT_MGR UI_FORMS Unable to change CLOCK name in Setup/Hold Worksheet under Timing in CM.( n- Z& J+ }% \% \) a0 ~
1224127 SIG_INTEGRITY IRDROP Is the old static IRDrop in 16.6 officially supported?. i: x# K; Z9 ^. s+ \- c" s( D
1225492 PCB_LIBRARIAN CORE PDV expand vector pins resizes symbol outline to maximum height again. v* B2 t c b/ k2 s
1225546 CONSTRAINT_MGR ECS_APPLY nets where the referenced ECS maps correctly in constraints manager for front end but not in back end ; W: V& W% ~/ x" Q' i4 V4 f4 n" @# B1226405 ALLEGRO_EDITOR INTERFACES File > Export > IDF ask for filter config file eventhough it is created in same session and stored in parent folder/ Y4 Q9 I9 j0 p2 F0 q
1226448 PDN_ANALYSIS PCB_STATICIRDROP License failure about PDN Analysis with XL and GXL& v, Y$ y' ~! K( q, k7 k! H$ l5 f
1228721 SIP_LAYOUT OTHER File Export Netlist Spreadsheet enhance sort to be a natural method per Jedec according to customer : m, Q6 i+ k" R3 p0 P5 k, I # E& H1 F! ?5 @. _% A2 xDATE: 12-20-2013 HOTFIX VERSION: 021' p6 I2 `$ U5 G6 A7 z! y) G
=================================================================================================================================== Y9 y( @- Q* T# i/ K1 i
CCRID PRODUCT PRODUCTLEVEL2 TITLE ) u, F: R% a7 D8 X5 g=================================================================================================================================== / A: Y% J- ~! u' c, P1214932 ALLEGRO_EDITOR OTHER Allegro will crash when performing show dimension on linear dimensions.+ J d: }! G3 `
1215045 ALLEGRO_EDITOR SKILL Successive file open / ipc calls crashes Allegro 16.6 , ^+ c. K' z+ n# `; m1215115 ALLEGRO_EDITOR NC drawing name doesn't display in the ncdrill.log file8 ?% c q; c* g/ C/ G! k$ P
1216028 SIP_LAYOUT PLACEMENT Design will not update embedded component symbols. % F4 e/ l* d. {- U; }1218451 ALLEGRO_EDITOR DRC_CONSTR Route Keepout to Pin DRC created even after adding Void in RKO shape& k6 J& ^! ]3 c. q, U9 q. K
1218636 ALLEGRO_EDITOR SCHEM_FTB netin process will rotate embedded symbols 9 J# h5 m1 ?. Q u e1218706 CONSTRAINT_MGR CONCEPT_HDL NCC associations get deleted from FE CM: G6 \8 x \, f* i
6 m2 a" F& D" V# X/ P6 T
DATE: 12-4-2013 HOTFIX VERSION: 020 1 e$ P4 A! k8 ?5 I3 K===================================================================================================================================+ N7 }4 c; I6 K* s* ~, P
CCRID PRODUCT PRODUCTLEVEL2 TITLE # C& T5 s R) k! e) I0 h=================================================================================================================================== ! D& Q+ `* V7 }0 T( X( R4 z6 D# b1116426 F2B PACKAGERXL Packaging in 16.6 increased by 3 folds compared to 16.3& K5 {! p! D3 I. \" c( t6 [5 h
1190095 CONCEPT_HDL CORE In Windows mode select the part and click on version placed selected version +1. - d2 }* }* Q; u1 @* _1199410 CONSTRAINT_MGR CONCEPT_HDL Constraint Differences Report window hangs in 16.6-s016 4 K; i" }6 ?# B7 j1199425 CONSTRAINT_MGR CONCEPT_HDL Import Physical fails (the cmfeeback.exe has stopped working) in 16.6-s016 " `2 i/ M% @2 |0 W4 [1199700 PSPICE NETLISTER Netlist fails on addition of netgroup + M$ u, s8 n# `9 ~) l1200936 CONCEPT_HDL PDF publishpdf fails if UNC paths are provided from the command line1 s: _6 Q' d* B; g7 l2 J$ e5 O
1202391 CONSTRAINT_MGR OTHER Getting 'An Invalid argument was encountered' when generating Net Class-Class report in CM 2 r7 t( L/ s+ {8 D- H1202587 CONCEPT_HDL CREFER Crefer schematic reports cannot be deleted on Linux., c1 C6 v# \% T8 k( k* k
1203143 GRE CORE GRE crashes on running Plan > Spatial9 g( }; ^7 P. M& i7 O
1206019 ALLEGRO_EDITOR INTERACTIV Allegro needs to be restrated to read steppath with 16.6 S017 ' Q5 R. m) f5 w1 q1207050 ALLEGRO_EDITOR INTERACTIV Refresh Padstack fails on Warning3 L$ N3 K2 ^# p+ Z2 J( S- T
1207178 CONCEPT_HDL CORE Aqua color on wire does not matches icon color ! l# \/ u- e0 l1208152 F2B DESIGNASSC ERROR: Dictionary File: cmdict.l could not be found ^8 f0 z& ~9 O* D! J$ e: N
1208276 APD STREAM_IF Stream in fails to import what Allegro exported * m! R( y) j" R: d1208345 ALLEGRO_EDITOR SKILL Why axlChangeLayer not working for shapes on this attached skill file? : X+ n4 h5 Y9 V1208351 ALLEGRO_EDITOR SKILL axlFilmCreate do not define the IPC2581 domain correctly.) p0 E* K/ v; b. t! x1 `
1208467 PCB_LIBRARIAN VERIFICATION con2con mangles cell data after checking cell having syntax errors on part_table ; U$ O/ t6 j2 i5 o+ v1208579 SIG_INTEGRITY GEOMETRY_EXTRACT Incorrect traces are extracted when void area is less than anl_min_void_area setting1 V P( P& o) @; K
1209347 ALLEGRO_EDITOR PARTITION Import partition that has diametral dimensions will crash Allegro ( m2 D# {- \, p' k1209897 ALLEGRO_EDITOR PADS_IN Pads_in will not translate design. ( u! P! j( V: R1 n- O1209902 PCB_LIBRARIAN CORE PDV crashes reading part 0 `% P# C: U; j* l1210183 PSPICE SIMULATOR SimSrvr crash with ORPROBE-3211 RPC Server unavailable Message9 L5 \. n9 \. k! ~( {/ F
1210408 ALLEGRO_EDITOR EDIT_ETCH AiBT hangs when doing interactive breakout on bundles using latest hotfix.3 I* F$ @3 N) _/ R$ t. b% z! o
1210443 ALLEGRO_EDITOR INTERFACES Allegro Design Publisher does not create fully searchable PDF for some of the text that are present or certain layers7 n9 y$ | b/ q. H+ O0 ~( d
1210876 CONCEPT_HDL ARCHIVER Archiver wrongfully deletes directories. 1 E/ ]3 p H& C% J, J% Q1211839 CONSTRAINT_MGR DATABASE Topology can't be extracted correctly. ( w2 B" b9 q* |) ]; \% `1212709 ALLEGRO_EDITOR DATABASE No connect can`t be detected in SPB165S048 5 p/ k; i4 J2 L2 A1213752 CONSTRAINT_MGR OTHER "Show Constraint Difference Report" option at File > Import > Logic does not retain the last setting 3 a$ h+ a* q( y# X! y) A " \+ M7 e8 j- o3 g5 U! H, c2 L# jDATE: 11-15-2013 HOTFIX VERSION: 019 ) e1 X% A# l" l1 ]0 S===================================================================================================================================; ^) o5 z3 g- B7 {* f$ Q) _
CCRID PRODUCT PRODUCTLEVEL2 TITLE# Q5 |, c9 O! O7 a
===================================================================================================================================7 V& s+ W5 \+ S
1176155 CONCEPT_HDL CORE Graphics remnants with 16.6 QIR 3 ; ^$ J( q4 X' J1178272 CONCEPT_HDL OTHER Verilog netlist does not include split blocks correctly* p0 `7 Y; s# Y$ M) M
1190782 FSP FPGA_SUPPORT Support for Altera > 5SGXEA9N2F45 device. % p0 f5 V7 U% b8 Y( v1194140 ADW LRM SYNC_PROPERTIES is not resolving issues a based sync_properties settings - w2 `7 ?, v& y+ a5 b; c, E* G1195744 APD EDIT_ETCH Diff_Pair routing fails on certain Uvias in the pair./ q5 k/ z1 W7 x
1196704 ALLEGRO_EDITOR INTERFACES ENH: During ipc2581 export checkboxes corresponding to 縈iscellaneous Image Layers� should automatically get selected # R# a) R; i3 ~1198340 ALLEGRO_EDITOR OTHER Multiple -product option on the Allegro command line does not access the second -product5 u6 |+ z) s& d
1198596 ALLEGRO_EDITOR INTERFACES When copper thickness is increased for the outer layers, step Viewer does not show correct component position.3 x% \0 z1 j, i# {
1199673 PCB_LIBRARIAN OTHER Component Browser fails to load footrpints if they are set with UNC path 9 v1 G J% z# R6 o0 ~ |& }1199889 ALLEGRO_EDITOR DATABASE Allegro crashing with latest hotfix.+ {3 i" h+ f: |( D/ H8 L/ a
1200303 ALLEGRO_EDITOR GRAPHICS 3D Viewer does not update after changing STEP model mapping * \4 P( K4 q, j1200449 ALLEGRO_EDITOR REPORTS Allegro crashes when generating Net Loop Report.- s+ V* U& G! ]' M$ @0 |4 f; q
1200915 ALLEGRO_EDITOR DATABASE Reducing accuracy of this specific design crashes Allegro 4 q' d. t0 `6 r5 L" I6 p, w: B1201011 ADW COMPONENT_BROWSE Component Browser crashes in DB mode 2 p6 b7 w% N, d& t. D1201376 ALLEGRO_EDITOR INTERFACES Allegro hangs when trying to map a specific STEP model to a package drawing.8 `: Z* z' H7 Z5 S
1201897 SIP_LAYOUT IMPORT_DATA BGA Pin Colors not matching the Colors defined in the Symbol Spreadsheet after updating.; G o0 H5 h9 N' [9 K" l$ r1 T
1202709 ALLEGRO_EDITOR INTERFACES STEP File generated from Allegro is not overwritten when the variable "set ads_textrevs 6 h4 Z. V1 Q' _. r) f [1202820 ALLEGRO_EDITOR INTERFACES Different xml generation for same step model on S106 and S017) i7 s/ n0 ~0 A1 b- y
1202842 ALLEGRO_EDITOR INTERFACES Step model invisible for one pin dra in allegro 16.6 symbol editor ! l2 A8 ^3 O0 |% H* |! G1202983 ALLEGRO_EDITOR SHAPE Shape voiding creates DRC with Route Keepout1 K" w4 G) d: F1 b* O" `, L
1203125 ALLEGRO_EDITOR OTHER Exporting STEP file with External copper enabled does not show all copper when viewed with Solid Edge or Inventor : B1 N+ E! b7 `3 i1203236 ALLEGRO_EDITOR INTERFACES IPC2581 output with crosshatched shape is not correct 6 B$ j% o$ x" M+ }- w2 M1203995 CONCEPT_HDL CHECKPLUS CheckPlus rule, local_signal_no_offpage_body, getting an incorrect failure.; B: G& ^+ j" R; `; G [ W# f9 q, }
1204629 ALLEGRO_EDITOR SKILL axlUIDataBrowse crashes the editor or returns error" x, k$ c; N+ P0 ?0 ?* R' }
1204640 SIP_LAYOUT DIE_EDITOR Concurrent co-design update fails- ~3 L* `2 X8 m
1204881 SIP_LAYOUT BGA_GENERATOR Pin numbers are messed up after deleting a pin at a staggered bga l( _* V W: Q& _- r1 Y9 W6 d
1204885 CONCEPT_HDL CONSTRAINT_MGR Cant assign discrete models after the wrong model was removed. * K" {# n( q( _/ x" L1205374 ALLEGRO_EDITOR OTHER pdf out command creates incorrect drill Symbol Characters placement in pdf file when setting film mirrored.0 W+ V1 j& ?. b3 @- u1 v$ E1 [
1205729 SIP_LAYOUT DIE_EDITOR update of codesign db fails on exit from die editor F' S( J1 S4 Y% K9 ^8 r" b7 e8 j6 K" y
1205801 ALLEGRO_EDITOR OTHER Tool crash when do export IPF. 5 h7 \* A+ H# I# g" p* p$ ^' y8 [1205881 CONSTRAINT_MGR OTHER In CMGR , Objects > Create crashes Allegro * r' g+ h- ~& T% g; T: @ * g; Y: n f% d+ a$ n( K+ uDATE: 10-25-2013 HOTFIX VERSION: 018- F% G8 z# k- X6 ?+ i: ~
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CCRID PRODUCT PRODUCTLEVEL2 TITLE 8 K" g, \$ j( ]/ [& {=================================================================================================================================== 6 Z6 l1 F' @6 w* W" D% u' P( v! r" i1118303 CONCEPT_HDL CONSTRAINT_MGR can not prdefine default units in HDL ' @- X# B% y" m/ _! j1174901 ALLEGRO_EDITOR GRAPHICS Spurious odd lines are shown in shapes and text that are not part of the design with opengl # |1 }* a Z r5 B2 a1176990 CONCEPT_HDL OTHER DEHDL BOM tool doesn縯 see similar names. / y ]) t$ X/ V) g& \( Q1179665 GRE CORE Plan Topological Crashes after around 8 hours of routing.! E' l% W. O( R: L2 S. k5 B* S+ j
1188193 CONCEPT_HDL CHECKPLUS CheckPlus not recognizing PIN as a base object. $ k' U, L% h$ N1189100 SCM OTHER Replace part in SCM using ADW as library fails9 c% ^+ [- L1 m
1189507 SCM SCHGEN ERROR(SPCOCN-2009): Package error after second schgen run with Preserve mode.. J) X6 u" Q9 _ H# z& q0 m- R% F
1192391 CONSTRAINT_MGR CONCEPT_HDL Restore from definition deletes local objects in other blocks 2 I; H8 w- h4 G$ A1 W1194597 FSP OTHER Pin definition problem) j- V( I2 l9 F
1195202 SIP_LAYOUT LEFDEF_IF Cannot add .lef files in IC Library Manager. Getting warning message WARNING(SPMHLD-52) ! g% ~* o! I0 y |: ^* Y1195309 GRE CORE GRE crashing during Plan Spatial. 4 W% ^7 |* z8 B0 m0 ]8 c2 B- }, T1197262 ALLEGRO_EDITOR MANUFACT Angular Dimension created in symbol is placed w.r.t. board origin and angle is blank 1 U' C6 { {$ a: `1198521 CONCEPT_HDL OTHER Cadence DEHDL issue - Note for Hotfix_SPB16.60.016_wint_1of1 9 f& j+ ^/ u: o: r3 a# i& v8 c* Y1199219 ALLEGRO_EDITOR INTERFACES Question on STEP Model export which uses PLACE_BOUND layer for any symbols that do not have STEP model mapped3 y5 y4 H! p7 n! E, }! {. ^
1199235 ALLEGRO_EDITOR SCHEM_FTB capture's behavior is redundant while creating pcb editor netlist + E( X9 t9 {, T1199323 GRE IFP_INTERACTIVE Crash when importing logic * i; y$ L0 U2 f" C1199368 SIP_LAYOUT DIE_EDITOR Refresh of die abstract in die editor with this design takes over two hours0 t; V; F# M% W; ~% W& l
1199760 ALLEGRO_EDITOR DATABASE Allegr won't display Soldermask Top layer % X. M1 l l- N- R0 h% c" h ; m; q4 d6 E6 O8 z9 tDATE: 10-10-2013 HOTFIX VERSION: 017# h0 m. h$ q% O1 ` i
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CCRID PRODUCT PRODUCTLEVEL2 TITLE 7 a4 [7 I G8 |3 _=================================================================================================================================== . N( T$ k ^3 ?+ U0 Y735992 ADW LIB_FLOW Create Test Schematic does not use the correct package type : \; {' `5 e6 v9 l6 ]1121403 FSP PROCESS "Assign to Pin" not getting obeyed by Synthesis. 8 u" ^ ]" f0 ]5 K1141844 RF_PCB DISCRETE_LIBX_2A ADS Lib Translation Pin Soldermask/Pastemask missing. O7 }; F, B% m
1169269 ALLEGRO_EDITOR DRAFTING Dimension placed on package symbol moves to different place when it is placed on brd file. ( H7 W) \8 {4 h& o( a* {1170488 ALLEGRO_EDITOR MANUFACT Dimension text(on .psm) move to different position, when it is placed on .brd. 2 `# Q( G o( R+ R+ U1173345 CIS CRYSTAL_REPORTS Crystal Report - Display Parameter dialog for export option 0 c/ f, o3 s/ o( m; r$ _9 a1181759 SCM LVS SCM Crash when doing update all that executing import physical command. - E( z3 B1 f6 R5 ?- I) ?1182499 ALLEGRO_EDITOR OTHER Step export to include through hole padstacks (all pins and via) drill. / O; Z( C& W" @- o5 l! ~) y: ]' n1184682 CONCEPT_HDL CONSTRAINT_MGR Net Constraint not transferring to layout from schematic & K3 A0 O( y2 ^) m) {$ g* z, `% b1185524 F2B PACKAGERXL Enhancement User would like notification of pack_short in pxl.log ' r: Q9 h+ Q4 y( }1185902 ALLEGRO_EDITOR SHAPE Update shapes dont clear some diffpairs in HF15) p& z4 j6 P3 n) e2 E1 P) [& b
1186152 ADW LRM Part Status for Deleted Part in LRM is distinguished with other part status) t( R4 ?) x* K( }- A
1186387 ALLEGRO_EDITOR OTHER DXF cannot catch offset value in s047 hotfix.9 E, {: g! \7 x% i
1186805 ALLEGRO_EDITOR OTHER Exported STEP file missing multiple components placed on board & F/ e! i+ a+ {: F1 C1186818 ALLEGRO_EDITOR COLOR Custom color not retained during dehilight: {4 q& k* m9 S5 a
1187196 CONCEPT_HDL CORE TOC not populating (page 1). z2 f$ C& w' B/ {
1187667 F2B PACKAGERXL Existing hard LOCATION property in drawing was left unchanged ( f. {9 v0 s$ z. @# L4 \; F( a1188264 ALLEGRO_EDITOR MODULES Some fillets not regenerated in module created from a board file. 9 d5 R$ w" Z* J5 G% D4 c, i1190144 ALLEGRO_EDITOR OTHER Fillet shape is not genrated around cline 7 T7 u! o0 f$ s4 E5 u3 ~1190210 F2B BOM The bomhdl.exe fails - MFC Application has Stopped Working ( }. r d; v: }6 n1190618 ALLEGRO_EDITOR GRAPHICS Enhancement for Visible grid0 c/ I/ g& r$ T O$ h, y
1190813 ALLEGRO_EDITOR INTERFACES 3rd party netlist file in TEL format fails syntax check but imports successfully 6 e% y7 a* v2 r0 l4 E7 U7 J, h1190895 ALLEGRO_EDITOR EDIT_ETCH Route delay meter displays violation when sliding diff pair 5 u4 s7 \) V1 ~6 _1190908 F2B OTHER DE-HDL aborts if dummy net is being cross-probed from PCB Editor7 `# x- d+ t! z
1190990 CONCEPT_HDL CORE Mismatch in .csa and .csb files L- T' b0 h" f; R, k* w1191008 CONCEPT_HDL CORE Remove Binary File feature doesn't work / m! J1 t& |. H0 z/ g1191514 SCM PACKAGER Packaging error PKG-100 L9 I9 P3 k$ Y" S8 o( L4 q8 O
1191517 ALLEGRO_EDITOR DRAFTING Metric +tolerance when using dual dimensions is not displayed correctly$ E& @$ U5 x* S2 |7 X7 m/ q
1192561 ALLEGRO_EDITOR GRAPHICS Padstack with offset is not showing correctly in the 3D Viewer. " _5 P4 {" R2 M1192916 ALLEGRO_EDITOR EDIT_ETCH Wrong static phase values are shown in the dynamic timing meter for certain Diff pairs compared to CM.7 O3 X& N0 {7 J0 o/ p
1194197 ALLEGRO_EDITOR OTHER Step export to include through hole padstacks. ! [- y2 d9 ]3 L7 }1194239 PSPICE DEHDL Associate Model does not launch from DE-HDL9 }0 s! B, Z, Z
1194736 PSPICE SIMULATOR Design causes RPC failure when run consectively6 P% W5 h* O. G2 o; z5 \1 Y+ a- _
1195139 ALLEGRO_EDITOR PLACEMENT Components disappears from board file once they moved ( ?2 O M* [8 M4 O) a4 A1 h2 [/ k* [. A
DATE: 09-27-2013 HOTFIX VERSION: 016! Z3 ?6 |6 R+ [
=================================================================================================================================== ! T: I) ]3 e' x- N; X1 M9 z6 [CCRID PRODUCT PRODUCTLEVEL2 TITLE9 q' N3 o2 a/ b9 c' i8 }
=================================================================================================================================== 4 @6 N! ~5 ?6 {0 F) x548538 CAPTURE NETLIST_ALLEGRO Enhancement:Include mechanical parts in Allegro netlist; m9 P! X* F$ P: N. k3 a8 W
1076579 CAPTURE GENERAL Display value only if value exists + R1 }- v" v; L# }* u* @$ |1083904 FSP GUI Need Filter in Change FPGA dialog to select desire FPGA from the long list.5 B: j5 B: l2 w1 [2 f
1089313 ALLEGRO_EDITOR INTERFACES Allegro Export PDF requires similar setup options as DE-HDL Export PDF for layer visibility , e) }5 n4 k1 D$ Z l! X- b) Z4 P1095728 ALLEGRO_EDITOR EDIT_ETCH Slide to grab adjacent elements when extend selection is enabled # J- q! ~, r: p/ Y$ f% r1102698 SIG_INTEGRITY ASSIGN_TOPOLOGY ECset will map on single ended nets but fails when the two nets are define as a diff pair. & n" F! B3 M; b1 h9 Z v1104071 SIG_INTEGRITY REPORTS Shape Parasitic value changes for bottom shape for changes in top shape( l( h. i. L5 X8 p' c5 _' f W: z* R2 p
1117731 FSP POWER_MAPPING Ability to sort in Power Regulator forms2 L! t# \/ R# Z. D1 i+ u
1121539 FSP CONFIG_SETTINGS Cannot configure special FPGA pins (temperature diodes). W& T# J+ i' A' K4 W! Q
1122721 FSP MODEL_EDITOR Partial copy-paste overwrites the complete cell in XML Editor) K, o4 ]. g g$ z. M# D
1123238 FSP TERMINATIONS Report functionality for terminations defined in the complete design. & o- |1 [/ h6 m1123364 FSP GUI Clicking on column header should sort the column.7 O/ v( P! R7 j( K3 _) R4 n/ w
1123403 FSP EXTERNAL_PORTS Improper checkbox selection for 緿o Not Connect� or 縀xternal Port� column* F. G: T: d5 Z9 x: ~: O
1125611 CONCEPT_HDL OTHER display unconnected pin in schematic pdf.; R, B# z, s/ t4 I5 I
1129871 ALLEGRO_EDITOR INTERACTIV Wire Profile Editor can't read mcmmat.dat in working directory. ) r4 O7 ~7 i* h# l; E1133688 ALLEGRO_EDITOR GRAPHICS Enhancement request to enable 3D Viewer to show STEP model from .dra file./ X' D4 x9 Q0 }, a6 d
1141747 ALLEGRO_EDITOR GRAPHICS 3D view dooesnot displays height if step_unsupported_prototype variable set& Q7 ^5 Q( T# ?1 R/ k6 N
1142215 SIG_INTEGRITY SIMULATION PULSE_PARAM set on DiffPair wasn't used for designlink simulation.* A3 |" [& g/ f% D4 _
1142798 ALLEGRO_EDITOR INTERFACES Step file output is incorrect in step viewer when composed of arcs and line. . o9 i. b% n* ]1 d( h1142894 FSP GUI Ability to RMB on a header and select `Hide Column�+ L. W0 w! E2 t
1142940 FSP EXTERNAL_PORTS Issue with checking/unchecking "Do not connect" and "External port" cells ' ~9 @1 Z V: N- Z6 U9 _1142949 CONCEPT_HDL SKILL Usage of "Preferences > License Settings� in FSP% Z8 `+ V& B, |6 }( Z! |
1143091 SIP_LAYOUT SYMB_EDIT_APPMOD symed: When AddPins is used to add pins to a co-design die, those pins are not output as bumps in the die abstract; V9 z$ z; b9 X2 s
1144371 CONCEPT_HDL COMP_BROWSER Component Browser search results are inaccurate 0 P9 H' g- L& }! R' x* x* c1145033 ALLEGRO_EDITOR PLACEMENT When aligning components with options in Placement mode displays no busy indicator. K+ ~7 H7 |+ T
1145286 CONCEPT_HDL CORE Directive required for switching off the console8 g# z; ^: Q. e8 W; U
1145800 ALLEGRO_EDITOR GRAPHICS Spurious odd lines are shown in shapes and text that are not part of the design with opengl." l+ i4 ]1 c) w: K. r$ V/ I
1147899 ALLEGRO_EDITOR SHAPE Autovoid two overlapping shapes that share the same net! p" s6 L7 V9 u- `! a3 a: G! G
1149996 ALLEGRO_EDITOR EDIT_ETCH Routing does not follow the ratsnest 'pin to pin'. ! x$ S, r7 y3 V* l. ^1150847 ALLEGRO_EDITOR INTERFACE_DESIGN Rename of DiffPair was not retained.. i4 j7 r9 y9 L# \5 M) I& r" o
1152577 ALLEGRO_EDITOR DATABASE slide removes cline seg k. G, @# \; p: O& O1152751 CONCEPT_HDL CORE Option to double-click and copy the Netname + Q1 U: }$ B+ T g) i1153220 ALLEGRO_EDITOR INTERFACES ENH: option to supress header/footer during PDF Export 2 [1 N# Y! R% H m. e: ~1153625 ALLEGRO_EDITOR INTERFACES If Symbol has place bound bottom, the step model shows incorrect placement. / F( c+ V% E, F0 \: m/ C1153813 CONCEPT_HDL CORE Spaces should not be allowed in the signal name entry form ' \6 a. H, j4 P1153857 CONCEPT_HDL CORE Changing different power symbol should maintain the schematic level properties. $ x! K0 u. H# p0 m( B0 C* G/ i1155161 CONCEPT_HDL CORE Add Signal name: Suggestion box overlaps with the typed signal name that is typed 8 R G5 h7 d$ Q+ T4 }8 Z( O1155922 CONCEPT_HDL OTHER How can I use the batch mode for PDF Publisher and print a variant overlay?: ]7 |2 ^# A$ X& ^8 M* j" v
1156858 ALLEGRO_EDITOR PADS_IN PADS Translator: Missing drill on square PTH padstack1 @- Y! d$ [4 W3 k, L! R
1157362 APD 3D_VIEWER Need a way to color multiple nets in 3D viewer from APD/SiP.& h1 r4 d! q4 x6 }
1158130 CONSTRAINT_MGR ANALYSIS Constraint Manager do not display the Cumulative Result in Reflection Simulation 9 v" _! m% @* s4 ]5 Y3 V1 O. X1158210 ALLEGRO_EDITOR SHAPE SIP Layout happens crash while users move the shape with route keep-out 5 `2 f0 {. n1 V1 k8 P# r1158452 SIG_INTEGRITY GEOMETRY_EXTRACT CPW differential traces are not extracted as coupled when they are routed at an angle 3 ^7 W, v3 G( F, w) E1158827 ALLEGRO_EDITOR EDIT_ETCH Slide a via in pad automatically add cline back to via to pin. 5 z6 E4 S7 C$ q1158871 PCB_LIBRARIAN IMPORT_CSV PIN TEXT is not automatically added when importing the .csv file) b) N; s/ t0 H; Q
1159738 ALLEGRO_EDITOR INTERACTIV Selecting the Cancel button in the Text Edit command does not cancel the text. 4 C9 [( v8 m. i! k! j1159878 SIG_EXPLORER OTHER Ecset mapping dont follow topology template - ^+ g5 o H/ I, C0 d$ u" b1159971 ALLEGRO_EDITOR MANUFACT Allegro PDF Publisher requires ability to control film record sequence when generating the combined PDF file 1 x6 c" X3 e! \1160017 SIP_LAYOUT DIE_ABSTRACT_IF Add text to clarify shrink operation3 [* M/ j4 O1 M9 W
1160507 APD EDIT_ETCH Script not playing back what was recorded when sliding lines6 g! P; a1 X7 U! D/ P I
1161261 ADW TDO-SHAREPOINT Schema for TDO-SP fails on Japanese OS9 Y3 f# Y% `/ j. X: n3 k6 X
1161538 CONCEPT_HDL CORE Espice model value edited in DE HDL & then netlisting done, but it doesnt changes the earlier assigned model in Allegro 1 T M: E: H0 Y' ^: S1161636 ALLEGRO_EDITOR DRAFTING need new function for PDFout : hatching shape - ~0 s5 N) _# s% y! W, P! Z- ?1161777 ALLEGRO_EDITOR OTHER default line width for PDF output9 x: j0 s& H6 I8 ]6 u
1162383 CONCEPT_HDL CHECKPLUS Checkplus not using $CDS_SITE/custom_help and $CDS_SITE/custom_rules_include directories. b& j* J3 I/ f6 g4 J0 ?2 H
1162562 CAPTURE STABILITY Capture crash on second attempt of pspice netlist creation in 16.67 S6 Q+ N4 k1 J: r+ ?6 u- Y
1162629 FSP PROCESS "Load Process Option" under Run does not work properly4 A4 Y5 e9 a2 z }& i0 ]
1162686 CONCEPT_HDL CORE Changing NET_SPACING_TYPE to display both shows up with $NET_SPACING_TYPE' f. C9 m9 E. d4 I
1163149 ALLEGRO_EDITOR DATABASE Autosilk creates Illegal arc to corrupt database- I# E, I& n5 f) H5 l4 O9 E" `6 Z
1163439 ALLEGRO_EDITOR COLOR Duplicate Views Listed in Visibility Tab.; B4 L8 c" |5 _5 Y! e& q( x
1163521 CONCEPT_HDL COMP_BROWSER System Architect crahes on replace6 D) O4 ~2 j7 S7 `8 V6 f! s! X
1163709 CONCEPT_HDL CONSTRAINT_MGR Loosing Diffpairs when reimport block or restore from definitioin 9 u& K) o% M9 j- h2 W1163902 APD EXPORT_DATA Q- In APD > File - Export - Board Level Component, check otion of delay reports is not working, is it ?% X$ c G; j: P4 ]
1164337 CONCEPT_HDL CORE Cannot delete attribute filter value in PDF > General > Attribute Filter list; M, ]3 y# g3 C+ y3 V1 B4 ]" W
1164365 ALLEGRO_EDITOR INTERACTIV Symbol not selected for Move because Symbol Pin number selected in options tab not available on symbol6 V% |1 @1 n h9 e
1164769 APD VIA_STRUCTURE The replace via structure command does not accept a single canvas pick. 5 i: O" A9 |' r( T( T6 x) T7 R1165026 ASI_SI GUI EMS3D exist in Via Model Setup of SI base. ; Q8 m$ D4 O8 G f" W7 y( Y8 k1165561 CAPTURE DRC File > Check and Save clears waived DRCs " h1 v( p1 ]- y6 v6 h: M1165631 CAPTURE STABILITY Capture crash in the hierarchy tab of Project Manager window 3 D. k4 s/ G9 J, w* G8 W1165836 SIG_INTEGRITY GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation.(update)# T% \* o' i. N
1165911 FSP PROCESS Editing group name in protocol causes incorrect Process option checked8 P; C- O q* r* Q4 W
1166026 ALLEGRO_EDITOR DATABASE Running DB Doctor removes net name from vias + j9 a) {6 L$ n9 G4 k! ?1166034 SIP_LAYOUT OTHER SiP - Cline Change Width command enhanced to have selection by polygon not just rectangle ; l4 [! {( t% R. g& o z- x& P {1166074 GRE CORE GRE crashes during planning phases/ w5 ^) c! ?6 J- o+ C! `
1166319 ALLEGRO_EDITOR PLACEMENT Swap not succeed3 v- V! U, j4 b2 B
1166484 SIP_LAYOUT WIREBOND Bondfinger "Align With Wire" problem during move * c, P8 G u) {; h9 B# s* U& x1166530 ALLEGRO_EDITOR INTERACTIV Bug: Mirror in Placement Edit resets the options tab for Edit > Move : j; r: M- P8 Y" V' u6 J1166819 CONCEPT_HDL CORE Cadence DEHDL Text Size Issue 9 l2 ~/ D6 ~- A5 V- h1167847 CAPTURE PROPERTY_EDITOR Implementation name length greater than 31 character causes capture crash : W0 N& G/ A2 Z( T3 U2 p1167887 F2B OTHER Improve message on symbol to schematic generation " m2 d/ i7 _- e1168369 F2B DESIGNVARI Variant don縯 appear in increasing order while Annotate.. z* H! |( S* g; t: ^( T; V: t
1168629 APD OTHER Do we have Skill command which is equivilant to Change Characteristics operation of a Wire Bond in APD 7 z: a7 J1 t5 Q# q: ~1168678 ALLEGRO_EDITOR NC Drill Figure will be changed wrong layer when some subclass was deleted in SPB165S045.# @( w/ V) B2 }. C3 u7 T5 D& q) x* E
1168798 ALLEGRO_EDITOR INTERACTIV Enh - Allow user the ability to set the visibiity layer of refdes while moving the symbol rather than fixing it to silk 4 |" f& ?4 q4 J8 W A9 L2 n1168830 ALLEGRO_EDITOR DRC_CONSTR missing DRC-marker for package to package check ( C' c9 Y" Y0 ]1168864 ALLEGRO_EDITOR CREATE_SYM Saving the dra after Shape Expand/Contract throws warning 'Sector Table is not empty/ e' p8 [6 Q9 }9 [% j9 w$ J, d
1169213 PSPICE SIMULATOR Parametric sweep is giving incorrect reuslts # [! S D+ {5 W* r1169436 FSP FPGA_SUPPORT Add support for Cyclone V CSX and CST parts! g1 K3 {; f/ f
1170108 ALLEGRO_EDITOR INTERACTIV Enhancement to preserve Rat T location for Topology assigned schedule 9 C9 j: y! X) r$ r! E. l4 l1170313 SIP_LAYOUT LOGIC scm adding additional pin names and unassigned property to codesign die chips file % M$ S$ m- c& m1171136 CONCEPT_HDL CORE Page Number should also be displayed in Import Design Window. " B+ C* i' U8 y' q1171747 ALLEGRO_EDITOR PLACEMENT Allegro crashes when doing a gate swap between components7 R/ h/ z$ K5 v" [% X' U* }5 i
1172183 ALLEGRO_EDITOR INTERACTIV Alignment modules fails on equal spacing" T) e3 _3 M1 k5 N; U( ~: o
1173183 ALLEGRO_EDITOR DRC_CONSTR Undesired Same net DRC for overlapping Pin and Via. X( j- \$ S, Q+ g6 z
1174067 ALLEGRO_EDITOR DRC_CONSTR Soldermask to shape drc does not show if the layer is a PLANE. % m. O( Z( K; V8 S0 D1174338 ALLEGRO_EDITOR PLACEMENT preview has rotated pads + I2 [0 i8 [, j9 H1175307 CONSTRAINT_MGR ANALYSIS CMGR fails to report RPD DRC for accuracy 4 - mm # D# ~3 f+ ]/ F, g- W- H/ }+ Y! l1175537 ALLEGRO_EDITOR REPORTS net loop report crashes Allegro. Design specific+ k1 z- c$ |& e
1176126 ALLEGRO_EDITOR INTERFACES 3D viewer doesnot change models units dynamically ( n4 ]* U( ?9 o* H' U" O1176281 CONCEPT_HDL CORE Option to Auto-hide excluded modules % W# f& `8 [+ c7 J, ~1176413 ALLEGRO_EDITOR MANUFACT Q - testprep parameter settings is not retained, what could be the cause..0 y/ Q/ j/ ~4 S- }' Z
1176791 ALLEGRO_EDITOR GRAPHICS Spurious odd lines are shown in shapes and text that are not part of the design with opengl7 y. y" P* P7 Q5 h: e
1178052 ALLEGRO_EDITOR SHAPE SIP crashes during shape degassing. + m/ @+ a' t- P2 Q e1178158 ALLEGRO_EDITOR INTERFACES Export step file creates step file of same height 8 r' k$ B0 L/ _/ N/ M2 Y1178201 ALLEGRO_EDITOR GRAPHICS Large oval pads rendered as oblong hexagons in the 3D viewer( Q; |$ ^2 y; c$ K
1178671 ALLEGRO_EDITOR GRAPHICS 3D Viewer in package symbol editor not displaying correct place bound shapes. 9 w$ _/ z% F. ^4 `" U1178725 ALLEGRO_EDITOR OTHER With fillets present, rat lines do not point to the closest endpoint.8 l, P0 g+ }& [7 K
1178972 CONSTRAINT_MGR ANALYSIS The Cross-Section's parameters was not applied immediately after importing a DCF on the Constraint Manager. # d6 X, V U3 Y( X4 B. L0 i1179093 ALLEGRO_EDITOR SHAPE Dynamic Shape for GROUND net on TOP Layer is corrupted and is not voiding correctly in certain areas. 0 w' _: ]9 a$ W. V+ t; u) k1179109 ALLEGRO_EDITOR OTHER DXF importing makes figure shift in 16.5&16.6 version it is ok in 16.3 version - _: j" N( `+ u/ k' o1 x8 x1179571 ALLEGRO_EDITOR ARTWORK Artwork crash and artwork log report Aparture missing6 ^1 W) I$ h) y6 k+ x" Q0 _
1179636 SPECCTRA ROUTE Route Automatic will not start if NET_SHORT are attached to a mec-pin 6 [" Q/ ?+ Q. a) x1179659 SIP_LAYOUT DIE_EDITOR die edit on co-design die losing c4 bumps( [ X, N* C% m' G3 U, J1 W. _
1180306 ALLEGRO_EDITOR ARTWORK When trying to create Artwork the tool crashes with no error messages just a little X box, b, `5 u1 k8 ^$ b
1180573 ALLEGRO_EDITOR ARTWORK If one layer has warning, all artwork films are "created with warning". 9 T; t I7 e0 c2 ?1180960 SIP_LAYOUT PLACEMENT swap function is not swapping logical paths in sip layout! i6 i2 v* n! S/ j. k
1182534 ALLEGRO_EDITOR SKILL axlLayerPrioritySet() not working with v166 s013 and up. j; P+ c3 L. B' R$ y+ ]! y! f% Z
1182560 ALLEGRO_EDITOR PLOTTING Creating plot 2nd time casues Allegro to crash , k8 L8 A5 Z0 \* `1182616 ALLEGRO_EDITOR PLACEMENT Application crashes when attempting to place a high pin count BGA 6 s/ a( U) v z C! ~1183752 CONCEPT_HDL CORE Unable to modify location properties within a read-only hierarchical block( c$ H; }$ O* l1 {
1183774 SIP_LAYOUT DIE_EDITOR Die Refresh hangs : D. Z+ ?" q) U4 V% k6 k" S# h' e1184178 CONCEPT_HDL CONSTRAINT_MGR Ecset xnet members lost from electrical class when restore from definition of subblocks 3 R9 V4 B& h! ~1184787 ALLEGRO_EDITOR EDIT_ETCH Allegro SPB166 s 015 crashes during normal add connect function.0 [, j7 [. B& n& W o5 ~
5 l! h) L* ?: {# a3 V' K% h3 ^
DATE: 08-22-2013 HOTFIX VERSION: 015$ C3 X) R* [* g, t6 c& \# F/ Z
=================================================================================================================================== 3 l2 K( Y; K+ gCCRID PRODUCT PRODUCTLEVEL2 TITLE, g q1 C3 W) i5 q1 F: K6 {3 u
=================================================================================================================================== ! H. q" c( Y! h0 U' T7 N0 P1156102 PCB_LIBRARIAN CORE PDV severe performance degradation on Linux platform makes PDV counter productive after some time + {6 v2 I2 E- ^1165756 CONCEPT_HDL CORE DE HDL 16.6 adding ASCII character to properties + Q1 J+ m% _' y# b& ~( Q& g+ N1169896 ADW LRM Library Revision Manager makes updates but the interface never returns to the user- C6 m; J# M U5 H/ m. w
1170635 SIP_LAYOUT WIZARDS BGA PIN NAME doesn't sync with PIN Number R% \; C5 B. I7 W1171061 ALLEGRO_EDITOR PLACEMENT Place Replicate Apply cannot place module' `4 {' w. U* L8 A% ~( d; ?
1171415 CONCEPT_HDL CORE Mismatch in the interface ports in design bw_hybrid for block a38410_scsp \ s/ ?/ s* A
1171598 APD WIREBOND Cannot load xml over 65 profiles defined in file.$ i1 a% L5 g# a7 B3 U* |1 O6 o3 D
1171713 ADW LRM Blank lines appear in the LRM - RM-Clicking causes LRM to crash0 K# |3 W& _# F+ w
1172576 SIP_LAYOUT IMPORT_DATA AIF import fails with Error: symbol is missing refdes 7 {; `: _& ]7 q! }% q# m. O+ }1172938 ALLEGRO_EDITOR PLOTTING Export IPF probrem ! h( c3 D+ \; u* j, ^0 V1173190 ALLEGRO_EDITOR ARTWORK Not able to Add/ Replace film_setup.txt file in Artwork control file.3 z' X' d$ {0 k
1173750 ALLEGRO_EDITOR REPORTS SIP tool crash when clicking report "Net Loop Report"/ J3 X. c+ I; }
1175582 ALLEGRO_EDITOR SKILL axlDBCreateFilmRec error undifined function 3 j3 Q% E m# ?- R5 ^1 X: m9 E/ o" Q6 b4 y
DATE: 08-9-2013 HOTFIX VERSION: 0143 q6 O+ ]: @! F9 z N' a; n
===================================================================================================================================* J8 N- v ]7 w- A
CCRID PRODUCT PRODUCTLEVEL2 TITLE 9 v x8 Z9 L. o===================================================================================================================================. g+ b+ G- o/ G6 Y6 S) p
1155569 APD MODULES P1_U1 and P1_U3 Die pins are missing after Place Module.$ Q+ h- |% e4 W# H. p
1158528 CONCEPT_HDL OTHER Dual Monitor issue: Retain Hard Packaging option is missing and attribute test distorted $ p2 T! L/ w0 G/ L7 x1160968 ALLEGRO_EDITOR SKILL Text Subclass change difference in Edit > Change and axlChangeLayer Skill command 6 G) Y# b% i4 i$ @' V6 H. y) t1161986 SIG_INTEGRITY SIMULATION Flatline waveform seen when via model is set to detailed closed form or analytical solution 5 y1 S8 v8 ` l$ m4 `( a. {) }1162323 SIP_LAYOUT DIE_EDITOR Die Editor is incorrectly leaving an unassigned function pin in the die during refresh from die abstract4 O4 D( c2 Q5 f, a- O
1162752 ALLEGRO_EDITOR SKILL axlDBChangeText doesnt recognize ?layer as a valid argument as documented $ @6 h2 t+ h5 s- j) M% V0 G1165002 GRE CORE GRE Crashes during Plan Spatial giving "Memory Allocation Failure" Error. . U: l7 l: X* y$ X7 s0 j1165469 CONCEPT_HDL CORE Import Design loses design library name 8 Q. `# w: e c7 e" N# t( Q1165708 ALLEGRO_EDITOR TESTPREP Test point router failing when attempting to insert new TP via's6 Y5 g1 Q; i2 }* i- P
1165801 CONCEPT_HDL PDF Pin texts of spun symbol overlap in publish PDF.5 p! {4 B8 Z) v) m
1166020 SIP_LAYOUT WIREBOND Bondpads created with shapes do not follow the orthogonal pattern when adding wirebonds.! s H3 P: M# }
1166371 ALLEGRO_EDITOR DATABASE File locked for writing in 16.5 cannot be unlocked in 16.61 _. Y3 e- }7 X- H% w
1166482 ALLEGRO_EDITOR INTERFACES Step orientation for y-rotated component is not exported correctly.& R" v3 N+ J( {# n5 W
1167519 ALLEGRO_EDITOR DATABASE Uprev dbdoctor does not log warnings about renaming properties.2 b4 y# `, I {4 j
1167588 SIP_LAYOUT DIE_ABSTRACT_IF do not create a new pad stack for each I/O pad & I/ f( s9 N# h" k( f4 D1168496 ALLEGRO_EDITOR SCHEM_FTB Export Physical Crashes when netreving the board 4 t/ k" {. [ o7 y+ Q1169510 SIP_LAYOUT WIZARDS Netlist in Wizard is crashing with this text file where the Net Name for one of the assignments is blank, meaning dummy. }" V7 `$ A0 W6 I3 k* Q! n: G
1169593 CONCEPT_HDL PDF Published PDF file's hyperlinks do not work fine when user click 1D10 or 2A10. , F* C) ]6 ?/ a2 D q1169984 F2B PACKAGERXL Error Mapping cset when packaging but not in CM Audit T( g: m& c [# D+ x# l1171008 SIP_LAYOUT OTHER SiP Layout - Beta feature Void Adjacent Layer Shapes - changes or modifies "priority" of other/all shapes ; }' z. h" E% ]4 _0 |1171411 ALLEGRO_EDITOR OTHER Enh - Break in Step 3D view in latest hotfix v16.6s013 * W- H. v! t. ?7 m$ l, i- C( T* `: O T( n/ J
DATE: 07-26-2013 HOTFIX VERSION: 013 ' o- _6 \4 P/ f+ A=================================================================================================================================== % b9 D2 L4 o `. I0 l1 z" F' r( p7 NCCRID PRODUCT PRODUCTLEVEL2 TITLE9 a* d. t4 z( X. D/ u- _
=================================================================================================================================== " |6 ]- T2 ?% d2 ~5 K111368 CAPTURE CORRUPT_DESIGN Capture - will not produce allegro netlist with 10.0* S3 x" x, J8 s* g8 d9 c _
134439 PD-COMPILE USERDATA caCell terminals should be top-level terminals 8 i' K) K4 K, T) T) A( G& f; Z1 i7 T186074 CIS EXPLORER refresh symbols from lib requires you to close CIS! F% c! V7 ^; U7 F! d" L& u
583221 CAPTURE SCHEMATIC_EDITOR Option to have the Schematic Page Name as a Property in the Titleblock) m, p6 ]. u8 P
591140 CONCEPT_HDL OTHER Scale overall output size in PublishPDF from command line* T7 |- o. { Y
801901 CONCEPT_HDL CORE Concept Menus use the same key "R" for the Wire and RF-PCB menus 0 b" f. s1 C3 G* H4 `4 z& t' O813614 APD DRC_CONSTRAINTS With Fillets present the "cline to shape" spacing is wrong.8 O& H4 ]1 ^$ \7 b! {" d. j
881796 ALLEGRO_EDITOR GRAPHICS Enhancement request for Panning with Middle Mouse Button7 v7 \: c! u. S, E# Y' L7 f
887191 CONCEPT_HDL CORE Cannot add/edit the locked property * |1 n! r* M& f# ~# s+ q6 ^, ^911292 CONCEPT_HDL CORE Property command on editing symbol attaches property to ORIGIN immediately % j6 L9 N4 U) k987766 APD SHAPE Void all command gets result as no voids being generated on specific env. 8 Y% b7 A3 I( R9 M; s# @1001395 SIP_LAYOUT ASSY_RULE_CHECK Shape Minimum void check reports lots of DRCs which are not necessary to check out. & i, K2 g2 e; ~ x& t2 S8 N1030696 ALLEGRO_EDITOR INTERACTIV Enh - Allow another behavior of PAN movement using middle mouse in Allegro ! W& L; D! c( j4 a1 Q3 }- ]; B1043856 ADW TDA Diff between TDO and DE-HDL Hierarchy Viewer is confusing to the user. ^3 b$ c7 C9 L$ A3 K' x
1046440 ADW PCBCACHE ADW: ImportSheet is not caching libraries under flatlib/model_sym when the source design is not an ADW project 5 c3 Z* {* ~+ `4 z0 ]1077552 F2B PACKAGERXL Diff Pairs get removed when packing with backannotation turned on t" R! o: G. ?7 c# m6 t
1079538 F2B PACKAGERXL Ability to block all 縮ingle noded nets� to the board while packaging. & _* L" u8 v. l1086362 ALLEGRO_EDITOR SHAPE Enhancement request to autovoid a via if shape cannot cover the center of the via. & r: B6 T- w6 i- I1087958 PSPICE MODELEDITOR Is there any limitation for pin name definition?% j5 i& y* v' T/ n9 s: R
1087967 CIS UPDATE_PART_STAT Update part status window shows incorrect differences% E# d; V7 l; f/ M2 \
1090693 ADW LRM LRM auto_load_instances does not gray out Load instances Button; E0 {. a: M m" U, @
1097246 CONCEPT_HDL CORE ConceptHDL - assign hotkeys to alpha-numerical keys ]& O0 @( v) K1099773 CONCEPT_HDL CORE DE HDL goes into recursive loop if a custom text locked at site level is deleted from Tools > Option+ G2 n: P |' m% ~& M6 [( r8 m
1100945 SCM SCHGEN SCM generated DE-HDL has $PN placement issue0 d# i( f/ e t
1100951 PSPICE SIMULATOR Increasing the resolution of fourier transform results in out file , x3 n- `- y( \7 m0 \: A2 h6 l& ], D1103117 RF_PCB FE_IFF_IMPORT Enh- Allow the Allegro_Discrete_Library_to_ADS_Library_Translator to output in its original unit 5 J9 M1 m- P" W! C! E3 x1105473 PSPICE PROBE Getting error messages while running bias point analysis.0 X* t7 g+ v2 f! N0 \/ v
1106116 FLOWS PROJMGR view_pcb setting change was cleared by switching Flows in projmgr. ! _# `8 k. x% A: Q; L6 u D" e1106298 ALLEGRO_EDITOR INTERACTIV Copy Shape uses last menu pick location as origin and not the Symbol Origin as specified in Options. ; \$ ~6 ~7 v- |/ \0 T# E& A/ n1106626 CONCEPT_HDL CORE Concept HDL crashes when saving pages . `5 H. a4 m8 d4 }; X d1107086 ALLEGRO_EDITOR INTERACTIV manual void with arc's goes in wrong direction during arc creation. I3 j0 N+ h& J2 k+ N% r, N
1107172 CONCEPT_HDL OTHER Project Manager Packager does not report errors on missing symbol9 `2 n- o9 A( _. ]/ O3 c/ H
1108193 CONCEPT_HDL CORE Using the left/right keys do not move the cursor within the text you're editing8 t; ~; s* M+ q2 X8 k b k
1108603 PCB_LIBRARIAN VERIFICATION PDV Tools Verification > View Verification (CheckPlus) leaves <project>.cpm_tmp.cpm9 q5 V& h5 [ G
1109024 CIS OTHER OrCad performance issue from Asus. - l0 i0 h+ u, _. }0 u5 c/ Q1109109 CAPTURE NETLIST_ALLEGRO B1: Netlist missing pins when Pack_short property pins connected 1 S4 \# L8 x, g) u: z8 }1109466 ALLEGRO_EDITOR ARTWORK Artwork create some strange gerber lines for fillet. # P$ h$ u: N( }; L" f6 g8 i W+ C9 q1109647 SIP_LAYOUT DEGASSING Shape degassing command enhancement - control over what layers are counted in even/odd layer sets. 9 p+ ^: t3 ]7 ~7 J' _1109926 CONCEPT_HDL CORE viewing a design disables console window5 Q9 g' _3 @, R, {
1110194 SIP_LAYOUT WIREBOND If OpenGL settings for display of dynamic net names is enabled, should be visible while push/shove wirebonds. ( W! J+ q% [8 f0 _1112357 SIP_LAYOUT WIREBOND wirebond command crashes the application! P' V4 _1 J8 Z$ d8 c& G/ j$ W& n
1112395 CONCEPT_HDL CORE 縗BASE\G� for global signal is not obeyed after upreving the design to 1650. 2 m' L" f* }8 a4 m- p+ w) T1112658 CAPTURE PROPERTY_EDITOR Changing Part 縂raphic� value from property Editor Changes Occ refdes values to instance 5 f- o, W3 f% C4 e* q+ {- L7 _( G4 E1112662 CAPTURE PROJECT_MANAGER Capture crashes after moving the library file and then doing Edit> Cut. m6 F% ~" U* m3 U& u% u. \
1113177 PCB_LIBRARIAN CORE Pin Shapes are not getting imported properly ( g+ p+ C$ V4 I) X$ w6 m1113380 ALLEGRO_EDITOR INTERACTIV Change layer to - option for package type .dra is not available in 16.6 release3 A6 Q8 ~, Q( T# `2 A
1113656 SIP_LAYOUT WIREBOND Enable Change characteristic to work without unfixing its Tack point. , {, U* j' C* d1 e8 K/ m4 M# M1113838 SIP_LAYOUT DIE_ABSTRACT_IF probe pins defined in XDA die abstract file are added with wrong location + @: b8 D8 p: ?/ q& C8 O1113991 CAPTURE GENERAL Save Project As is not working if destination is a linux machine 1 ~: `$ }% D- ^) S5 b5 e8 ]9 i9 L9 { G- m1114073 APD DRC_CONSTRAINTS Shape voiding differently if there are Fillets present in the design. # b4 b0 a6 E; }! x/ O1114241 CAPTURE SCHEMATIC_EDITOR Port not retaining assigned color, when moved on the schematic6 k. b% i. _2 ~6 ^/ P: U
1114442 PSPICE PROBE Getting Internal error - Overflow Convert with marching waveform on + o/ ?, {* |1 X; U2 e9 W& r+ r1114630 CONCEPT_HDL ARCHIVER Archcore fails because the project directory on Linux has a space in the name( {2 ~) d; x5 F W X$ C: v* W
1114689 CONCEPT_HDL CORE Unknown project directive : text_editor & l" {! r3 k4 O1114928 F2B PACKAGERXL 縀rror (SPCODD - 5) while Export Physical even after change pin from A<0> to A $ T0 v/ n8 {' }# \- ]1116886 CONCEPT_HDL CORE Crefer hyperlinks do not work fine when user use double digits partitions for page Border." A# E6 D; u- y; q2 w. r
1118088 ALLEGRO_EDITOR EDIT_ETCH Should Plan accurate and Optimize be removed in 16.6?$ C1 l( {$ E7 h }2 J+ T
1118734 APD EDIT_ETCH Multiline routing with Clines on Null Net cannot route in downward direction. j0 O/ j4 H3 i% _ p; v8 c
1118756 ALLEGRO_EDITOR SHAPE Shape clearance parameter oversize values getting applied to Keepouts, U5 r0 D/ B) B/ q0 ~1 ~ q/ R( _9 P
1119606 CONCEPT_HDL MARKERS Filtering two or more words in Filter dialog box" O; R! S5 _' @1 V: g) A+ r
1119707 CONCEPT_HDL CORE Genview does not use site colors when gen sch from block symbol 6 a, `- I ~- G# a4 k1119711 F2B DESIGNSYNC Design Differences show Net Differences wrongly 7 E( T6 e" @2 G; L; i) D$ ~( k6 u1120659 CAPTURE PROJECT_MANAGER "Save project as" does not support some of Nordic characters.5 E( _6 Z1 M3 H
1120660 CONCEPT_HDL CORE Save hierarchy saves pages for deleted blocks. * E+ Q' f# G4 O0 d. e0 B1120817 SIP_LAYOUT SYMB_EDIT_APPMOD Rotate Pads commands not working while in the Symbol Edit App. mode7 Y4 J% j4 Y5 L7 g. h+ Z
1120985 PSPICE MODELEDITOR Unable to import attached IBIS model1 r) A& c' O" q6 W
1121171 CONCEPT_HDL CREFER PNN and correct property values not annotated on the Cref flat schematic c1 v. X1 g" O0 e
1121353 ALLEGRO_EDITOR INTERACTIV Local env setting will change after saving and reopening.0 A4 b9 X2 Y8 w0 j; b% {
1121382 ALLEGRO_EDITOR INTERACTIV Undo command is limited to two for this design 3 }) |" N, l$ \ @9 E1121540 F2B PACKAGERXL pxl.chg keeps deleting and adding changes on subsequent packager runs : B: i0 u1 U) a0 z3 S* I1121558 ALLEGRO_EDITOR MODULES Unrouted net and unrouted connection when module is placed of completely routed board file. 2 P2 X$ i* }% e3 i7 V' m7 [1121585 ALLEGRO_EDITOR OTHER Drill Hole to Shape Same Net Spacing with Dynamic Shapes shows wrong result. # R# ]0 ]& l7 B0 v1121651 CAPTURE SCHEMATIC_EDITOR "PCB editor select" menu option is missing }. o2 M% \" \- ^1122136 SIP_LAYOUT PLACEMENT Moving a component results in the components outline going to bottom side of the design. : H( K* i, W! \1 ^+ F1122340 CAPTURE NETLIST_ALLEGRO Cross probe of net within a bus makes Capture to hang. 4 D W3 z3 [) c0 x5 e' w+ s1122489 CONCEPT_HDL OTHER Save _Hierarchy causing baseline to brd files 1 r) \) V/ ?6 F! [1122781 CONCEPT_HDL CORE cfg_package is generated for component cell automatically 2 x W$ v7 K0 j/ a" ^6 e3 p* E1122909 CONCEPT_HDL CORE changing version replicates data of first TOC on 2nd one ' t. k6 L$ E) u2 k6 k2 j. h) t7 w3 i1123150 CONCEPT_HDL CORE property on y axis in symbol view was moved by visibility change to None. 3 N* l H% e; Z$ |1123176 ALLEGRO_EDITOR UI_FORMS Negative values for pop-up location is not retained with multiple monitors (more than 2)' {' {4 U" {# E/ W
1123815 ALLEGRO_EDITOR GRAPHICS Embedded netname changes to a different netname2 r) f7 ?( p! L. m+ c
1124369 ALLEGRO_EDITOR INTERACTIV Sliding a shape using iy coordinate does not work indepedent of grid.- Q, N) ]3 k$ g: P7 E
1124544 CONCEPT_HDL CORE About Search History of find with SPB16.5( }7 ?! J8 H0 f
1124570 APD IMPORT_DATA When importing Stream adding the option to change the point / i5 W- \, \/ j6 A l1 x1125201 CONCEPT_HDL CORE Connectivity edits in NEW block not saved( lost) if block is created using block add* j7 V& d4 c2 d: R% n5 x3 t
1125314 ALLEGRO_EDITOR INTERACTIV Enved crash during setting of library paths in user preference6 O `3 |4 L K+ H( U
1125366 CONCEPT_HDL CORE DE-HDL craches during Import Physical if CM is open on Linux( X' T* m h; h% W
1125628 CONCEPT_HDL CORE Crash on doing save hierarchy$ U2 Q0 R& e! d/ L7 \
1130555 APD WIREBOND Wirebond Import should connect to pins of the die specified on the UI.* A0 t3 t8 G# E h; |/ U
1131030 PSPICE ENVIRONMENT Unregistered icon of Simulation setting in taskbar$ G( \3 ~0 B, y$ V& M% |9 N& _4 B& O
1131083 ALLEGRO_EDITOR INTERACTIV Bug: 16.6 crash in changing the mode in Find filter window/ _& @7 {8 l% g& @8 ~9 C
1131226 ALLEGRO_EDITOR PLACEMENT When Angle is set in design parameters while placement component is rotated but outline is not. - X! z/ K! k' T1 F. h- v1131567 CONCEPT_HDL OTHER Lower case values for VHDL_MODE make genview use pin location to determen direction. 2 }7 ]3 W+ E7 S( ~2 t) d1131699 PSPICE PROBE Probe window crash on trying to view simulation message + }7 f" C+ q2 ]- ]* v1132457 CONCEPT_HDL CORE The schematic never fully invokes and has connectivity errors.; y! I6 l$ u- S, a# X0 K$ ^& e2 y
1132575 CONCEPT_HDL CORE 2 pin_name were displayed and overlapped by spin command. . m9 H: Z. d. {7 L1132698 ALLEGRO_EDITOR EDIT_ETCH Slide Via with Segment option with new Slide command6 ]8 N. z; O9 s! a; G
1132964 ALLEGRO_EDITOR SHAPE Same net "B&B via to shape" errors created when adding shape9 _( b0 b' C" A9 y& g
1133677 CONCEPT_HDL CORE Cant delete nor reset LOCATION prop in context of top L [. [9 F2 H2 J" H( \* M/ ]
1133791 CONCEPT_HDL CORE Cant do text justification on a single selected NOTE in Windows mode.! m; Y& p! G' y4 c J
1134761 CONCEPT_HDL CORE Why does Mouse Pointer/Tooltip display LOCATION instead of $LOCATION property% S( F! J2 f' B2 t9 D$ |- p6 r
1135118 ALLEGRO_EDITOR INTERACTIV Mirror and other editing commands are missing for testpoint label text in general edit mode.; g2 ], s) r5 G K# N/ K: v" L
1136420 CAPTURE GENERAL Registration issue when CDSROOT has a space in its path( `( W( A8 ?) e! w @
1136808 PSPICE STABILITY Pspice crash marker server has quite unexpectedly9 Q# b3 P# l! r9 Q+ o
1136840 CAPTURE SCHEMATICS Enh: Alignment of text placed on schematic page. A% J% r2 T- F# x. j6 q
1138586 ADW MIGRATION design migration does not create complete ptf file for hierarchical designs6 o8 q) E7 P: ]* d, T% h8 o& ~
1139376 CONCEPT_HDL CORE setting wire color to default creates new wire with higher thickness' y8 z" p2 _2 `" i. e
1140819 APD GRAPHICS Bbvia does not retain temp highlight color on all layers when selected. ' {& i6 w# R& b2 i. a% b% z8 p1141300 CONCEPT_HDL CORE DE HDL hier_write save hierarchy log reports summarizes Successfully saved block x while block was skipped/ P2 \, R! E, a4 P; H
1141723 ADW PURGE purge command crashes with an MFC application failure message : ~, L0 R, G( [( R) S1143448 CAPTURE GENERAL About copy & paste to Powerpoint from CIS 5 s" w" @& M( _% d9 c& U. ?1143670 SIP_LAYOUT OTHER Cross Probing between SiP and DEHDL not working in 16.6 release ) O2 g; a. k' R8 ^$ W5 c4 t8 p1143902 ALLEGRO_EDITOR DATABASE when the shape is rotated 45 degrees the void is moved. $ R) P+ O& O9 `1144990 PCB_LIBRARIAN CORE PDV expand & collapse vector pins resizes symbol outline to maximum height " a# I4 L1 a7 j' `! [5 ~! N1145112 CONCEPT_HDL CORE Warning message: Connectivity MIGHT have changed & ]/ X8 S j7 c* f) t9 M( L& c7 W# Y1145253 CONCEPT_HDL CORE Component Browser adds properties in upper case( g$ l: n6 ^6 x
1146386 ALLEGRO_EDITOR INTERACTIV Place Replicate Create add Static shape with Fillet shape; l( }5 }5 O- I8 \( X5 Y8 p
1146728 F2B PACKAGERXL DCF with upper and lower case values on parts causes pxl to fail : w* q$ m7 N. o+ s1146783 ALLEGRO_EDITOR INTERFACES Highlighted component is missing from exported IPF file. * F0 N) ]; `; l3 Q+ M/ k0 x1147326 CONCEPT_HDL CORE HDL crashes when trying to reimport a block / e- N1 q; J' Y- S8 W5 t1148337 CAPTURE ANNOTATE Checking "refdes control" is not giving the proper annotation result0 f- i7 r! s- h7 a) |3 E
1148633 SIP_LAYOUT INTERACTIVE Add "%" to the optical shrink option in the co-design die and compose symbol placement forms ) I. ~* A L4 a: a: b1149778 CAPTURE SCHEMATICS Rotation of pspice marker before placement is not appropriate 0 l# f# I2 e- p5 S- f1149987 PCB_LIBRARIAN PTF_EDITOR Save As pushing the part name suffix into vendor_part_number value9 a$ m2 |: z6 \/ p0 J
1151748 ALLEGRO_EDITOR OTHER If the pad and cline are the same width don't report a missing Dynamic Fillet.$ r8 T1 { \ Q, W
1152206 CONCEPT_HDL CORE ROOM Property value changes when saving another Page! q# m* f9 v( p- H) w% c% e
1152755 CONCEPT_HDL COPY_PROJECT Copy project hangs if library or design name has an underscore 3 K# t# q( ?1 e; C1152769 PSPICE ENCRYPTION Unable to simulate Encrypted Models in 16.6 ( G+ |/ l; X: E3 }: V# a/ S+ r1153308 ALLEGRO_EDITOR DRC_CONSTR Creating Artwork Getting Warning "DRC is out of Date" even when DRC is up to date. S7 \% v d& |8 Y) A( z+ q; N
1153893 F2B DESIGNVARI 16.6 Variant Editor not supporting - in name8 w* v( B( I1 `7 H3 `
1154185 SIG_INTEGRITY SIGNOISE Signoise didn't do the Rise edge time adjustment. : C: X% Q% `% t/ w" l+ x7 G1154860 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figures triangle, hexagon and octagon in NC drill legend2 i" Q) @( U; {9 t' Z: y/ g2 g9 J! [
1155167 ALLEGRO_EDITOR EDIT_ETCH Via structure placed in Create Fanout has incorrect rotation. # d! u0 c% l' _7 _1155728 CONCEPT_HDL CORE Unable to uprev packaged 16.3 design in 16.5 due to memory # d2 [ z- @) z+ j$ j1155855 SCM SCHGEN A newly user-defined net property is not transferred from SCM to DEHDL in Preserved Mode - n9 Q2 v# W7 @$ N, t1156274 ALLEGRO_EDITOR INTERFACES Exported Step file from Allegro is wrong+ W6 u9 ]2 T V* F0 \
1156316 CONSTRAINT_MGR OTHER Break in functionality while creation of pin-pairs under Xnet in Constraint Manager' h9 t B/ _, V3 ~3 W+ |
1156351 CONCEPT_HDL CONSTRAINT_MGR Loose members in Physical Net Class between DEHDL and Allegro& P' l- @6 C9 @1 I) [6 Q X4 g9 Y6 y) E* S
1156547 ALLEGRO_EDITOR DRC_CONSTR Etch Turn under SMD pin rule check through pin Etch makes confused.' A2 q/ @6 p0 _' R: X3 x
1156779 CONSTRAINT_MGR OTHER Electrical Cset References in CM not working correctly8 x+ V. Y7 Y6 X/ a; M7 k4 n
1157167 ALLEGRO_EDITOR SKILL axlPolyFromDB with ?line2poly is broken 3 d$ n& p- O' u9 }# h7 X) B( `1158042 ALLEGRO_EDITOR DFA DFA_DLG writes the dra file name in uppercase., \. x' H3 W+ I
1158718 CONCEPT_HDL CHECKPLUS Customer could not get $PN property values on logical rule of CheckPlus16.6. G- A6 n4 c6 q2 O- e6 \! ~4 f
1158970 ALLEGRO_EDITOR SCHEM_FTB Changing LOCATION to $LOCATION in DEHDL does not update the .brd file) z5 {; j% `+ |& @4 f. Z, T- P) {
1158989 ALLEGRO_EDITOR INTERFACES pdf_out -l creates a PDF. [+ H6 x& s" f0 O. \
1159285 APD DXF_IF DXF_OUT fails; some figures are not exported3 i- X% x) j! E; `5 D/ I0 A" R
1159432 ALLEGRO_EDITOR SHOW_ELEM http:// in the Show Element in 166 do not have HTML link to open the Website% E* V7 a! M1 ?3 ~
1159483 PCB_LIBRARIAN SETUP part developer crashing with ( C" w- f1 @3 T1159516 ALLEGRO_EDITOR EDIT_ETCH Unable to slide cline segment with new slide. + h# i; u) m' O) w* p9 s1159959 ALLEGRO_EDITOR GRAPHICS 3D viewer displays clines arcs incorrectly 9 _% a1 D2 W4 G3 L: ]: ]' T0 T9 s1160004 SCM UI The RMB->Paste does not insert signal names. , x0 P9 n2 ^5 k( c1160410 ALLEGRO_EDITOR DATABASE Lock databse with View Lock option is misleading! g& C5 Y% X; w: b3 `# p
1160529 SCM SCHGEN Schematic generation stopped because the tool was unable to create an appropriate internal symbol structure 9 N* z9 W2 U2 G2 A. B1160537 SPIF OTHER Cannot start PCB Router/ f) `$ _" I2 Q! O. ^% n8 V# q- k
1161363 ALLEGRO_EDITOR SYMBOL Getting error SPMHGE-73 when trying to mirror symbol' `( e6 J" [* `! b' b
1161781 CONSTRAINT_MGR CONCEPT_HDL SigXp crash when selecting ECset in design% ?- h) D% G* {6 p6 e2 ~9 Y
1161896 ALLEGRO_EDITOR DRAFTING Tolerance value added for Dimensions is not working correctly (HF11-12) 6 d k" B2 L( |4 p9 C, ^" i+ z1162193 SIP_LAYOUT DIE_ABSTRACT_IF shapes in dia file not linked to the die after edit co-design die _& y7 ^, P- q6 s0 u
1162754 APD VIA_STRUCTURE Replace Via Structure command selecting dummy nets. . p' P& k2 ~5 ?# I% G; H & S8 O% c9 S/ |/ a- Q/ r4 UDATE: 06-28-2013 HOTFIX VERSION: 0120 Q- i& a) j% I) r7 W$ c. @
=================================================================================================================================== 4 p3 J4 h2 d# k3 V( v& K( GCCRID PRODUCT PRODUCTLEVEL2 TITLE% y) i0 F/ ?; o
=================================================================================================================================== / ?& A6 c V/ b7 q7 i6 d0 P* `' R914562 ALLEGRO_EDITOR GRAPHICS 3D viewer, PCB Symbol view in DRA needs to be same as in BRD" [5 O- ?7 P! z: j1 d8 \3 O
1120397 CONCEPT_HDL CREFER CreferHDL attempts to create missing vlog004u.sir files" y+ e* a/ a1 Y& b: G9 F
1136449 ALLEGRO_EDITOR GRAPHICS about previous shape fill display 6 y9 B. U: o" x6 [( v" E1145635 ALLEGRO_EDITOR SHAPE Auto Voding on the same net shapes with other parameter.2 }8 M9 r" [' B( F3 @# g! m8 K8 z- L' T
1150334 ALLEGRO_EDITOR EDIT_ETCH AiDT deletes the clines and turns it back to PLAN line 1 `) f1 A# k! Z" q7 F+ J1151100 APD VIA_STRUCTURE Net filter not working in replace via structure command.9 r9 x! i4 [# ~7 ?% U6 T, \+ }
1151126 APD VIA_STRUCTURE Getting "group is not appropriate at this time" message when using Temp Group.) y, X# q9 G$ ?/ |3 A5 h
1151458 GRE CORE GRE crashes on Plan Spatial# O2 S+ ] T( ?3 o/ E8 Z( u
1151932 F2B PACKAGERXL PXL error when case is wrong at differen levels in hierarchy% U5 i) y9 q/ `! N7 s5 ~% P
1152151 ALLEGRO_EDITOR INTERFACES dxf2a gives error [SPMHGE-268]$ c+ s; w7 q1 h& I3 Y# k
1152475 PSPICE SIMULATOR RPC server unavailable error while simulating the attached design 7 C3 r) W! D1 s5 L" Z2 G7 T9 Z1152737 ALLEGRO_EDITOR SKILL dbids are removed because highlighted objects in setting the xprobe trigger7 k% o; z# v1 f+ N
1153006 ALLEGRO_EDITOR SKILL axlUIWPrint dose no work correctly in allegro PCB Editor 16.6.0 Q+ \+ Q2 k" s( e3 ~+ x' Q6 {
1153279 CONSTRAINT_MGR OTHER Netrev changing design accuracy from 3 to 2 dec places . F0 Q7 K* s% A" I1153461 SIP_LAYOUT DIE_EDITOR Regression problem in 16.6 ISR: Dia Abstract ECO is causing Die Editor Finish to fail 5 T4 S) j% w5 D1 n9 o1154973 APD EDIT_ETCH Same Net "Line to Line" violation occurs even with "Allow DRC's" turned off.: f9 c ] V; O; r
1155227 ALLEGRO_EDITOR DRC_CONSTR via to shape check on the negative layer( ]- q2 I( M9 t5 p) g: ?
1 m) U h! \5 A0 [DATE: 06-14-2013 HOTFIX VERSION: 011 # |" m2 m, w; C$ b# B) V; z4 S=================================================================================================================================== / G- q( K9 Z8 r1 i* {+ o6 yCCRID PRODUCT PRODUCTLEVEL2 TITLE 5 I8 j: S# M& }& j; E=================================================================================================================================== . e* h/ E7 L% m3 _! a9 D9 Y! u982306 CONCEPT_HDL OTHER When plotting a PDF publisher output the page coming out half inch bigger in pdf $ P8 l* X1 Z. |; w a$ r- I& B- k3 O5 n9 _1055338 SIP_LAYOUT DRC_CONSTRAINTS Soldermask to Via drcs on bondfingers3 K0 b- \+ g* n8 M- n
1093375 ALLEGRO_EDITOR PLACEMENT Align Module with Zero spacing value space the modules further away the modules should be nearer9 f3 M" v u4 |- m
1103201 RF_PCB FE_IFF_IMPORT Wrong permissions to map file during IFF import 0 P8 l6 K7 r* W1106900 CONCEPT_HDL COMP_BROWSER Component Browser performance utility should honor CPM directives for include and exclude PPT# @: W8 c4 Z- U G# G/ e
1110178 ALLEGRO_EDITOR EDIT_ETCH Line Width Retention should be controlled via setting& v7 |2 w. B$ E, X |7 `: s
1110323 APD DXF_IF DXF out is offsetting square discrete pads.* W! p3 U7 q0 y
1123581 ALLEGRO_EDITOR MANUFACT Dimension Line gets changed on board 7 R3 |5 W0 Z+ j/ B! A; g( ~1 r1134083 CONCEPT_HDL OTHER Published PDF file's hyperlinks do not work fine when user use double digits partitions for page Border.( l9 _; X/ p M' j# N) q% n* B
1139338 ALLEGRO_EDITOR DRC_CONSTR The total etch length does not seem to work for Xnets after setting the variable "retain_electrical_constraints_on_nets"$ P# w4 r: m0 T
1139361 ALLEGRO_EDITOR DRAFTING Angular dimension tolerance is incorrect when plus minus tolerances are equal. 4 U& R/ f! e$ v% Y+ K1141882 ALLEGRO_EDITOR EDIT_ETCH Allegro Crashes during diffpair slide! l! \- @+ p+ k {- i
1142876 ALLEGRO_EDITOR SHAPE No DRC error when airgap between place bounds exactly zero & D8 z6 |4 d! S; k* a" v% S1145235 CONCEPT_HDL CONSTRAINT_MGR DEHDL CM gives error when trying to launch SigXP7 H; [- |8 H: [$ x
1145243 ALLEGRO_EDITOR NC Duplicate drills found in the NC Drill output - u8 b) [+ ~; Q9 D& i: v1145260 SIP_LAYOUT DIE_EDITOR Enable "Copy" in die editor * D. w& N/ G- g* F; A' q1145284 CONCEPT_HDL CORE Publish PDF crashes DE HDL % g" m% `$ ~1 M; x1145333 ALLEGRO_EDITOR SHAPE SHAPE boundary may not cross itself. Error cannot be fixed. & h) A, L2 B3 o" m3 T0 f4 S' d1145856 ALLEGRO_EDITOR DRC_CONSTR DRC Line to Thru Pin appear while Fillet be added# B+ w. Q; f, B k) [
1146287 PCB_LIBRARIAN CORE PDV expand pins and change origin sets coordinates for few pins wrong and places pins on top of each other after collaps ) J1 n* U) ?- l8 q3 p5 A1146865 ALLEGRO_EDITOR DATABASE Allegro crashes when trying to place mechanical symbol ! F8 Q4 h1 A. o; l* a+ L- u) A1148513 ALLEGRO_EDITOR OTHER Importing a subdrawing file causes incorrect net name assignment. 8 ~* }. }- o2 r: X1148734 CONCEPT_HDL OTHER Logical Symbol Text is turned upside down after extracting PDF by Publish PDF+ V5 f# K. W9 ]- C9 X
1149025 ALLEGRO_EDITOR INTERFACES IPC-2581 imports cross-hatched shapes as solid a9 g% ?8 ]7 w5 s( @: E
1149948 APD OTHER Stream_out hangs on this design -- hang processing merge of overlapping shapes using poly_deletecolinear_only()1 e# ]' y6 T& O2 ]# ^6 W! b W2 D2 C+ e1 o
1150274 CONCEPT_HDL CORE Uprev from 16.3 to 16.6 is not preserving RefDes + G" n6 b$ j! E! S, ^" V7 r8 D! U1151450 SIP_LAYOUT DXF_IF DXF export from CDNSIP missing symbols4 R, j, s% e) {
5 H L" ~0 D9 A! K/ ~4 j' W( FDATE: 05-25-2013 HOTFIX VERSION: 010: N% @* J; y* D8 A B5 E; O
=================================================================================================================================== , J7 y( P ]( S% a8 q# \CCRID PRODUCT PRODUCTLEVEL2 TITLE ! Y1 F6 E6 k- U W3 ~=================================================================================================================================== ( z6 `- o2 h5 _% V: f1084716 ALLEGRO_EDITOR OTHER Getting an MPS error when updating CM from SigXplorer . y9 N! w! G, i! V- e# }: R1111430 FSP CAPTURE_SCHEMATI Auto-resize the schematic sheet so that hierarchical block fits within border " U; G! F1 Q8 ~2 ^, l, W0 G3 R" e2 t1119007 CONCEPT_HDL CORE PDF Publish of schematic creates extremely large PDF files & }6 y0 |2 ]/ M- O. R8 \1121020 FSP MODEL_EDITOR Cut-Paste from Excel causes empty cell in Rule Editor 2 c# B0 [2 Z: S% n1124610 PSPICE SIMULATOR Attached design gives "INTERNAL ERROR -- Overflow" in SPB116.62 j8 T! v! X$ q7 L
1125330 FSP CAPTURE_SCHEMATI FSP generates OrCAD schematics with components (Resistors) outside page border % S4 X6 @8 y$ U! D8 }7 X( ~1131775 ADW LRM LRM error with local libs & TDA * k9 d8 R2 _6 y9 F- f- Y1 R5 z7 X1131868 CONCEPT_HDL CONSTRAINT_MGR Many net-class constraints "fell off" the design after uprev and Import Design of GEP4 K' ]' Y: J$ C! I/ n5 a5 Q
1132080 ALLEGRO_EDITOR PLOTTING Size of the logo changes after File > Import > Logo ' x7 f% }. k7 _7 I" X' J1134956 SPECCTRA HIGHSPEED Route Automatic fails with error when Impedance rules are turned ON in Allegro CM. ) A8 p5 J. W0 J. h1135548 SIP_LAYOUT SHAPE This design shows two areas with shape shorting errors that should not occur5 D3 C& j0 d4 z8 L0 l
1138312 ALLEGRO_EDITOR MANUFACT NCROUTE is not generated for filled rectangle slot ? 5 H" @: T3 j1 H4 y1139433 ALLEGRO_EDITOR GRAPHICS embedded netnames not displayed or getting very small upon panning after exiting 3D Viewer. 8 v$ W5 R) ? @" k7 Y. U1139509 CONCEPT_HDL CORE The LRM update changes npn device to resistor3 L7 A# K" @0 v4 I! j/ F9 a
1140752 ALLEGRO_EDITOR PLACEMENT Moving a place replicate module crashes allegro/ e% `; m6 x4 P9 { @: H7 o" m, Y
1141314 SIP_LAYOUT SYMB_EDIT_APPMOD Design will lock up after changing the border using Edit Boundary in Symbol edior mode. - F* Z3 t! V7 c$ W( @6 [: B7 I1141751 ALLEGRO_EDITOR INTERFACES Allegro Crashes with Export IPC2581.4 B. L: a, ]# W. ]: z2 M' Y
1142478 CONSTRAINT_MGR INTERFACE_MAPPER adding constraint to netgroup causes CM & PCB SI to crash% l0 L: T) K I" m( v& K+ R- P0 @
1142884 ALLEGRO_EDITOR OTHER Boolean type user defined property doesn't export to the PDF) C, [3 q5 O) e5 `+ G' i
1143199 SIP_LAYOUT DIE_EDITOR Enable bump remastering & J7 N& y: G8 _7 ~7 ?9 [1 f1143654 SIP_LAYOUT DIE_EDITOR Add X&Y offset when adding or moving a pin in die editor 2 Q5 c& h6 F. f8 B6 ]: ^- K* K# H4 C1 @( E' {
DATE: 05-9-2013 HOTFIX VERSION: 009 i( h5 {3 x: L9 r5 J, n9 v
===================================================================================================================================% K8 b/ Q# o& Z! u* @
CCRID PRODUCT PRODUCTLEVEL2 TITLE 6 y/ A' ?; p! r7 o, `===================================================================================================================================( X+ h9 y4 L* M/ Q! F9 k2 P4 s
961420 ALLEGRO_EDITOR PLACEMENT Regardless of the aspect ratio for room of side The QuickPlace by room command could be placed comp % H2 O9 m1 X/ I1079862 ALLEGRO_EDITOR SKILL Ability to create IPC2581 layer mapping file by Allegro Skill function- Q5 g( G4 d. Y( y1 A# `
1080734 CONCEPT_HDL CORE Repainting of grid lines during pan or by moving window show as solid white lines instead of gray da: s- I* o6 v; O3 b
1104145 ALLEGRO_EDITOR SCHEM_FTB User defined properties do not appear in PCB 0 w l0 W1 U( b) F9 Y3 l0 I1107547 SCM OTHER v15.5.1 tcl/tk code not recognised in 16.6 - t' z6 J o3 c' e1110209 CONCEPT_HDL OTHER We can move symbols and wires off grid despite the site.cpm grid lock # I( Q, E+ p. ]$ ^7 P- P& [7 J6 x1117825 CONCEPT_HDL OTHER SHOW_CONSOLE_ON_LAUNCH throws an unrecognized directive warning in the schematic editor ' }; c, }1 X o0 w" \) b1118874 ALLEGRO_EDITOR INTERFACES Oblong pad shapes are not shown with correct orientation after DXF export from Allegro6 W, S: z* j1 |" u4 x* [5 _
1121873 ALLEGRO_EDITOR INTERFACE_DESIGN Importing Bundles from Net Groups does not allow any further editing./ ]( `' f) ?* N/ E
1122933 CONCEPT_HDL CORE Newly added Toolbars are getting invisible after re-staring Concepthdl0 u% L& U3 D1 M% \; k
1124587 ALLEGRO_EDITOR INTERACTIV The Shape Expansion/Contraction command should also be available in EE mode.* p* o1 R8 f' U2 B
1125895 SIP_LAYOUT LEFDEF_IF Tool crash while moving the slider in the Filter options Macro tab form of the co-design die library manager" e- ~! x# ?, P2 q& T$ j
1125962 F2B DESIGNVARI Custom Text in Variant Details dialog box is inconsistent+ M6 D H) C. f' N9 s8 I
1126096 SCM REPORTS Two nets missing in report ) E( `/ m6 W B1126134 SIG_INTEGRITY GEOMETRY_EXTRACT Attempting to extract topology hangs APD) q' H& ?( }: s5 N2 h
1126182 ALLEGRO_EDITOR DRC_CONSTR Shape fillet DRC in same net thru via to thru via was removed after update DRC. . J% _" X8 y# P9 b( v1130280 ALLEGRO_EDITOR MANUFACT stream_out command in 16.6 seems hard coded to look for a design called stream_out.brd 6 T. G. X& v" q8 f5 f8 o4 g1130737 F2B PACKAGERXL Error - pxl.exe has stopped working+ n! \' u# U F% P3 d
1131650 ALLEGRO_EDITOR PLOTTING PDF Publisher doesnot display few component defination properties in Property parameters 9 f# k8 w8 ?9 Z* s1131764 ALLEGRO_EDITOR EDIT_ETCH Line segment will not slide using the New Slide. 2 R7 x" {1 L, A2 r1132638 ALLEGRO_EDITOR DFA 'dfa_update' crashes when running the utility on the attached foder. 5 g8 }* i% s* L* _% w2 _1133311 ALLEGRO_EDITOR SKILL ?origin switch is not working correctly with axlTransformObject while rotating shapes % Q' j: I3 V+ P! Z9 p# B/ N: b1 u1133893 SIP_LAYOUT IMPORT_DATA netlist-In Wizard crashes/ t# Z' e4 q4 D9 L& U3 d
4 f0 _/ g7 Q! G% M( o
DATE: 04-26-2013 HOTFIX VERSION: 008! K0 }5 {: l' ?7 |+ h+ j8 Q
=================================================================================================================================== ' Z# X# c1 B9 R1 w8 j5 hCCRID PRODUCT PRODUCTLEVEL2 TITLE0 \. V# C6 Y9 S% m, a) y; O- ~4 C
=================================================================================================================================== / X* ~0 A; W' S- C" Z8 `6 ]876711 ALLEGRO_EDITOR GRAPHICS Mouse wheel will only zoom out using Win7 64 bit$ G4 O/ ^3 w S: S6 i* m
1080386 CONCEPT_HDL CORE Unable to highlight netclass on every schematic page using Global Navigation + X+ W5 g1 Q& K1082587 FSP FPGA_SUPPORT Support of Xilinx's Zync device/ \! Q @. X1 I7 F
1105286 FSP DE-HDL_SCHEMATIC FSP crashes while creating board in Schgen if it does not find any available license.7 f$ i5 O v, ]; Z
1105461 ALLEGRO_EDITOR DRAFTING Dimension Enviroment deletes Diameter symbol whenever we add anything to Text section 0 i5 [* I# {0 A, B, h& z1105504 PCB_LIBRARIAN CORE PDV on Linux Move pins by arrows does not stop when release arrow key but keeps on running8 f( i% C6 g$ N
1110126 ALLEGRO_EDITOR GRAPHICS Display Hole displays strange color. 3 [" n& A* @9 k' q+ U1113518 CIS DESIGN_VARIANT Incorrect Variant information in Variant View Mode for multi-section parts with occurrence 3 ?& h' t% o- [+ f1117580 SCM OTHER DSMAIN-335: Dia file(s) error has occurred.. a7 E% E( r, u5 J/ |
1117845 FSP DE-HDL_SCHEMATIC Schematic Generation fails without a reason' _4 U3 U% P6 g5 s) }7 A
1119864 FSP TERMINATIONS Auto-increment the pin number while mapping terminations. * s) Z1 }9 \0 m) V6 y1120250 ALLEGRO_EDITOR MANUFACT Why is the parameter File altered?$ L' G7 r9 n! a- Q/ N
1120414 ADW LRM TDO Cache design issue , o4 U- z0 V4 X5 ]5 F1121044 SIP_LAYOUT SKILL axlDBAssignNet returns t even when no net name is assigned to via ! Y& t% ?4 f9 F1121148 ALLEGRO_EDITOR PLACEMENT Ratsnests turns off when moving symbols with Net Groups ?9 Y; b4 O% z
1122440 ALLEGRO_EDITOR DATABASE Cannot unlock database using the password used to lock it0 k$ N" M6 K' h
1122449 ALLEGRO_EDITOR DRC_CONSTR Uncoupled length DRC for diff pair shows different actual length value between show element and CM. 1 C# z7 `/ N5 ~4 F% O U/ \0 Q1122990 ALLEGRO_EDITOR INTERACTIV RF PCB Symbol which is part of Reuse Module cannot be replaced, i8 e8 X0 s% Y# \) E" l' X1 Y+ q
1123083 ALLEGRO_EDITOR PLACEMENT Saving after mirroring a Place replicate mdd create a .SAV board file. 6 x5 G: f8 f# i9 Z( l H. ]1123257 SIG_INTEGRITY SIMULATION some of the data signals at the receiver are not simulatable/ l0 N, j4 x, y4 _# C# z
1123764 CONSTRAINT_MGR OTHER Allegro crash while importing DCF file% w; J$ z2 }4 i. d# |0 G$ @2 [
1123816 CAPTURE PART_EDITOR Movement of pin in part editor9 p6 U# ^* p/ |) i5 } [
1124183 ALLEGRO_EDITOR EXTRACT Output from EXTRACTA gets corrupted with refdes 50% E2 y/ I3 v1 X" v" {" {
* T0 i4 E8 u4 {6 D4 b# ]DATE: 04-13-2013 HOTFIX VERSION: 007 0 z3 U; O: x% Y& q; ^===================================================================================================================================, U" D- y. H0 G6 B# Y( \
CCRID PRODUCT PRODUCTLEVEL2 TITLE, x3 ]9 t1 ^# Y* S
===================================================================================================================================6 }6 x0 G# f9 e3 B' e& E/ n8 Q
1107397 SIP_LAYOUT PLACEMENT Place Manual-H rotates die " Q* |1 I& \( R1111184 ALLEGRO_EDITOR PLACEMENT NO_SWAP_PIN property does not work in 16.6 - D4 d8 x5 H3 e c. a0 H1112295 APD DXF_IF Padstacks� offset Y cannot be caught by DXF.5 q$ q, L2 g% M. Q1 s
1113284 ALLEGRO_EDITOR INTERFACE_DESIGN Rats disappear after moving components) i1 o7 A% l m+ h5 v+ }! `
1113317 CONCEPT_HDL SKILL skill code to traverse design not working properly , u; {3 z7 c" I' v* U2 e: v1115491 ALLEGRO_EDITOR SKILL telskill freezes command window " p# r. o4 p2 g" O3 x6 c6 _1115625 ALLEGRO_EDITOR SKILL Design extents corrupted when axlTrigger is used.) t( h7 ~% B0 y' w% S: W; ^
1115708 ALLEGRO_EDITOR INTERFACES Export DXF is outputting corrupt data on one layer.* G+ p0 z3 w0 _: h6 L9 |
1115850 ALLEGRO_EDITOR GRAPHICS Text edit makes infinite cursor disappear + F1 y& X7 M/ ?* g. Q1116530 ALLEGRO_EDITOR MANUFACT Import artwork show missing padstacks 9 v' m( K$ d4 @1117498 ALLEGRO_EDITOR DATABASE Why does dbstat flag LOCKED? . \& c5 L9 [. i, _& x1118407 SIP_LAYOUT DIE_EDITOR net connectivity is getting lost when running die abstract refresh; g; U" u& _7 U4 ?
1118413 SIP_LAYOUT DIE_EDITOR pin number is getting changed when running die abstract refresh6 A9 T* ]0 _* g' \8 o) W. C8 f
1118526 CONCEPT_HDL CONSTRAINT_MGR Upreved design now has Constraint packaging errors' F) J2 o5 s; A$ X/ s/ J4 ], E
1118830 ALLEGRO_EDITOR SHAPE Performance issue when moving/refreshing shapes in 16.6 ! H* n F* K4 J1119784 ALLEGRO_EDITOR INTERACTIV ipickx command gives drawing extent error inconsistently! e; a' @7 O. z0 ^6 Q! R
1120469 SIP_LAYOUT DIE_ABSTRACT_IF use different padstack for different, but look-alike bumps5 P l6 e9 L# o- Y
1120669 CONCEPT_HDL CORE DEHDL crash on multiple replace of hier blocks5 @5 `( D0 c1 j8 l
1120810 ALLEGRO_EDITOR EDIT_ETCH Cannot slide cline segment. 8 b+ ^, }5 H) i; w1 l& }3 l N' E: G, S
DATE: 03-29-2013 HOTFIX VERSION: 006: ^3 p9 T l: n5 C* W; E. d
=================================================================================================================================== ; M7 J2 L: D4 N' SCCRID PRODUCT PRODUCTLEVEL2 TITLE( C( \+ @# [. X: ?
===================================================================================================================================: h7 V+ ~; y( |8 ~$ U: H
625821 CONCEPT_HDL CORE publishpdf from command line doen not work if temp directory does not exist./ ]+ D; G' N# J% E% R% s
642837 PSPICE SIMULATOR Option to disable Bias Points when Primary Analysis in Active Simulation Profile is DC Sweep) M R: H. O0 y9 p7 R
650578 ALLEGRO_EDITOR SHAPE Allegro should do void only selected Shape without "Update Shape".. P$ q+ I. \2 u7 y+ r8 W
653835 ALLEGRO_EDITOR MANUFACT Double character drill code overlaps with "cross" in NC drill legend ! q3 z/ x; `) |% b, |687170 SIP_LAYOUT DRC_CONSTRAINTS Shape to Route Keepout spacing DRC display incorrect / }+ k8 a' E( c, }1 Y5 U9 `787041 FSP DE-HDL_SCHEMATIC FSP Refdes inconsistency when gen schematics5 i0 X8 I& N2 @' J v: _0 K
825813 CONCEPT_HDL CORE HDL crashes when copying a property from one H block to other7 U6 V9 z/ r0 H9 [; f! L5 `1 i& S
834211 ALLEGRO_EDITOR SHAPE Constant tweaking of shape oversize values is time consuming* i3 O9 B' q; H! T9 m9 Z) r5 A
835944 ALLEGRO_EDITOR OTHER Customer want to change for Jumper symbol by other Alt symbol.( @& s+ D. _3 Y# T6 C/ ]9 X# }# h) y/ o
868981 SCM SETUP SCM responds slow when trying to browse signal integrity ) \8 W$ B# [3 a/ n: Y871899 CONCEPT_HDL CORE 'Multiple:' column of Grid window in DE-HDL option is too wide' K8 r( Z3 z. W6 O- \1 x
873917 CONCEPT_HDL CORE Markers dialog is not refreshed8 {# A4 ~; Q* l0 r5 F( X& n
887887 CONCEPT_HDL CORE Option to find unconnected Pins/Nets with DEHDL L License: J* D P5 g7 M; j5 G0 P" p
888290 APD DIE_GENERATOR Die Generation Improvement& z2 B; ]% p7 g
892857 CONCEPT_HDL CORE packager treats R? as a unique reference designator1 C; q# z i' q5 m! ^: B
902908 PSPICE SIMULATOR Support of CSHUNT Option in Pspice 4 V; n3 y* w+ F% k( g908254 ALLEGRO_EDITOR INTERACTIV Enhancement request for DRC marker to have a link to CM % k1 t. ^) d' M4 C* @! I, a3 D922422 CAPTURE NETLIST_ALLEGRO Netlist errors when using mix of convert and normal symbols* k8 x+ m! a6 Q6 z. s( l
923361 ALLEGRO_EDITOR INTERACTIV Stop writting PATH variables in env file if no modifications are done using User Preferences8 x9 S- t. z7 U. y4 @! Z+ P
935155 CAPTURE DRC No any warning messages listed in the On line DRC window even executed "Check & Save" to on line DRC ! f _# g8 y( t1 Q3 c945393 FSP OTHER group contigous pin support enhancement3 Q/ M0 r9 X8 u* z5 v7 ?8 m
969342 ALLEGRO_EDITOR DATABASE Enhanced password security for Allegro database 8 e7 d& U* p- p& h4 p5 A+ y( O1005078 CAPTURE ANNOTATE Copy paste operation does not fill the missing refdes _- X l R! L! k; ?# f
1005812 F2B BOM bomhdl fails on bigger SCM Projects , H( H$ l, C. }) i1010988 CAPTURE OPTIONS ENH: ADD ISO 8601 Date Time format to Capture! m) v0 d! P5 c" f
1011325 ALLEGRO_EDITOR PLACEMENT Placement replication creates modules with duplicate names4 e! C3 M$ h' s$ F' U5 p$ n
1016640 ALLEGRO_EDITOR PLACEMENT Error/Warning Message for not finding or unmatched mechanical symbol or fiducials or which are not on a net ; ^' p; ` e1 [9 N1018756 CONCEPT_HDL CONSTRAINT_MGR Match Groups with Pin Pairs are not getting imported into the schematic CM during Import Physical & A% P5 @( t+ b& T: i1032387 FSP OTHER Pointer to set Mapping file for project based library.9 o1 } Q$ O6 @3 K: f- Z; z5 g
1032609 FSP IMPORT_CONSTRAIN Import qsf into FSP fails with 縋LL PLL_3 does not exist in device instance� " O8 y! z- \6 t; U/ Q* i( U1040678 ALLEGRO_EDITOR MANUFACT Text spacing is inconsistant for top and bottom SM layer in xsection chart( j! {# n. a' J3 W+ i# `
1042025 APD WIREBOND Order placement of power rings for power/ground rings generation with using Perform Auto Bonding 7 ~; z; E% q% [7 B1045500 CONCEPT_HDL CORE Why Search results does not display the correct Physical Pages. 2 n* B- n* Q) _+ H" `% y) N- e( e1047259 CIS EXPLORER Sorting in CIS Explorer is not Numeric even for columns which are of Numeric data type9 c8 a: R, ^! J! g0 {
1047756 CAPTURE NETLISTS Not adding user defined properties in netlist generated by orDump.dll % @' d. {5 ^1 s! w1052455 RF_PCB DISCRETE_LIBX_2A RFPCB IFF Export to fix port direction for ADS for footprint having the same pin rotation + g; t" G0 `- v1054314 CONCEPT_HDL CORE Zoom of custom text is different from other schematic objects ) O% f8 O6 f+ \$ ~) R1 M1061529 CONCEPT_HDL CORE Space can be included in LOCATION value and cannot be checked by checkplus : e- R/ U2 c, b1064035 CONCEPT_HDL COMP_BROWSER Component Browser crashes on part number search using a library containing >23K parts5 B/ ?, x5 O, ?0 a" O7 T
1064604 ALLEGRO_EDITOR MANUFACT Enh - Include ability to add slot notes to designs 0 _4 v$ s* k& ^; Q1065636 CONCEPT_HDL OTHER Text not visible in published pdf8 f B3 b. @* i7 b% v8 A5 M% p4 ^
1065843 CIS PART_MANAGER time stamp on library from different time zones triggers part manager lib out of date warnings ' K7 e* ?3 h4 B4 v8 D+ C1066701 ALLEGRO_EDITOR OTHER Missing padstack warnings not in Symbol refresh log summary: P! H3 A& h, k2 a/ c! V$ O/ C+ K
1067283 SCM PACKAGER ALLOW_CONN_SWAP does not work for lower level schematic parts1 L2 Y4 c8 c( f3 K1 \0 X
1067400 CONCEPT_HDL CORE ERROR(SPCOCD-171): Port exists in symbol but not in the schematic 1 a. Y+ m+ a U' K# B$ F1068878 CONCEPT_HDL CORE Rotating symbol causes the pin name to be upside down% R1 L( L: \+ }* P7 d
1069896 ALLEGRO_EDITOR EDIT_ETCH Cline changes to arc when routing even when Line lock is set to Line 45 6 ` i( g2 h% s( Z% d& C1070465 CONCEPT_HDL CORE Why does ConceptHDL crash on renaming a Port Signal5 f0 U3 s7 u9 f) H. f% P
1071037 PSPICE SIMULATOR Provide option to disable Index Files Time Stamp Check' a7 o" p x5 [9 Y
1072311 CONCEPT_HDL OTHER Schematics are incorrect after importing design. 9 G8 v- K. S6 A: t, h1072691 CONCEPT_HDL CORE Customer has the crash from Run Script of DE-HDL 16.51 again(#3) 2 F0 e) P; W% f7 @% U: ^1072859 SIP_LAYOUT DIE_EDITOR padstack selection window crash from Die Editing: Component editing of Co-Design Die 2 `9 p% d$ |# w1073354 CONCEPT_HDL CORE Bubble defined on symbol pin is not visible on the schematic " ], n2 k6 b: ~/ H7 u3 N1073837 ALLEGRO_EDITOR GRAPHICS Some objects disappear on ZoomIn ZoomOut & {) v8 M8 o, ?& l1074243 ALLEGRO_EDITOR GRAPHICS Allegro WorldView window does not always refresh after dehighlight of objects( A- g1 P( l, c* P# c7 S) }
1074606 ALLEGRO_EDITOR INTERACTIV Enh - Cosmetic change in Filter Option UI of Replace padstack to indicate multiple pin entry format+ o" r5 [& w/ `+ \0 w _
1074794 ALLEGRO_EDITOR REPORTS add commonly reguested via reports to Allegro and ICP reports. Via per net, via per layer per net # ~& i( W; q7 B8 N) E2 B* t1075587 CONCEPT_HDL PAGE_MGMT Unable to insert page in schematic 2 |+ z7 j/ h" z9 Y, ]1 }. n8 |1076117 PSPICE PROBE Copy & Paste text/label in probe window changes font size and later gets invisible 9 x9 C# ^' G0 f' l ^1076145 SIP_LAYOUT DIE_ABSTRACT_IF Issue message in Add Codesign and Refresh Die Abstract if Pin Numbers from Die Abstract exceed 31 chars.. m- J; _( B' Y0 i2 ]; Q; Z( C
1076566 ALLEGRO_EDITOR EDIT_ETCH Sliding diff pair cline that has a min/max prop rule displays the HUD meter inconsistently.; H: o0 B: p7 ]3 }
1076604 ALLEGRO_EDITOR SHAPE Sliding via in pad corrupts surrounding shape and generates false DRC Errors1 k/ C8 h1 r N, W# v
1076820 SPECCTRA FANOUT Fanout fails to stack vias in bga pads. , M- {8 e0 {5 \4 B3 h, ?1 r1076868 ALLEGRO_EDITOR PARTITION Symbols become 'read only' inside a design partition9 C$ h( f- _, a
1076879 GRE IFP_INTERACTIVE Plan Column should not be present in Visibility tab for Symbol Editor/ ]. ~* c; A7 g4 F
1076898 CONCEPT_HDL CORE User can not increase logic grid size value continuously using Up button on Design Entry HDL Options 1 k: n/ Z9 T# R9 ?8 ]1077026 CIS LINK_DATABASE_PA fonts changes while linking db part in 16.5& Q* T! A* f6 q, l0 A
1077187 ALLEGRO_EDITOR DATABASE DBDoctor appears to fix database but nothing is listed in the log file.; U/ @- Y* S+ a" `
1077527 CONCEPT_HDL CORE ConceptHDL net with name U cannot be found using Global navigate % g+ N6 w/ d9 t; E1077621 CONCEPT_HDL CORE DEHDL crashes when saving page 3 2 d5 I% l: h! X2 _1078270 SCM UI Physical net is not unique or not valid2 l) J5 Z# c6 {5 c n% g
1079616 CONSTRAINT_MGR CONCEPT_HDL Packager error in 16.5 which is resolved when system is re-booted 1 p7 X P; G x8 |6 P0 o1079821 CONCEPT_HDL CORE Project Setup does not respect $TEMP variable for temp_dir and creates a directory in project calle 5 R/ L8 X: R$ X1 x) J2 r) i1080142 CIS CONFIGURATION peated entries in Allowed Part Ref Prefs1 \$ W2 U p p. B
1080207 ALLEGRO_EDITOR INTERACTIV Separate the 2 types of SOV violations."Segments over voids & Segments with missing plane coverage". k7 k' n9 K! b1 R2 D" O: C
1080261 PSPICE SIMULATOR Encryption support for lines longer than 125 characters $ u( S0 W8 a" c" h1080336 CONCEPT_HDL CORE Backannotation error message ehnancement . y) G$ E( t# Q1 ?: j1081001 ALLEGRO_EDITOR PLACEMENT Package boundary is not visible while manually placing a component when using OrCAD license * h# g9 g8 e5 J* Q( ] c) m1081237 ALLEGRO_EDITOR PLACEMENT Place replicate > apply does not apply component pin properties stored in .mdd1 l. Q" h8 L/ V* O
1081284 MODEL_INTEGRIT TRANSLATION Space in the file path will create a bogus error 6 U/ L/ @7 t! g1081346 ALLEGRO_EDITOR INTERACTIV With Place manual, rotation of the symbol is not updated. % Z% E9 ^& p" U& [/ [2 u' Q' h1081760 FSP CONFIG_SETTINGS Content of 縁PGA Input/Output Onchip termination� columns resets after update csv command / {9 Z8 M6 t0 `' f4 z1082220 FLOWS OTHER Error SPCOCV-353 - O* N# g, p4 a i* v1082492 ALLEGRO_EDITOR PLACEMENT Place replicate create does not highlight symbols.$ k' a E$ J: b Z# J* [ r2 o n$ e% ]
1082676 ALLEGRO_EDITOR EDIT_ETCH HUD meter doesnot display while sliding / add command . f; H' t+ p& x- q# Z1082737 CAPTURE GENERAL The 緼rea select� icon shows wrong icon in Capture canvas.: y! `. |. S4 Q. g& {
1082739 CAPTURE OTHER The product choices dialogue box shows incorrect name7 f/ Y, c1 P6 V" W' j4 d
1082785 CONCEPT_HDL CORE DE HDL should clean the design with non sync properties in some automated way9 |# C8 t# O9 y( [3 A3 _" B- M8 Y0 E" ?
1083761 CONCEPT_HDL OTHER AGND text missing from PDF Publisher) b# J9 j. A2 S6 z0 h
1083964 CONCEPT_HDL OTHER Do not display Value and other attributes on variant parts which are DNI : ^% |. @: {7 h! f$ _$ G6 ]1084023 PSPICE MODELEDITOR Model Editor is slow/unresponsive while opening a Model by double-clicking on .lib file B3 P& F" Q) w% l1084178 ALLEGRO_EDITOR SHAPE Spike create on dynamic void. + S' }4 x I. X7 ~1084637 ALLEGRO_EDITOR INTERACTIV Enhancement: Pick dialog should automatically be set to enter coordinates 6 V% a! b2 p+ `% Q0 b1 w1085010 CONCEPT_HDL CREFER Crefer crashes if the property value in the dcf file has more than 255 characters: a: t7 r8 T, u% ^/ X2 ~
1085347 CAPTURE SCHEMATIC_EDITOR Replace cache results is loss of net graphic changes. % n9 p/ z+ \ U, p+ v- n1085522 ALLEGRO_EDITOR INTERACTIV Allegro add angle to Display->Measure results 7 U+ ~' B( _* F+ {$ t: J$ w3 n1085791 CONCEPT_HDL CORE Publish PDF can not output Constraint Manager properties into PDF file. : v( v& m) X2 Q" r$ E' m4 s y3 |1085891 ALLEGRO_EDITOR INTERACTIV about DRC update* b2 P! A1 _) E3 k4 h3 v
1085990 CAPTURE DRC B1: "ERROR(ORCAP-2207) Check Bus Width Mismatch" should be INFO # Q9 c0 N" K: ? S G. C. J6 j J1086514 CONCEPT_HDL COMP_BROWSER Component Browser placement restrictions not working8 t+ z, v' r4 g# Z
1086576 CONCEPT_HDL CHECKPLUS CheckPlus hangs when running Graphic rules.3 t2 g$ [4 T% k C3 ^6 s7 ?, P
1086671 PSPICE SIMULATOR SPB16.6 pspice crashes with attached design " U/ _+ c, D( f1086749 ALLEGRO_EDITOR MENTOR mbs2brd: DEFAULT_NET_TYPE rule is not translated $ M! H; h/ J; Y; G2 S1086886 CAPTURE PROPERTY_EDITOR "Is No Connect" check box in property editor doesn't work for power pins # L) h! B6 z2 ~; n, m) K- R1086902 CONCEPT_HDL INFRA Problems occurred while loading design connectivity . v- r( O C7 c& @1 F2 g1086937 PSPICE ENVIRONMENT PSpice Color map getting doubled leading to crash after colors are modified number of times. 6 l: P: n' o2 j9 ^' u% W1087221 CONCEPT_HDL OTHER Part manager could not update any parts. 8 \6 z- }: k& o8 t C1 q2 r1087223 CAPTURE CROSSREF Cross Probing issue when login into system with user name containing white space ( J! S5 a: m6 K0 t7 o1087295 SIP_LAYOUT EXPORT_DATA Enable "Package Overlay File for IC" for concurrent co-design dies too ; z( W, W; h9 G% H, R1087658 CAPTURE PRINT/PLOT/OUTPU Lower level design pages are getting print twice0 v; R4 |% k* d7 \; W0 d6 P7 q( b1 i
1088231 F2B PACKAGERXL Design fails to package in 16.5 1 T1 y: g% n& E9 B# @1088252 CONCEPT_HDL CORE Menu commands grayed out after Save (with 16.5-s035) when launched from ASA.4 H- m; h$ i5 j; m- y5 V& H
1088606 ALLEGRO_EDITOR INTERACTIV Pin Number field do not support Pin Range for Symbol Editor ) t+ h* ?8 v) ]$ \: O: G, j1088983 CONSTRAINT_MGR CONCEPT_HDL Units resolution changed in 16.6 Constraint Manager + w8 c1 U( P0 A1 d9 M& Q: X1089017 ALLEGRO_EDITOR SHAPE What is the cause of the shape not filling?7 f) L0 l/ b4 u
1089259 SCM IMPORTS Cannot import block into ASA design3 k4 m4 K2 g; P# F3 k
1089356 SIP_LAYOUT DIE_EDITOR Distributed co-design : launching die editor taking more than an hour to bring up edit form 7 C9 I8 x- ?( {" k: B1089362 PSPICE STABILITY Pspice crash on pspice > view simulation result on attached project# U7 b$ M( [$ d6 W
1089368 SCM OTHER Can't do Save - cp: cannot stat ... No such file or directory9 U9 }+ ~/ _2 i9 Y. B. L, K
1089605 CONCEPT_HDL CONSTRAINT_MGR Power net missing from the CM opened from DEHDL Schematic editor. J0 Y; h3 y+ \% E: j# R; K2 z1090068 ALLEGRO_EDITOR SHAPE shape priority issue in SPB165 ( D. ^7 p" y2 `1090125 ALLEGRO_EDITOR DATABASE Q- The rename resequence log file is not giving correct message. 4 h( R% g' p8 B: |: }2 R2 E1090181 GRE CORE AiDT fails for the nets with errors SPGRE-21 & SPGRE-22 x x, D7 R& W: K, r
1090930 CONSTRAINT_MGR CONCEPT_HDL DEHDL-CM does not retain customized worksheet.% T" e' Y6 B: X Y4 w/ F* v
1091335 CONCEPT_HDL OTHER Color change cannot remain in some situation.1 i4 Q6 E3 R+ `! \; v" @' `- _
1091347 CAPTURE TCL_INTERFACE The Project New link on Start Page doesn't work when Journaling is enabled - H( r! d' |$ S/ j# ~0 _1091359 CAPTURE GENERAL Toolbar Customization missing description 9 ^% a$ G6 ?: H1091662 CONCEPT_HDL CORE Incorrect behavior with the SHOW_PNN_SIGNAME directive+ Y- O$ X) D9 o* Z
1091714 CAPTURE PART_EDITOR More than one icons gets selected in part editor at the same time , @0 G6 t8 I) v h* d1092411 CONSTRAINT_MGR INTERACTIV In v16.6 CM multiple net name selection under net column is not working as in v16.5# q, n! V+ x5 u- f0 j0 I
1092426 CONCEPT_HDL CORE Getting ERROR(SPCOCN-1993) while saving a Hierarchical Design 6 N$ j( U7 A3 ^7 U. `6 o" G1092874 CONCEPT_HDL CORE DEHDL wire short during move not detected with check enabled " p6 q' L: }% t }/ P$ A1092882 ALLEGRO_EDITOR EDIT_ETCH AICC should be removed from orcad PCB Designers design parameters 5 l6 U8 A& {8 W# |) `: j0 v" Y1092918 CAPTURE GENERATE_PART Generate part functionality gives no/misleading information in sesison log in case of error : {! b' O9 _, ]3 c* y: ]0 ]1092933 CONCEPT_HDL OTHER PDF Publisher saves the pdf generated in the previous project folder R6 m8 }. k9 r5 ]% e1093327 CONCEPT_HDL OTHER Getting error SPCODD � 369 Unable to load physical part in variant editor 2 z- B0 _4 d9 _" [& n/ l1093391 CONSTRAINT_MGR OTHER Setup > Constraints > (domain), doesn't open correct worksheet with OrCAD PCB Editor Professional license. ( ?" Y# J6 @* K* }% z1093886 SPECCTRA HIGHSPEED Pin delay does not work in PCB Router when specified in time $ o, y7 t% c8 w9 y% M1 \. ?1094223 CAPTURE PROPERTY_EDITOR CTRL+S does not work in Property Editor but RMB > Save./ |0 W! z0 N$ W6 n% z
1094513 CONCEPT_HDL CORE How to display $PNN for which SIG_NAME is not visible? 1 L/ E' Z7 t) V% T2 E8 B' b1094611 CAPTURE PROPERTY_EDITOR E1: 'Tools->Update Properties' should list parts which are present in .UPD, but not schematic # _3 j6 \! y! v8 ]- A1094618 CONCEPT_HDL INFRA Unable to uprev the design in 16.5, [* L9 g$ k& ~; w8 n5 f& v
1094867 CONCEPT_HDL CORE Page Up / Down Keys are hard-coded assigned to Next /Previous Sheet 5 V' n' l) _3 a- ?8 f1095449 SIP_LAYOUT LOGIC Allow netlist-in wizard to work on a co-design die O" p/ q6 Z1 H* X. k1095701 CONCEPT_HDL CORE Replace part in replicated block only preserves the Refdes in 1st instance of the replicated block " U0 j- X* ~: u' W$ _- ^1095705 CONCEPT_HDL CREFER Cref_to_list not updated on repl icated blocks in 16.5 release worked fine in 16.3 6 F; |' M9 Z% {( G; F6 s1095861 F2B BOM Using Upper-case Input produces incorrect BOM results% |! B0 X, z3 d4 C3 y7 |
1096318 ALLEGRO_EDITOR INTERFACES IDF import not removing MCAD tagged objects during import3 k- w& Q( i( M8 H
1097241 CONCEPT_HDL CORE Concepthdl - zoom in to first object in Find result automatically+ ]& s" b: T! b) q9 H0 e
1097468 ALLEGRO_EDITOR INTERACTIV Need ability to hilight and assign color to vias6 B" o& W/ A* _% [( e, C) U4 N
1097675 CAPTURE ANNOTATE Enhancement:Option to have Incremental reference Update to be checked at all times when we click on Tool>Annotate6 r5 }6 X- y1 X! G6 v i( z1 O9 e* c$ w2 @1 v
1099151 SIG_INTEGRITY SIMULATION All Neighbor crosstalk numbers reported when there are no aggressors 9 v2 P6 w) `! ]: c% }0 C3 U3 r1099175 CONCEPT_HDL CORE CPM directive that enables the Command Console Window in DE-HDL9 {# n, V4 J' ?: Y" c9 x
1099838 CAPTURE TCL_INTERFACE TCL library correction utility is not working correctly.; o9 U, U5 |+ y+ c8 q
1099903 ALLEGRO_EDITOR PLACEMENT Mirror and rotating component places component mirror side' A( z! A8 X1 c! g& D, h$ i1 U
1099941 ALLEGRO_EDITOR PLACEMENT Problem in rotating bottom components when using Place Manual or place manual -h command# S: P) Q. r4 e+ ]+ @4 f9 o
1099998 CONCEPT_HDL CHECKPLUS CheckPlus marker file not locating signal when signal name includes the # character.* o6 e: s2 r3 |7 Y* L
1100018 CONCEPT_HDL COPY_PROJECT CopyProject gives errors about locked directives( P. i0 x @5 x9 o0 Y
1100449 ALLEGRO_EDITOR ARTWORK Pad with Net_short property and shorted to shape supressed wrongly with Pad Supression in Artwork % c: |; w4 H: B% p4 S1100758 CAPTURE LIBRARY Import properties does not update pin numbers of multi section parts# [& ]! A* v( b4 a' Y1 R: T, z
1101009 CONCEPT_HDL CORE Cursor stays as arrow after performing File > Save Hierarchy 0 b& t; [4 G6 W$ T6 S1101497 ALLEGRO_EDITOR UI_FORMS Allegro PCB Editor crashes using attached script when working with RF PCB Clearances.7 q/ A$ J! S' R+ R A
1101813 SIP_LAYOUT DIE_ABSTRACT_IF Support die abstract properties 5 w( Y0 w* f4 l1102531 ALLEGRO_EDITOR GRAPHICS Allegro graphics distortion infinite cursor 16.6 2 J8 R- o9 k# s6 T; ~3 R8 B8 ]3 h1102623 ALLEGRO_EDITOR SHAPE Strange void around the pad # d0 }3 n! d9 P$ g' o: @1103246 FSP FPGA_SUPPORT New FPGA request - Arria V - 5AGXMA1D6F31 - IN2P3! U/ \; P$ w1 a- d" f) @
1103631 MODEL_INTEGRIT OTHER Model Integrity license when using orcad 7 l* D* q) L8 C* G7 |% p1103703 F2B DESIGNSYNC Toolcrash with Design Differences7 L( y2 z2 Z7 l' U
1103712 CONCEPT_HDL COPY_PROJECT Copy Project crashes on customer design attempting to update symbol view % i, g7 V" I" s4 W# B% I, ]$ V1104068 CAPTURE DRC "Check single node connection" DRC gets reset in 16.6 , i0 Q2 V% o. O4 V# g/ o9 w1104121 PSPICE AA_OPT 縋arameter Selection� window not showing all the components : on WinXP 5 g: L! l1 y+ f& B9 R; i1104575 CONCEPT_HDL CORE Allign does not allign offgrid symbols correctly ( R& l8 I" T4 V. Z1104727 CONSTRAINT_MGR SCM Net Group created in sip does not transfer to SCM- o8 ~) v# L2 ?& u
1105128 CONSTRAINT_MGR DATABASE Import dcf does not clear out user defined schedule." t6 U! _( o) @/ m
1105195 SIP_LAYOUT WIREBOND Request that Tack points default to a "fixed" position after Generate Bond Wires.6 o% A/ X. z" k3 e: t F4 x" p
1105249 ALLEGRO_EDITOR OTHER PDF out--- component user defined prop doesn't list the prop selection form 8 a; U% z! K W1 h7 K1 M# u1105443 PSPICE AA_OPT Parameter selection window in optimizer does not list param part, l3 ^) P( \6 Q$ Y* S. `& [* F
1105818 ALLEGRO_EDITOR INTERACTIV Menu-items seperators are clickable and menu goes away when clicked - c1 p, ~, U& L; z% S' u1105822 ALLEGRO_EDITOR SCHEM_FTB Netrev failing with compact pin syntax # M1 S! m# D6 }- }9 N: S. M1105993 SIP_LAYOUT LOGIC Import netlist no longer works with co-design die in SiP 16.6 1 Y& r6 [* x% b1106332 SIP_LAYOUT OTHER sprintf for axlSpreadsheetDefineCell writes characters in upper case only 1 I( i1 L2 a, D* B% s1106786 CAPTURE SCHEMATICS Bug: Pointer snap to grid # E6 Z$ d8 S' l4 D/ M0 J+ }1107132 FSP OTHER Altera ArriaV (5AGXMA5GF31C4) support. 3 r6 [0 J6 ]! B* c/ m- R% n3 n' c4 ]1107151 ALLEGRO_EDITOR ARTWORK Shape filling removed when changing artwork format to RS274X in Global Dynamic Param" L$ u- i. g7 o4 J* O3 S& a
1107237 SIP_LAYOUT WIZARDS Updating a Die using the Die Text In Wizard will error out and not finish! N1 G) Z/ q7 N
1107371 ADW COMPONENT_BROWSE ADW preset Warning filter is spelt incorrectly. (Wraning)." Z- ]: P- i$ S- V, K4 x, K, R
1107599 CAPTURE STABILITY Capture 16.6 crash when trying to invoke' | l9 z8 n- \- e1 }
1108118 ALLEGRO_EDITOR OTHER PDF Publisher pad rotation messed up with flashed pad.) R% U# I/ T5 S: k2 O! a5 p
1108574 ADW COMPONENT_BROWSE LifecycleStatus functionality does not work when in Metadata mode. Work correctly in PPT Mode x: f3 d9 t2 p4 i: |0 F, R6 K; S1109095 SIP_LAYOUT WIREBOND Bondfinger move in hug mode create drcs& ~$ O# a! r5 L
1109113 ALLEGRO_EDITOR DATABASE Allegro Netrev crash with SPB 16.61 K0 G* Z% M7 F1 |. ~0 ?
1109622 SIP_LAYOUT DATABASE In a wirebond design, the ratsnests with 'Closest Endpoint' should not point to the die pins./ ?3 ?4 x" v3 B, `1 j- z/ Q B
1110077 ALLEGRO_EDITOR DRC_CONSTR Duplicate Drill Hole DRC's are not shown for Pins overlapped in same symbol unless "Min metal to metal" DRC is turned ON" [/ Z9 \/ v, B4 j6 |- {: T
1110256 ALLEGRO_EDITOR SHAPE Auto void on dynamic shape is not correct in 16.6$ T* B" J3 v+ o
1110264 RF_PCB FE_IFF_IMPORT IFF Import in DEHDL has component offset : w- ^: a; j7 l0 C: V1111226 ALLEGRO_EDITOR DATABASE Name too long error with Uprev command when output file name exceeds 31 characters 2 B( `/ Q3 T. m, B: V1111234 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figures triangle, hexagon and octagon in NC drill legend- b/ O1 e! x5 ]5 G: q: D6 `
1112431 SIP_LAYOUT COLOR Frequent crash while working with latest version of CDNSIP ( O4 D$ U$ n$ x2 l$ ~1 j1112493 ALLEGRO_EDITOR DATABASE Customer does not like 16.6 Ratsnest points Closest Endpoint& j$ B8 u1 c6 S6 S4 m, Q
1112774 GRE CORE Allegro GRE not able to commit plan after topological plan/ [- D8 J% A& x; o( s; ?% J
1113908 ALLEGRO_EDITOR COLOR Dehilight command fails to remove highlight pattern on a cline, without removing net custom color. 1 t$ m4 Z; Q$ s8 B. I% V1114815 ALLEGRO_EDITOR OTHER Q1: Switchversion error when reading -fa file * @4 A: t* P0 w; {1114994 ALLEGRO_EDITOR DATABASE Getting an error after upreving components to 16.6 r& C$ p7 G \, s& Z) z0 [3 j! f! A- u7 n
DATE: 03-7-2013 HOTFIX VERSION: 005( u$ i1 ?+ e! ^, z1 M
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CCRID PRODUCT PRODUCTLEVEL2 TITLE + q2 Q- M0 D6 M2 }5 t( ]=================================================================================================================================== " N x4 E$ @5 d/ w+ m1067770 IXCOM-COMPILE COVERAGE Assertion failed: file ../covToggleCoverageXform.cpp, line 1102 ' }9 B% W Q b' m6 j" L: L3 z( h1100442 ALLEGRO_EDITOR PLACEMENT Placement queue shows components whichs are already placed# Y2 f3 {9 ?1 y4 f+ B
1101555 ALLEGRO_EDITOR DATABASE Allegro Crash frequently: e/ d6 [9 s. D$ k# O8 Y, P
1104011 ALLEGRO_EDITOR DATABASE Place replicate move group of a modules leaves traces behind2 ], ?" M4 r* f; } p& ]
1104065 SCM NETLISTER SCM 16.6 has problem generating Verilog with existing sym_1 view $ O0 u2 r+ `% [+ O3 t1104605 F2B PACKAGERXL Pins of function swapped part in block not displayed + d% {/ | j( J) v7 b+ i7 H1104790 SCM IMPORTS Corrupt data once SiP file is imported into SCM # } B4 a0 n9 q; ] ]1105066 APD IMPORT_DATA Import NA2 worked in 16.5 "035" but fails in 037 and 16.62 V Z% S6 R T9 G: P8 z) Q( v
1106323 ALLEGRO_EDITOR PLACEMENT Unable to locate specific placed symbol on this board as it becomes invisible after placement. / W+ K) {' g3 R$ Z/ Z( n7 j1108032 CONCEPT_HDL CORE 'Find' option does not list all Components in the Design / f' j5 c1 [. F7 j' f1109080 ALLEGRO_EDITOR OTHER Window DRC is not working in OrCAD PCB Editor Professional + j0 X$ M7 l1 p1 o9 H3 G6 v, _( Q, C
DATE: 02-22-2013 HOTFIX VERSION: 004 P; e. M9 j1 ^4 {/ K* o
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CCRID PRODUCT PRODUCTLEVEL2 TITLE1 I" D ~0 l% Q2 j& S( ?
===================================================================================================================================: F' R- c9 u8 G% n @
1081026 ALLEGRO_EDITOR GRAPHICS 3D Viewer do not show the height for the embedded component correctly ' {1 n7 D; u2 h( R( [/ G1095225 ALLEGRO_EDITOR EDIT_ETCH The Constraint option does not work from right mouse click>Options>Line Width > constraint during interactive routing ( d; U# E0 N0 n( }5 O$ h1096356 ALLEGRO_EDITOR DATABASE Cannot Analyze a Matched Group in CM ! a5 C0 @ T$ [0 v+ }" W1097481 ALLEGRO_EDITOR INTERACTIV Allow replace padstack command in design partition . Z' X! T8 ~: V3 d* x1098252 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figure "circle" in NC drill legend 5 }3 \ y3 b% |- x; d1099958 ALLEGRO_EDITOR PAD_EDITOR Library Drill Report producing an empty report* ~1 ]: t7 {6 {- o
1100401 ALLEGRO_EDITOR OTHER Invalid switch message for "m" for a2dxf command + y; U7 n. S1 D, k. D$ z1101026 ALLEGRO_EDITOR OTHER utl_perftune hanging in fpoly_RemoveVerySmallSegments(), causing shape degassing never to exit. , P r, h/ w) w: K2 B5 b' V$ F1101064 SIP_LAYOUT SHAPE 'Shape force update creates a rat 7 f/ F4 c) Z% S4 u9 f& r1102798 SIP_LAYOUT OTHER Stream out puts offset pad in wrong position if pad is mirrored but not rotated.; w6 \0 [2 J6 I
( M% I& X0 C3 y; p7 q& K# @% x
DATE: 02-8-2013 HOTFIX VERSION: 003; f% t1 m# A6 K1 L& _
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CCRID PRODUCT PRODUCTLEVEL2 TITLE 4 r$ m" `) T g===================================================================================================================================; L8 T, v) E L3 p! z
1077728 APD EXTRACT Extracta.exe generate the incorrect result* m* }4 {/ E! Z
1084711 APD DXF_IF Padstacks with offsets cause violations in Export > DXF. Q, Q# i' X/ |1 I. Y
1090369 SIG_INTEGRITY LICENSING Impedance value not updating in OrCAD PCB Designer 3 a8 m* C4 c' B9 H1093050 ALLEGRO_EDITOR DRC_CONSTR Taper trace on diff pairs not checking to min line spacing. 0 U7 A5 j. V: r! `/ F1093563 SPECCTRA ROUTE PCB Router crashes with reduce_padstack set to on `" g* l( ~' ?0 a1 Q$ d: [1093717 APD DATABASE Design is crashing in Tools > Update DRC and in Dbcheck but seems inconsistent* q4 P8 v; c2 p, X( K
1094788 SIP_LAYOUT WIREBOND Wirebond edit move command' |6 Y8 J4 ?. j, C7 Q8 a5 ]: C
1095786 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro PCB crashes when running DBDoctor, {. |3 o! `: P
1096234 ALLEGRO_EDITOR DFA Via pad connected to shape didn縯 show up after 縎uppress unconnected pads� option. 8 U0 h5 ?% L9 l* P9 j6 d1096313 RF_PCB LIB_TRANSLATOR Allegro Discrete Library to Agilent ADS Translator offsets in the CDNSsymbo.iff / Y) \" ^7 z2 v$ Y1096613 ALLEGRO_EDITOR INTERACTIV Enh-While moving parts silk ref des should remain visible 1 f& U. c2 j# Q, y7 ~1096676 CONCEPT_HDL CORE SPB 16.5 HF36 breaks designs that workded fine in HF35 * k+ U2 Z+ ]: V3 l3 F/ a1096913 APD IMPORT_DATA Import > NA2 fails to bring in the Y1 component.; M7 U. j3 F2 \' H% `( E3 g6 n; t
1097751 ALLEGRO_EDITOR DATABASE Import CIS netlist crashes.! J6 `1 k! j# Z& l8 S6 ?: B
1097889 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro crashes when routing from a via to a pin using High Speed option license.8 [& V4 j: g5 X# B% M
2 H! `- E' O9 h3 rDATE: 1-25-2013 HOTFIX VERSION: 002' X& V7 ]3 O4 e) W' W. |: q7 p7 `% m
=================================================================================================================================== ' V% |7 D1 F0 `! }* A# N- vCCRID PRODUCT PRODUCTLEVEL2 TITLE6 ^2 V2 W2 D( f, s8 n
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491042 CONCEPT_HDL SECTION Prevent PackagerXL from changing visibility on SEC attribute# c% C7 H+ Q5 z2 O6 z( U
863928 ALLEGRO_EDITOR INTERACTIV Segment over void higlights false "nets with arc"0 X7 s4 ^9 p s) Y4 }+ j! H
1067272 PCB_LIBRARIAN CORE Unable to retain the symbol outline changes' Y. i$ q- y7 W& @5 K' A( M' I
1074820 ALLEGRO_EDITOR GRAPHICS losing infinite cursor tracking after selecting the add text command with opengl enable ; d7 d6 a) W: p+ ?1075622 CONCEPT_HDL CORE PDV Edit Symbol in DE-HDL all editing functions disabled since Hotfix 33 2 C2 i# v, H- M3 m+ p7 R3 N# a1076986 APD WIREBOND Wirebond Adjust Min DRC does not maintain the finger position in the same sequence / U1 M W! q- J$ Y1078031 SIG_INTEGRITY REPORTS Requesting improvement to progress indicator for report generator 8 A! e, c$ ?2 W8 w T; |8 K9 x1080213 SIP_LAYOUT WIREBOND Wrong behavior of Redistribute Fingers Command : i# _$ c7 V$ f# W- x+ ?1080667 ALLEGRO_EDITOR GRAPHICS Allegro lines with fonts not displayed correctly in 16.64 I* S: k: Q! |- \0 }
1080982 CONCEPT_HDL CORE Crash of Allegro Design Entry during a copy of a note. ! ]9 h) k6 o, ^* i v$ I* J1081200 CONSTRAINT_MGR OTHER In the DIFF_PAIR worksheets various Analysis seem to take a long time to complete.3 V/ Y. u$ o* L. |+ H9 d/ \. S
1081553 CONCEPT_HDL OTHER Model Assignment can not translate M (Milli-ohm) property value of DE HDL. ; v3 ?2 ]4 A) A8 l) l" k1081696 ALLEGRO_EDITOR INTERACTIV Compose shape not working when radius is set to 1.0 ! c- H# \6 l a+ g: r1082595 ALLEGRO_EDITOR COLOR Infinite cursor remains white even we change background to white' z R- c ]7 k6 x% T
1082704 ALLEGRO_EDITOR GRAPHICS infinite cursor disappears when using Display>Measure 9 z& Z- ]% P: `# [1082715 SIG_EXPLORER INTERACTIV Single line impedance for BOTTOM Layer is not calculated in cross section upon changing the thickness of dielectic layer1 Q6 z. b8 n- x( L) Y
1082774 ALLEGRO_EDITOR TECHFILE Import techfile command terminates abnormally when importing a generic techfile. 4 j C2 ?( o3 V6 g! D1082820 CONSTRAINT_MGR UI_FORMS The configure generic cross-section pull downs do not work.2 t' ^$ s1 k) G8 U( k' C7 R4 M/ e
1083133 SIP_LAYOUT INTERACTIVE SiP will crash when using the beta Pad Rename command to change a BGA pads name.4 g# A/ c0 D# [0 y
1083158 ALLEGRO_EDITOR GRAPHICS The cursor chage to Arrow head for Shape Select is more sensitive to location in SPB 16.69 a% L4 N" U# l' t- t
1083533 CONCEPT_HDL CONSTRAINT_MGR Bug -Net-count under few of the netclasses are not in sync between Schematics & Layout ! v {7 @+ l" g3 L' {1083637 PCB_LIBRARIAN CORE Save As is not renaming the NAME in the symbol.css file- r% |' |5 Y% y0 n! s# T9 d
1083934 ALLEGRO_EDITOR PAD_EDITOR Error(SPMHUT-41): File selected is not of type Drawing.$ b1 P0 R5 V5 M! M" a7 D$ }. w, b
1084148 CONCEPT_HDL CHECKPLUS The CheckPlus hasProperty predicate fails in the Physical environment. 5 |6 ]! d0 l! p) T" h1084166 SIP_LAYOUT DIE_ABSTRACT_IF Updating sip layout with new die abstract doesn't properly update IC_DESIGN_CELL* properties # ]* k! H. \9 U1084285 CONCEPT_HDL INFRA Corrupted dcf was never fixed and caused PXL error7 M( o% r3 X# v8 C5 x
1084441 CONCEPT_HDL CORE Assigned net property value changes to numeric . G8 U% H: A& |3 {4 n3 v4 j l2 |1084542 ALLEGRO_EDITOR DRAFTING Dimensions associated with frect doesn't rotate with the symbol.4 O; b+ t0 ~1 o; }3 E1 H, D9 I
1084736 APD IMPORT_DATA Import SPD2 file from UPD-L shape Pad and text issue6 {# i/ I# ]0 C& `
1085008 ALLEGRO_EDITOR INTERACTIV Relative (from last pick) option in the Pick dialog not working for pick command - T! y5 Z5 m7 \) {6 y1085139 ALLEGRO_EDITOR GRAPHICS Infinite Cursor disappear during Add Connect if Infinite_cursor_bug_nt is enabled' j% z2 }; e: ? r3 I: c" ` R* u
1085187 SIP_LAYOUT INTERFACE_PLANNE netrev with overwrite constraints fatal error8 U7 ~* D& y3 n; ^9 d
1086402 ALLEGRO_EDITOR GRAPHICS Infinite cursor dissapear when using command like add connect or Place manually with opengl enabled. $ P3 e( _& p! t6 U1086905 PSPICE SIMULATOR PSpice crash while simulating circuit file with BREAK function) j; K# ~1 l7 y3 m+ s
1087770 ALLEGRO_EDITOR EDIT_ETCH Allegro crashes on a pick with the slide command. : V# ~ T1 ~2 t7 j0 Y% b1088412 SCM CONCEPT_IMPORT why reimport block adds _1 to the netnames?+ h+ V2 i w0 R( ~, r( \
1088958 CONSTRAINT_MGR INTERACTIV annot create Differential Pairs out of nets that belongs to a Net Group. B, P8 h7 i% S! I0 _
1089336 ALLEGRO_EDITOR GRAPHICS infinite cursor and pcb_cursor_angle, D: ?1 W8 C S; V/ m7 u& e
1090689 ADW LRM LRM: Unable to select any Row regardless of Status9 Z8 L$ l$ R% {' Z8 b6 V2 w/ i
1090955 ALLEGRO_EDITOR OTHER Cancel command crashes PCB Editor when add rectangle / @5 g- ~7 M8 P ?5 A8 S% U1091047 ALLEGRO_EDITOR REPORTS The "Dangling Lines Via and Antenna� report seems to be missing vias that are antennas. ( }+ v. n- ?. H+ Z* b. ^% H+ G3 X1091218 ADW LRM LRM is not worked for the block design of included project9 H1 h" t) }( `" G& G* a2 K
1091443 ALLEGRO_EDITOR OTHER Crash when toggling suppress pads 9 x" r, J, r) M$ \ w/ D& P+ U1091706 ALLEGRO_EDITOR EDIT_ETCH Allegro crash while routing after setting variable acon_no_impedance_width% r; @& C, U7 ]/ i* I4 w% d$ k
1092916 CAPTURE OTHER Capture crash 5 Z! Z5 d$ l0 s: t1093573 ALLEGRO_EDITOR DATABASE team design opening workflow manager crashes allegro. possibly corrupt database / d* k8 _& C7 h; A. e & r# r2 Q' U; P0 @" dDATE: 12-18-2012 HOTFIX VERSION: 001 / Z8 {/ R1 g7 G& \- _ U=================================================================================================================================== 3 s0 }, J8 P* R n6 SCCRID PRODUCT PRODUCTLEVEL2 TITLE' _5 Y* {8 w3 ^/ J. t9 o% V4 S& h
=================================================================================================================================== - S& K8 Y9 L/ d0 T501079 ALLEGRO_EDITOR MODULES Enhancement for Module swap function similar to component swap, u$ r O3 H/ h( l4 ]" s J1 f8 K
745682 CONCEPT_HDL CORE Attributes window requires resizing each time DEHDL is launched( n; p8 @! c0 V) O) t9 \
825846 CONCEPT_HDL CORE The module_order.dat file gets corrupted$ [+ d& c) y; V o: \- {9 h8 q, M
871886 CONCEPT_HDL CORE Browse button in Signal Integrity window of DE-HDL option causes program crash , D: D C- C$ \* _891439 ALLEGRO_EDITOR INTERACTIV moving cline segments, b' z) H& A% E, i0 _% y
898029 CAPTURE PRINT/PLOT/OUTPU ENH: TCL:To show net alias clearly in print out if alias has underscore0 L9 G; o; |8 G; d& C; k8 Q4 c) U9 g
923210 CONCEPT_HDL CORE Search with multiple properties does not show all properties0 n- I: y& u+ E
938977 CONCEPT_HDL CORE Properties attached to standard/DRAWING symbol does not propagate to parts placed in the schematic. L( T3 C3 y- H+ d& [, u3 z
947451 ALLEGRO_EDITOR INTERACTIV Allow the tool to select multiple shapes when assigning a net to more than one shape.. I( U, E4 r( p$ i, I
968646 ALLEGRO_EDITOR EDIT_ETCH The Cline to Pad spacing not followed for Multidrill pad it is more then minimum spacing . B. u8 @/ q5 ?* b8 C976723 ADW MODEL_MANAGEMENT SI DML Model has to be provided the Auto Generate function for discrete components on DBeditor 6 H( p# C5 V- C$ a- P2 T+ ~5 Y- G7 ~981767 SCM UI Add series termination in ASA will crash if both output and input pins are selected.! ]! d1 f' X1 n7 y
982273 SCM OTHER Package radio button is grayed out 8 r% S3 f0 u, }5 E988438 CONCEPT_HDL CORE Visible constraint disrupts MOVE command + X. X1 e/ w& x m989471 ALLEGRO_EDITOR INTERACTIV Functionality to zoom to the selected object in Pre Select Mode 8 Y* u0 c, V# _& F" a) n993562 CONCEPT_HDL INFRA After upreving the design save hierarchy is leading to WARNING(SPCOCD-34).2 ?: {' P7 F4 S/ {% Q
996577 SPECCTRA ROUTE Specctra not routing NET_SHORT connections + K9 o7 L. Y6 p8 v* j& H$ U7 M* `997992 CONCEPT_HDL CORE Why are Page Numbers not enumerated correctly when multiple TOC Symbols are used?9 y& k7 w" V0 q9 V6 Q9 N# b" ]
1001300 PSPICE MODELEDITOR BUG: Simserver crash with encryptedm model & L% h) {% N. k& W2 W( J% O$ \! p1010124 PSPICE SIMULATOR Monte Carlo summary doesn't list all the runs in case of Convergence error in one of the runs 2 G% }; d2 n9 A' a3 S" h1 j% r" p1013656 SCM OTHER create diff-pair should honour diff-pair setup or ask user for positive negative leg! A5 o! ~8 Q2 n# x1 _$ J/ Z9 e7 t$ u
1013721 ALLEGRO_EDITOR EDIT_ETCH Routing near a 2x3 multi drill padstack does not maintain the spacing constraints. : [* {( Q S! P- |1016859 SCM REPORTS dsreportgen exits with %errorlevel% , V# n. A' l: b: S$ f1018506 ALLEGRO_EDITOR INTERACTIV Edit copy with retain net of via will assign net to pin 8 j2 g M" P0 h1020746 CONCEPT_HDL OTHER PDF Publisher tool behavior inconsistent between OSs 7 \" G& N* U& o, u. p1020798 SIP_LAYOUT SHAPE Shape not voiding on layer 2 causing shorts + h0 G& m# T' p. d, f9 I1 K1023051 SCM UI Wrong and incorrect message is generated while adding connectivity in SCM matrix view � DSTABLE-140 ) q6 ~( k6 x8 E2 Y( q8 C1023774 APD WIREBOND After "xml wire profile data" is imported it isn't reflected to actual wire. , C3 [/ }# k0 i: V7 J" T2 S! x) O1023807 SPECCTRA GUI Unable to close SPECCTRA using File > Quit or by clicking on standard window red close cross button8 i8 N+ h% h5 c0 s3 G2 g7 e% I5 K
1024239 ALLEGRO_EDITOR INTERFACES DXF pin location is moved when I execute DXF out ; G2 y+ }& a6 z1028237 CONCEPT_HDL HDLDIRECT Error binding design when generating simulation netlist X- P" \. |: t1 D1 `
1030591 CAPTURE LIBRARY Library Correction utiltiy locks the library and deosn't frees it even after being closed - y6 f( Z: U" B# t2 D1035624 CONCEPT_HDL CORE Options pre-selected when launching base product" @' p* m, C, J% A5 }8 ^2 }- b0 E4 f
1035896 SIP_LAYOUT ASSY_RULE_CHECK Rule Wire Length under Wire on line in Assembly Rule Checker doesn't work correctly 6 l6 q' T# c! K0 I1036580 ALLEGRO_EDITOR MODULES Module created from completely routed board file has lot of missing connections in it. / H' c0 U. ^" K7 K& t1037345 ALLEGRO_EDITOR INTERACTIV Enhance Allegro's Snap-To tools to select the origin of a sub-drawing(clip file)" R( C( c, J7 ]
1038180 ALLEGRO_EDITOR DRC_CONSTR BGA escapes not being calculated in phase tol: ?1 \/ O( h8 r8 y, u) Q* n' i
1038285 SCM UI Restore the option to launch DE-HDL after schgen. ?# R( e) u# S7 v
1038371 ALLEGRO_EDITOR INTERFACES Import > IDF fails with error "(SPMHDB-187): SHAPE boundary may not cross itself." R+ b/ ]/ r- Y$ v& \
1038577 ALLEGRO_EDITOR DATABASE Modifying Void crashes Allegro ' o( R' x2 H; ]7 T. {1039112 ALLEGRO_EDITOR ARTWORK Antietch and Boundary layers deleted when Match Display selected ; X! Y2 t9 R2 J. C6 ~1039147 ALLEGRO_EDITOR COLOR Need an option to change color of Text marker and Text select in Display listing 0 m+ ^% A' C4 X- ^1 N1040653 ALLEGRO_EDITOR DATABASE Cannot update netlist data, ERROR(SPMHDB-121): Attribute definition not found. d5 }% A. j: g& @1 r" }& ^
1041368 APD DEGASSING The Degas_No_Void properties assigned to Cline does not work. * ^. Z6 Q5 m$ s7 B8 J- O9 Z1041864 ALLEGRO_EDITOR MANUFACT Allegro crashes when opening the Backdrill setup menu- f/ ^3 f: E" t% ]
1042199 SIG_INTEGRITY SIMULATION Waveform list was not refreshed by switching tab. # N" X* Z$ W4 a! V1042348 SIP_LAYOUT STREAM_IF GDSII export includes the full refernce path, breaks CATS flow 7 F0 P6 d1 n7 H6 u1043861 SIG_INTEGRITY REPORTS Derating values are NA in bus simulation report when derating table is not in working directory3 g1 D' s5 x: I9 ?
1043903 GRE GLOBAL This design crashes during planning phases in GRE.$ @/ ~, ~0 k7 k- \7 L! ?
1044029 PSPICE ENCRYPTION Encrypted lib not working for attached; q2 p+ j. Y( t3 ]
1044222 ALLEGRO_EDITOR INTERACTIV Capture Canvas Image changes working directory 7 Z2 e5 W. e0 V# L1044264 PSPICE SIMULATOR Why does the 'ORPSIM-15009:This device scales to 0.0 at this Temperature' Error occur.4 ~* l0 ^! l* k
1044577 GRE CORE Plan > Topological either crashes or hangs GRE . p+ @+ Y! r( X( i. p! F1044687 TDA CORE tda does not get launched if java is not installed9 O2 c8 P; v! C J+ o; h) I5 P
1044754 SIG_INTEGRITY SIMULATION Incorrect waveforms when simulating with stacked die ) j& [4 Z7 L: d2 T. o. P1045607 ALLEGRO_EDITOR OTHER Component get placed even after Cancel IDF in form. % _( v* Q0 ^* S3 f) v3 s k& f& E9 s1045694 CONCEPT_HDL INFRA Why to package the design twice to pass the net_short property to the board? 3 a* _* A. P8 A. a: H9 R1045863 CONCEPT_HDL INFRA Customer had the crash several times when they run script with SPB16.51.& `. C5 R: u& }6 b' R& v
1046929 CONSTRAINT_MGR OTHER Unable to create physical of spacing cset after rename the default cset in design entry. * G0 f1 N! ~; P, n/ j/ I1047590 ALLEGRO_EDITOR SCHEM_FTB Buses created in Allegro-CM are deleted by netrev in traditional flow 7 _# W. S3 U, P$ G, `" X1047823 CONSTRAINT_MGR OTHER acPutValue predicate text not being displayed at bottom of Constraint Manager window. 7 r3 T# H) U( W3 d5 ?0 g1 U( y1048403 ALLEGRO_EDITOR SKILL Allegro crashes opening more than 16 files with skill , p4 c. J, V% O/ t! D4 m) ?1049262 ALLEGRO_EDITOR OTHER APD and extracta crash owing to Wirebond.7 @9 P. ^/ h5 Y9 _( j
1049303 CONCEPT_HDL CORE Block rename deletes schematic data immediately in 16.5 ; T }3 g- y+ l0 R1 r% S d1049317 CONCEPT_HDL OTHER bomhdl with scm mode not working on RHEL in 16.54 L3 C* z: v) A! Y/ O$ S
1049399 SIG_INTEGRITY OTHER Toggling z-axis delay in CM shows the same value1 K2 H3 ]2 f4 j \
1049956 ALLEGRO_EDITOR DATABASE BUG:dbdoctor deletes fillets as design is migrated from old version : S* V ~' w) O! x9 f+ D" W1050408 APD DXF_IF Symbol has 45 degrees rotation in mcm but DXF doesn縯. # v2 X: ^- c5 i3 s$ @1050483 ALLEGRO_EDITOR DRC_CONSTR DRC has been waived but after updated DRC system generated a new DRC. 5 I: v9 ~0 ?) H) G( s1 x/ r1050918 ALLEGRO_EDITOR MANUFACT Testprep Automatic generate testpoints with wrong padstack Itype in SPB165S026. 8 T: D! F( E$ |1051588 ALLEGRO_EDITOR PAD_EDITOR Pad_Designer library drill report omits some drill holes , d$ [% t3 Z( N1 o$ @! B0 l1052005 SIG_INTEGRITY OTHER Huge difference in Z-Axis delay with the latest hotfix for 16.5 that did not exist in older ISR's of 16.5.: N4 }4 h @0 E6 ]
1052045 ALLEGRO_EDITOR OTHER Bug - Thermal relief connects not sustaining 15 degrees component spin in version 16.5 unlike v16.3& B- a- n+ I1 P, z2 C: O
1052449 CONCEPT_HDL COPY_PROJECT Copy Project does not update all relative paths in the cpm file& k. t6 {, u7 n" G0 @
1052600 ALLEGRO_EDITOR SHAPE Adding a specific cline causing shape errors ) E/ o: \; Q0 t1052753 ALLEGRO_EDITOR DRC_CONSTR Allegro showing soldermask drc only when the symbol is rotated.* \' B# |! E+ k% X
1054235 ALLEGRO_EDITOR PLACEMENT Cannot place alt_symbols for mechanical parts.- n" d0 \5 |5 i% {- [( W
1054269 ALLEGRO_EDITOR MANUFACT Backdrill Setup and Analysis crashes on attached design 2 N; P8 N- T% k1054351 ALLEGRO_EDITOR SHAPE Shape voiding fails for board having diffpairs with arcs$ R- R9 q, o. L
1054456 ALLEGRO_EDITOR MENTOR mbs2lib incorrectly translates refdes label8 {# t4 H) `8 ]# B( |- i
1055273 ALLEGRO_EDITOR INTERFACES DXF exported from Allegro has an offset in pad location for Y- direction. * ~. n2 C8 [, n5 m, m1055328 CONCEPT_HDL COPY_PROJECT Project Manager - Project Copy/ F: L3 {" E- I. A7 `8 ]9 q
1055481 APD SHAPE keepout does not clear shape unless it's picked up and dropped down ) u$ A, f# c/ f1055729 CIS GEN_BOM Standard CIS BOM per page is not working correctly with option Process Selection' f }* D. Z9 O3 Q( e8 v
1056418 ALLEGRO_EDITOR OTHER PDF exports the blank text markers whether or not the markers are visible. ! {7 |) h/ F) b# C1056579 CAPTURE OTHER Ability to define custom variables for titleblocks that update for specific variant views , K$ `! L- @ o1057003 ALLEGRO_EDITOR SHAPE Z-copy to create RKI does not follow board outline* M) {# }( p0 e {2 U
1057976 ALLEGRO_EDITOR DRC_CONSTR No Same net Spacing DRC on attached design. 4 P) M+ Y K8 I, e, b4 ^! w$ m1058002 SIG_INTEGRITY SIMULATION Incorrect Xtalk sim netlist was created. * T- G2 c2 j6 T' e% ]6 G8 L1058364 ALLEGRO_EDITOR SKILL axlTransformObject() is moving refdes text when only symbol pin is selected for move 7 F1 l8 s ~: t8 x' E O% V; M, G1058940 ALLEGRO_EDITOR INTERFACES IDF(PTC) out command output wrong angle value9 A- y0 U2 y, Z7 H7 i
1059037 CIS PLACE_DATABASE_P What enables the Refresh symbol libs option under hte update menu in CIS explorer / w0 D8 Y+ n1 U0 x9 S: g1059389 ALLEGRO_EDITOR MANUFACT about back drill analisys report % f Z1 J5 ^1 z- ?9 P) Z2 C9 d1059901 CONCEPT_HDL CORE Global Property Change and <<OCC_DELETED>> property value. 0 }9 s, L: Y" T( N+ _3 ~( K/ m0 t+ g1060428 ADW DESIGN_INIT ADW Flow Manager Copy Project fails to complete7 v) {6 J2 j9 A0 P! i4 q( C6 g
1060589 F2B PACKAGERXL Packager Fails with ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance properties.1 u5 }% y3 t6 `
1060977 F2B DESIGNSYNC back annotate in 16.5 does not bring in already placed nets as global nets! p" U2 {6 u1 i& }
1061223 CONCEPT_HDL CHECKPLUS What determines a passthru pin? ' N1 _2 t: ]. f, x) ]1061424 CONCEPT_HDL CORE Customer creates <<OCC_DELETED>> property values.! k( E5 j+ E0 E. i" f
1061572 ALLEGRO_EDITOR INTERACTIV Shortcut keys wont work after "Edit Text" command is finished. 9 Y; @6 W# U# X- q* B1061659 ALLEGRO_EDITOR DATABASE Unable to return drawing origin to 00, j) O3 d8 @- ~( n. c& V
1062558 APD DXF_IF If set both in X and Y offset DXF only get one and not get absolutely value in 45 degree rotation & I6 c, _% g" U N0 n1062982 ALLEGRO_EDITOR MODULES Module containg partitions has been imported to the main design and cant be refreshed. h# w, |4 y( a1 {, o) Z
1063284 PCB_LIBRARIAN OTHER PDV Save As is broken 5 j7 G6 e1 Q1 {; k1063658 ALLEGRO_EDITOR SCHEM_FTB Allegro Import Logic does not remove library defined diffpairs - g; _; O/ S5 u% ^% U) ^1063778 CONCEPT_HDL CHECKPLUS The hasSynonyms CheckPlus predicate is not returning true for all global signals.1 B. W; _: g" Z8 M$ Z! d6 A
1063924 CONCEPT_HDL CONSTRAINT_MGR Highlight the net between DE-HDL 16.5 and Constraint Manager. # q" T+ o v2 j1064707 CONCEPT_HDL CHECKPLUS Rules Checker core dumps on design 4 h, O; E* ]; T ~1065124 PCB_LIBRARIAN SETUP PTF properties cannot be deleted from the setup in PDV" _# E7 f, ^, I. h( l% n& o
1065618 CONSTRAINT_MGR ANALYSIS DRCs on board but Constraint Manager shows the columns as green." i" B& W$ T: q8 j' x
1065641 PCB_LIBRARIAN CORE PDV symbol editor is crashing when deleting a group using delete or CTRL+X; M9 G- G2 J4 E. o: M. p( G
1065745 SIP_LAYOUT DATABASE The logic assign net command crashes the application 1 {/ Q8 n8 H+ ]* o }" x" C1065860 ALLEGRO_EDITOR REPORTS Design crashes when running a padstack usage report, B% I+ H9 w0 T& e
1066051 ALLEGRO_EDITOR TESTPREP Auto Testprep generation creates TP with Testpoint to Component Locatin DRC4 S& o# U& X% l' X" i* l+ x; Q! b
1066318 CONCEPT_HDL CREFER Issue with LOCATION visibility in flattened schematic : ]# l* `1 m7 W1067339 CONSTRAINT_MGR ANALYSIS Relative Propagation Delay analysis in the Partition file seems very inconsitent.6 {6 ~5 B( N$ t6 O2 p
1067984 SIP_LAYOUT OTHER layer compare batch fails with write protected file" h/ r- S+ \1 A2 z, O
1068425 F2B DESIGNVARI Out of memory message in Variant Editor while 縞hange properties� command g' P2 w- |3 x0 I; T1068547 ALLEGRO_EDITOR EDIT_ETCH Outward Fanout is not fanning out this 4 sided part as intended6 @( l8 u; G0 j8 W) p9 f% g& ^$ |
1068966 SIP_LAYOUT DRC_CONSTRAINTS DRC update aborts on this design with ERROR -3000067 ( V% H/ V3 \& V* U1069215 CAPTURE DATABASE Capture Crash on usnig a TCL utltiy to correct design 0 L" ^2 S( W2 T; \8 X3 A1069517 SIP_LAYOUT DIE_EDITOR change die abstract pins tab default action from delete to modify2 C+ S: u7 D1 x) ]9 ^5 v0 ^
1069915 ALLEGRO_EDITOR EDIT_ETCH Allegro hangs with when doing spread between voids z( @8 r: _) b# c( |1070007 ALLEGRO_EDITOR PLOTTING Export IPF omits drill figure characters for backdrill holes 6 ]3 B& j- b3 a$ Y0 `! S1071722 SIP_RF DIEEXPORT Virtuoso SiP Architect not writing out pins to the .dra needed for LVS flow. M0 T+ z5 W- ~) T
1072067 APD EXTRACT When expoting using Extracta oblong pads with anyangle are abnormal- n* _5 X) t8 y8 ?; F3 h; }
1072791 ALLEGRO_EDITOR DATABASE Database check cannot fix error and keep report the same issues cause artwork cannot export. 9 t8 i5 ?% U9 a5 x1072806 CIS EXPLORE_DATABASE Query tab in CIS explorer doesn't show searh fields in 16.60 L6 {5 h# A J' E
1072843 ALLEGRO_EDITOR PLACEMENT The move command that was present in the right mouse pop up menu during manual placement is missing in 16.5 * ~0 V- V. q' a+ `" P ~1072904 SIP_FLOW SIP_LAYOUT Probe pins not being mirrored in Die Editor correctly in Chip Down mode. . H) t* F4 `7 Z I# e1073237 SIG_INTEGRITY GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation.9 ~9 p1 V# r \: V: J0 {) T
1073445 ALLEGRO_EDITOR GRAPHICS 'infinite cursor graphics fail -ghost copies as you move cursor % E$ \- }) C* p+ K2 o# H" w1073464 SCM SCHGEN Schgen never completes.% c. F4 X* O/ L7 U1 r9 s
1073587 SIP_LAYOUT OTHER axlSpreadsheetSetWorksheet command clears the cells in memory 2 c% G( r. G- n7 P$ A: j! V, X9 Y1073745 CONCEPT_HDL CORE Import design fails # C$ J3 |# D. z Z( `# W, J1 }6 o) X1073852 ALLEGRO_EDITOR INTERACTIV While doing a Copy Via use the last 'Copy Origin' $ E) q4 O3 D. H9 o# E1074279 ADW DSN_MIGRATION Design Migration fails purge if there are cells with BODY_TYPE ( v0 l9 _) }& A/ ~9 F3 {1074791 CONCEPT_HDL HDLDIRECT User gets port exists in schematic but not on symbol message even though the port does not exist - h1 F5 K% [# n. U% R' ^. h6 i8 ~" c1075135 ALLEGRO_EDITOR DRAFTING Ability to edit dimension text block in Instance Parameter . ^" |0 V- |2 h Z1075151 ALLEGRO_EDITOR SHAPE Cannot change global shape parameter back to thermal width oversize after having used fixed thermal5 b3 R# T7 S& s: V
1075256 ALLEGRO_EDITOR OTHER Import > IPF in 16.5 is dropping data.8 {( X. S1 G5 u/ A; B
1075853 ALLEGRO_EDITOR REPORTS please add "PART_NAME" at Extract UI; Y( R. `' T7 C8 l% B
1075934 ALLEGRO_EDITOR DRAFTING Able to Changing Dimension Text Block 2 v: Z" j/ c& n9 P/ O' p( g8 O2 L1075955 CAPTURE SCHEMATIC_EDITOR ZOOM in 16.6 using key "I" on keyboard in not centered on mouse pointer 1 d. H4 i; W4 k3 L, N1075964 ALLEGRO_EDITOR SHAPE Shape voiding is not consistent in conjunction with odd angle and arc traces" ~5 w: T0 ~# I+ z! F+ r
1076086 SIP_LAYOUT IMPORT_DATA missing wirebond after import SPD2 ; o3 G# X0 V9 z" v* \1076202 ALLEGRO_EDITOR EDIT_ETCH Allegro add connect causing crash after Hotfix 3 v- ]3 m' C9 a& l2 f0 c$ z/ H1076205 CAPTURE PRINT/PLOT/OUTPU : Printing of User Assigned RefDes/ \$ f$ F& A4 S- J! v% R. Q
1076536 ALLEGRO_EDITOR DRC_CONSTR Embedded component which protrude out toward Top do not create DRC with Place Keepout on Top+ X1 r5 w: E! f& R- g
1076538 CONCEPT_HDL CORE Property visibility changes in attribute form not updated in schematic canvas. . K& S _ l6 L- l6 _$ p1076655 APD DXF_IF Dxf does not get offset value if die symbol padstack has offset value * F4 o1 C; w p2 Z! @0 G1 M! j1076846 ALLEGRO_EDITOR EDIT_ETCH Grid snapping broken after slide in 16.6 + ^" h3 @1 P( c" O, T1076891 ALLEGRO_EDITOR INTERACTIV Symbol rotation not displayed correctly when defined as a funckey / I. x2 |# v- X1 G# O! B% X1076909 ALLEGRO_EDITOR DRC_CONSTR Allegro crashes while placing modules from database 1 m" T6 o: h4 X$ v1 z3 a# Y) z; ?1077084 CAPTURE NETGROUPS Crash on selecting bus when Enable Global ITC is unset0 T7 U T8 R7 H: W0 I3 u* I% _# H# B
1077169 APD SHAPE Shape > Check is producing bogus results. 8 P7 q8 Y% x5 t, C2 a/ \4 K5 g1077572 ALLEGRO_EDITOR DATABASE Mechanical symbol created with 16.6 cannot be placed on board. 9 T0 [7 K0 A; ^6 [1077879 ALLEGRO_EDITOR SKILL Allegro Skill axlDBCreateFilmRec fails when 15th argument missing "draw hole only" for the first tim ( Z/ {8 [) C6 D, L; U! z1078380 SCM OTHER Custom template works in Windows but not Linux; y- h% `9 j& V9 @3 C) s$ @
1078497 ALLEGRO_EDITOR INTERFACES Import DXF does not seem to work correctly. . ~, l3 U5 J6 {+ G# d1078682 ALLEGRO_EDITOR DRC_CONSTR Unaccetable slowness with Slide % N/ ?+ H6 \% [. d1079082 ALLEGRO_EDITOR PLACEMENT Swap components, gives error SPMHGE-616, when symbols instead of components are selected for swapping$ P& r' d- C. S4 X9 K
1079533 ALLEGRO_EDITOR PLACEMENT Swapping components in 16.6 results in Error "E-(SPMHGE-616): Symbol and layer embedding requirements do not match") o( J3 K, Z+ F
1079937 CAPTURE SCHEMATIC_EDITOR ZOOM in 16.6 is non uniform on text; g) I2 b& s9 }( A5 _2 D
1082582 ALLEGRO_EDITOR GRAPHICS Allegro hangs on a given testcase using the MMB zoom control3 W8 |+ Q0 t; B' F
1082981 ALLEGRO_EDITOR SKILL Allegro crash while change the new symbol type as mechanical. # w4 S5 `+ F' s2 K6 t1083230 SIP_LAYOUT SHAPE Shape fill in 16.6 releaase not fillilng shapes as good as it did in the 16.5 release.) T9 Y$ k& ^& x, q! I" l! x9 q 作者: yondyanyu 时间: 2014-7-31 10:18
补丁真多，BUG真多！作者: bluemare 时间: 2014-7-31 10:49
