标题: Cadence 27号 补丁修复的BUG较多更新百度网盘链接 [打印本页] 作者: dsws 时间: 2014-4-26 15:14 标题: Cadence 27号 补丁修复的BUG较多更新百度网盘链接 本帖最后由 dsws 于 2014-4-28 12:56 编辑 * l/ i5 g* Q& p4 o! G4 _) K + d6 l# @; q# W! }- S# b' ?% H! K( q! b链接: http://pan.baidu.com/s/1dD9XLPB 密码: ujuq 5 t- m- z4 i% H; z! O) {" X! y+ h9 p+ r! J
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DATE: 04-25-2014 HOTFIX VERSION: 027* K3 ?1 K( d4 A1 a" O
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CCRID PRODUCT PRODUCTLEVEL2 TITLE + _; o1 I7 n P9 W# q; q m5 K===================================================================================================================================0 {6 j; m |7 Y; S1 Y; x* E- A
308701 CONSTRAINT_MGR OTHER Needs to delete user defined schedule in CM2 Q+ ^, z2 v! u
481674 ALLEGRO_EDITOR PADS_IN No board file saved from PADS_in: u. W1 x: r( i2 ]
982929 ALLEGRO_EDITOR EDIT_ETCH can't route on NC pin and other that are not pin. % Q" W: Q6 S0 w# o F1012783 FSP OTHER Need Undo Command in FSP: D1 Z! Y0 ^: A/ D0 B* n
1017381 ALLEGRO_EDITOR DRC_CONSTR Need Dynamic Phase to be able to measure back to the Drive Pins. 3 e4 O5 c5 v/ u1072673 PCB_LIBRARIAN GRAPHICAL_EDITOR Copy paste goes offgrid if mouse is moved 1 \: K: W5 { c1073231 CONCEPT_HDL CORE Copy-paste of signal names goes off-grid in Windows mode., k) e. X& Q0 P* Y
1105371 CONCEPT_HDL INTERFACE_DESIGN Strange behavior when shorting two Net groups 1 C0 t8 A* n+ X: E9 u* ^1116498 CIS LINK_DATABASE_PA link database with modified part results in Capture crash 6 t. p. C7 [( A0 N8 j/ J7 l1118632 ALLEGRO_EDITOR GRAPHICS Text display refresh issue while in Edit > text command& ? Z o; v2 _. r2 z6 S6 j; q6 \
1155821 SIG_INTEGRITY LIBRARY Xnet are not recalculated correctly when model is changed on the Series switch part defined as discrete with Espice mode 6 R6 H1 S$ k/ R1 g$ d1 [1157372 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase for Diff Pairs not reporting back to Driver pin if pin escapes present$ [0 Z# b1 p2 r- y S; Z
1171951 ALLEGRO_EDITOR CREATE_SYM Jumper has a limited of count when it add to list. 9 w% z1 A- T4 a1180871 CAPTURE LIBRARY_EDITOR Copied parts don't retain pin name and pin number settings 4 J- X* f! `: L4 ]- G/ f1185575 SIP_LAYOUT DIE_STACK_EDITOR Updating symbols causes the graphics for the Assy layer to change from Bottom to Top.1 Y" s( ^/ m7 P+ | c' C6 O9 i
1185772 PCB_LIBRARIAN CORE VALID_PACK_TYPE warning when cell was opened in PDV 0 O; f: b+ o. C1192377 CAPTURE SCHEMATIC_EDITOR Pin name/number position is incorrect on schematic if it is changed for a rotated part.; a- [6 e7 k9 h3 P+ K& J7 W
1202654 ALLEGRO_EDITOR GRAPHICS Zoom using mouse wheel shall maintain the center co-ordinates4 v) A( F; T/ O1 m {- l
1208031 ALLEGRO_EDITOR INTERACTIV Snap to Pin for via during Copy command do not snap to connect point everytime4 N3 v) i! Y* y( q
1208478 PSPICE PROBE Attached project gives overflow error with marching ON. R) V% O: M5 x
1210015 CONCEPT_HDL CORE The value of $PN should be not turned on spin or rotate symbol 8 X% ^1 Z# [% s1210425 CONCEPT_HDL CORE When moving a circuit tool reports that connectivity has changed 7 R# j: I5 Q% O. T1215858 ALLEGRO_EDITOR SHAPE Force update does not void cline with the shape ; l- n L+ s) ?8 m4 ]$ j1215906 ALLEGRO_EDITOR SHAPE Dynamic shape fill smooth failed when copying to other layers8 Z# I2 |' Q$ [4 r, b! P* j
1216358 CONCEPT_HDL CORE Can we improve our export BOM function to check if user did export physical function before exporting BOM? 1 u5 S _- B- F, O( K$ T6 D1217364 CONCEPT_HDL OTHER Netlist reports fail because error: GScald failed.1 v: i2 B5 E3 c/ n: h
1217529 CONCEPT_HDL CORE ADW checks do not catch single quotes in PTF values $ n% {3 T* c& {1217556 F2B PACKAGERXL signal name change not sent to Allegro after packaging8 c" f0 ]7 H S
1219283 ALLEGRO_EDITOR DRC_CONSTR Show constraint is inconsistent when displaying region information( k- w/ j: v* \& G# n2 j+ w" `
1220078 F2B PACKAGERXL Export Physical crashes when ALL the part pins are added 1 W% \$ {( R" X( a2 b3 O1220393 CONSTRAINT_MGR CONCEPT_HDL HDL import physical from board file will annotate CM data back to HDL which includes cross-section thickness. ]) ~7 {7 U0 e7 N* N: Z1220540 ALLEGRO_EDITOR GRAPHICS Need an option to see the pads inside the internal plane shapes [+ E" p: u3 o$ o( i1220936 CONCEPT_HDL CORE About crash by vpadd/vpdelete command on Linux8 C. O5 b: i, Y' M( ^/ R
1221059 ALLEGRO_EDITOR DRC_CONSTR Get a "Shape to Thru Via Spacing" DRC error only the first time when the shape is manually voided." ~: w4 G" o! s$ E; f* o, ~
1221182 ADW TDA Team Design with SAMBA# u! Y% N1 _# R* k E
1222442 CONSTRAINT_MGR UI_FORMS Duplicate pin pairs appear in DiffPair* f3 I" k# x( @
1223175 CONCEPT_HDL CONSTRAINT_MGR Schematic crashes when opened / }* X7 `; Y4 K& l' i) _1223533 ALLEGRO_EDITOR GRAPHICS Why the through pins for STEP models are shown at an offset when viewed in 3D inside Package Symbol? T9 y0 Y, H/ G0 b# S9 M1 ^1223680 CONSTRAINT_MGR ECS_APPLY Improve ECSet mapping by allowing user to address ambiguity of Parts 9 y/ D8 a2 X0 [9 }6 w. F$ m1224156 SIG_INTEGRITY SIGWAVE Exporting spreadsheet with filter Subitems in SigWave exports all waveforms & m$ u \4 C7 q% o( ~2 f% P1224417 ALLEGRO_EDITOR PLOTTING Hidden font pattern is not showing correct in 16.5 version also 16.6 version. 2 ?2 _/ Y9 P; s P4 r% L1224704 F2B DESIGNVARI There is no lock for the variant.dat file - multiple users can open the editor 0 j+ i; G p$ G7 ]1224968 ALLEGRO_EDITOR INTERACTIV Delete >(RMB click) Cut> Snap Pick to>off grid loction does not work for lines. . A) E8 c7 T6 m3 l1224982 CONCEPT_HDL PDF commandline publishpdf does not work when there are spaces in the path * p8 T1 x+ ? I( \1225114 CAPTURE GENERAL H-pins added after netgroup pin get color as of netgroup pin5 s) n2 }; o* Y& V# Q+ Q
1225494 CAPTURE DRC Different DRC results for Entire design and selection " f9 ]( [2 A8 h( C* l, Y% A) I" x3 D, X6 ?1226153 ALLEGRO_EDITOR INTERFACES Export STEP should include PART_NUMBER property 0 X J8 J0 |% M1226235 ALLEGRO_EDITOR EDIT_ETCH Enhancement to include Pin_delay of descrete forming Xnet& W6 t: ]+ i- g
1226372 CAPTURE GENERATE_PART ENH: Functionality to add pin spacing in New Part From Spreadsheet% e' ?( C+ ~/ {8 l8 A
1226477 CONCEPT_HDL CORE DE HDL縮 `Allowed Global Shorts? function is inconvenient for Global Signal 4 H" A9 M+ X$ B1226813 SIP_LAYOUT LEFDEF_IF ERROR SPMHLD-120 when importing a DEF file. Request to increase the number of characters/line in a .cml file * Z" K% P# y/ A1227453 ALLEGRO_EDITOR SHAPE Addition of Fillet generate Pin to Shape Spacing DRC errors and DBDOCTOR errors' T- t' u+ [! Y& o5 {
1227461 ALLEGRO_EDITOR SHAPE Sliding a cline for certain net changes the thermal relief connects for pins connected to another net from 4 to 5,6,7,8* R( j. N7 J; Z! w b1 t v5 Y1 x6 l
1227469 CIS DBC_CFG_WIZARD Oracle Views not visible on Step2 of CIS Configuration ; Z: Q: |& O% R5 _6 X" z6 |7 {' I1227780 CAPTURE ANNOTATE Inconsistent behaviour when annotating heterogeneous part4 g6 T6 V% p9 S: p
1227831 CONCEPT_HDL CORE Pin text and H-block name in upper case 8 `/ Y' P1 i( M) {1 x1227954 CONCEPT_HDL OTHER supress check for global signals when wires are unconnected to pins ( j4 q9 { L% z' w# z/ i$ J1228190 ALLEGRO_EDITOR OTHER Unable to close the 'usage' window during license selection ' M7 Y. G& m: r$ S: r1228899 CONSTRAINT_MGR INTERACTIV Export/Import constraints in "overwrite" mode from same design shows different results when imported second time.- l1 i! A# Q4 E2 b3 S, i( v5 m
1228934 ALLEGRO_EDITOR EDIT_ETCH The "View Active Layer" option like the Board Station should be provided for dynamic layer visibility.+ p5 m m" O( f( @
1229316 ALLEGRO_EDITOR EDIT_ETCH When routing with Hug only enabled we were able to route through other routes(sometimes Hug).- o5 v, Y$ i$ F
1229545 CONSTRAINT_MGR OTHER Allegro indicate bundle scheduled nets in CM 0 ~ _ A" l# N0 k) p' }1230056 ALLEGRO_EDITOR GRAPHICS Bug: 3D View of Mechanical Symbol with the drill hole defined5 P3 B. k4 u/ ?4 n* z4 t8 j
1230432 CONCEPT_HDL CORE No Description information in BOM# u2 l) H, b Z! D9 }( m3 e' L
1231148 F2B DESIGNVARI The variant.dat file is not updated with library PTF changes 0 ^% o* o0 \" b( U) {1231625 F2B DESIGNSYNC VDD at command line needs to support sch2sch and test variable to write out report files 1 F7 @3 [1 _0 `1 c1231697 CONCEPT_HDL CORE If any locked files exist force a pop-up dialog restricting certain commands, H; o. m2 X. q$ @4 H2 O
1231767 CONCEPT_HDL OTHER Unable to find under the search options single bit vector nets ) _% r0 ^8 L4 Q! |% ^1231961 ALLEGRO_EDITOR SHAPE Shapes not updating to smooth unless we use force update and as a result false DRC's appear in board. 3 y- I4 [( \4 w0 k+ n6 A7 Y1232100 CONCEPT_HDL SKILL Unable to execute the SKILL commands in viewer mode ( p. n% T8 i8 P! M# m1232336 CONSTRAINT_MGR CONCEPT_HDL cmFeedback takes 5hrs to complete during Import Physical Q u" t# k9 o1232710 F2B DESIGNVARI Dehdl crash while moving component in variant viewer mode # Y! v% L* d. P; V- ]3 T1233894 F2B PACKAGERXL The page data is missing in the pst* and PCB files) M; E: g! b6 N; f) G0 X
1235785 CONCEPT_HDL CREFER cref_from_list custom text is not subsitituted in complex hierarchy$ w1 K" E; k+ g: `
1235928 CAPTURE SCHEMATIC_EDITOR OleObject modifications not saved 6 ~! B$ I/ ^! A0 q/ X* j" m5 S1236065 CAPTURE PART_EDITOR Mirrored part after being edited get pin name locations incorrect o4 V' x0 [( o% B1236071 ALLEGRO_EDITOR SHAPE Airgap for Octagonal Pads ignores DRC Value when Thermal set4 K( A0 n. Z; e
1236072 CONCEPT_HDL CORE Page 122 cannot be saved as logical page 119 has different page mapping in connectivity data and schematic# v3 ]) } ^& @& C
1236161 CONCEPT_HDL CORE Import Design shows the current project pages ! F! r- V5 y+ R" T" [4 Y1236432 ALLEGRO_EDITOR PADS_IN pads_in doesnot translate via and shape in some instances. % z4 V0 y( R# g+ g8 q. `1236557 CONCEPT_HDL PDF Running Publish PDF on command line in linux doesn't output progress until completion $ U" C5 H* H. [4 h" d2 `1236589 CONCEPT_HDL PDF Enhancement license failure error should appear in pdfpuplisher log file" f6 |* j, `6 `# J6 h
1236644 ALLEGRO_EDITOR EDIT_ETCH create fanout deletes shape : n" j" `/ I9 z, K" i1 @1236689 ALLEGRO_EDITOR GRAPHICS Graphics displays extraneous lines when panning or zooming% Y; L& ~/ |1 `* V5 J4 _% X' w* ^
1236781 F2B PACKAGERXL Export Physical produces empty files; {: [/ d0 q: M/ U, C
1237331 PSPICE ENVIRONMENT pspice.exe <cir file name> - hangs when run , v- P& w: t" h1 _5 q1237400 CIS EXPLORER Capture hangs on 2 consecutive runs of `refresh symbol from lib? command " C4 I- Q5 D, J# N: |7 G1237437 CONCEPT_HDL CONSTRAINT_MGR CM Crash when saving after restore from definition0 z. l4 H3 j% K, b6 W/ d3 D
1237862 CONSTRAINT_MGR OTHER A way to remove the RAVEL markers from the Constraint Manager. ' Q, ?( l7 P. u Z. t1238852 CAPTURE GENERAL signal list not updated for buses) O3 Q- F/ Z6 C P* M6 l8 \8 g
1238856 FSP DE-HDL_SCHEMATIC FSP schematic generation crashes % w7 P- A& t( n; S6 c% x1239079 ALLEGRO_EDITOR INTERACTIV The 16.6 Padstack > Replace function leaves old padstack. . P8 U" A( c7 I/ x+ ?& B7 j* U) C% R1239706 CONSTRAINT_MGR ANALYSIS The reflection result on a differential signal in the CM when Measurement location is DIE ; P2 o/ F3 T2 t8 R) |& B( n2 W1239763 PSPICE PROBE Cannot modify text label if right y axis is active5 |6 _; N( e' X8 z
1240276 ALLEGRO_EDITOR GRAPHICS Printing to PDF from SigXp is giving unreadable images 2 l" R. _6 z# ~% @" g! F1240356 CAPTURE IMPORT/EXPORT Can縯 import SDT schematic to Capture.$ p v4 z! ^" Z% m+ _4 a
1240502 F2B PACKAGERXL Corrupt cfg_package does not stop PackagerXL from completing 0 a" _! a7 G A: V8 t+ j6 J1240607 ALLEGRO_EDITOR OTHER Footprint of screw hole got shift in DXF file6 q2 }7 b( A8 l+ v4 z
1240670 ALLEGRO_EDITOR PLACEMENT Select multiple parts and Rotate makes them immovable' h T5 B4 `8 p( m/ q8 ^
1240773 CAPTURE DRC DRC check reports error for duplicate NetGroup Reference in complex hierarchy 4 g! Y+ n$ j! d0 S6 |1240845 SIG_EXPLORER EXTRACTTOP Narrowband via models for Mirrored BB Vias not extracted in in the interconn.iml and this gives bad ringing in waveforms ; \( p i J, p" U) _1241634 ALLEGRO_EDITOR OTHER Netshort for pad-pad connect not working; v7 T! B- [2 X4 f7 ]
1241776 CONCEPT_HDL CORE In hierarchal design not all pages are getting printed.' X W1 I5 R# |% d( Q) d& O
1241788 CONSTRAINT_MGR CONCEPT_HDL Issues with changing focus in Constraint manager using keys on keyboard4 M* C1 W. h" y& T
1242683 ALLEGRO_EDITOR INTERACTIV Color View Save replaces file without warning / t) U& b N- x, F+ `1242818 ALLEGRO_EDITOR PLACEMENT Placement edit mirror option places component on wrong side 4 v$ @& k" e, t2 L8 c3 h1242847 ALLEGRO_EDITOR GRAPHICS Need an option to suppress Via Holes in 3D Viewer" D% S' p6 R" d3 L4 k
1242923 ADW COMPONENT_BROWSE UCB reports Missing From DB only after selecting the Row in the search results/ p- \/ |$ Q8 ]: M, g
1243609 CONCEPT_HDL CORE autoprop for occurrence properties; y# V) P8 F7 Z% x
1243682 F2B DESIGNVARI after undocking variant icon cannot be redocked back to GUI 5 L& q, o9 M% v5 N- d1 N1243686 ALLEGRO_EDITOR GRAPHICS Invoking Edit->Text, the infinite cursor disappears until edit mode is changed. , `/ o) z, i. ^+ C" t+ e1243715 CAPTURE PART_EDITOR Pin name positioning get changed after rotating or mirroring, }7 ~% N. i! j# M
1244945 CONCEPT_HDL PDF PDF Publisher does not include image when file is not located in the root folder - y* \2 |1 y: @- x9 ^9 {$ Q1245568 CONCEPT_HDL CORE Dual unselect needed for wires attached to other net/source and property is not deselected when component is+ e- O- ` }1 `! \ n
1245819 F2B PACKAGERXL wrong injected properties information passed during packaging of the design " q* M; P, v3 d& Q: X# a1245916 SCM CONCEPT_IMPORT Where does the folder location reside for DEHDL imported blocks? 1 o+ `( s. `5 U$ u9 @# L1246347 CONSTRAINT_MGR CONCEPT_HDL DEHDL crash if environment variable path has trailing backslash character 2 w# K" s% @) |. ?1246896 ALLEGRO_EDITOR DFA DFA_UPDATE on Linux reports err message if the path has Upper case characters \" t9 _+ V# }% {6 X- v
1247019 SIP_LAYOUT DIE_STACK_EDITOR SiP Layout - refresh/update symbols is mirroring the assembly drawing data on DIE that is placed ChipDown , q1 i- Y: b# c; M% w# j2 [& H1247037 CAPTURE LIBRARY_EDITOR Copy & Paste of library parts resets pin name and number ) r; q' Y4 i3 J3 N1247089 CONCEPT_HDL CORE Group Align or Distribute > Left/Center/Right crashes DEHDL 1 m, m. A& `; n+ ^6 s1247163 CONCEPT_HDL PDF Physical Net Names in PDF not maintained) l3 \3 [$ i$ D
1247462 CONCEPT_HDL CORE Text issue while moving with bounding box ! t; ?$ g% ?( T) r/ T( |1247464 ALLEGRO_EDITOR UI_FORMS When using the define B/B via UI the end layer dropdown arrow is partially covered+ k( `1 h! S% |. d9 P8 B/ A( n
1249063 CONCEPT_HDL CONSTRAINT_MGR CM and SigXP doesn縯 respect PACK_IGNORE at components& _; ^/ _/ J5 Y% b- k5 e" ^
1250270 CONCEPT_HDL CORE Part Manager Update places wrong parts% U* y* V7 R9 `* C; g
1251206 ALLEGRO_EDITOR ARTWORK Aperture command cannot create appropriate aperture automatically from design. ' v- q7 H" m# G1251356 ALLEGRO_EDITOR INTERFACES Some STEP models are missing in 3D view of footprint, although all components have STEP model mapped in footprint " s _% o+ Z y# X; f1251845 ALLEGRO_EDITOR EXTRACT Crosshatch arcs do not extract correctly! g9 |* b- \7 i0 E
1252143 APD OTHER When using the beta "shape to cline" command the tool is removing the shape instead of converting it.2 M+ U, O. A/ g
1252737 SIP_LAYOUT OTHER SiP Layout - Option to create shapes from Pins for WLP wafer level packaging technologies* Q) _2 |: n, I% b; q f5 F
1253424 SCM SCHGEN Export Schematics Crashes System Architect 3 ^% |7 r% W: g3 {1253508 ALLEGRO_EDITOR INTERFACES Bug - Export IPC2581 exports Crosshatch shapes as filled7 k! ~- W5 m* n/ ?, e3 J) F
1253554 SIP_LAYOUT OTHER SiP Layout - Add Netlist Spreadsheet export to SiP layout to help with connectivity auditing% |9 w j+ Z( Y# {
1254578 SPIF OTHER Specctra crash with Error -1073741819 for Auto router 5 m+ M' C8 O, G( ~2 l" p1254637 ALLEGRO_EDITOR DRC_TIMING_CHK adding nets to a net group causes constraint assignment error + r9 X. `" e- |$ |2 j8 } ]1254676 GRE IFP_INTERACTIVE Rake Lines disappear when Auto-Interactive Breakout is enabled.8 }; r/ {* M0 p) L' v% H+ J
1255067 SIG_INTEGRITY REPORTS Allegro hangs on Net Parasitc Report generation , C9 H! i5 U1 z+ \1 J1255267 ALLEGRO_EDITOR SKILL axlDBGetPropDictEntry does not return a list of all objects 5 E- W, i! N2 m/ D3 C& A: t: i1255383 SIP_LAYOUT IC_IO_EDITING cant move bumps or driver in app mode 2 h6 F3 T: }) D1 h1255703 ALLEGRO_EDITOR SKILL axlCNSSetPhysical and axlCNSGetPhysical return nil if a constraint set name is provided9 E4 C4 s- R+ T
1255759 ALLEGRO_EDITOR INTERFACES Change the silkscreen OUTLINE from layerFunction DOCUMENT to layerFunction BOARD_OUTLINE2 ?+ {; D' L1 `7 ~7 \% L: B2 b7 U
1256457 CONCEPT_HDL CONSTRAINT_MGR Extracting a XNet from CM crashes the tool$ i! {( [6 ?1 G7 n& b. K
1256597 GRE CORE Allegro GRE crashes while running Plan Spatial, on a particular design * R+ x$ [/ g: ?1 Y5 c1256650 ASI_PI GUI PFE - Cannot generate model file error when using company decap library1 f, }- I3 P5 d6 Q# b
1256837 SIP_LAYOUT DIE_EDITOR Open and close of die editor takes too long . v# |8 s! l1 w8 |5 B$ i1257732 CONSTRAINT_MGR OTHER Bug - Export Analysis Results in CM makes Allegro crash : \1 I( |3 ?7 D0 b3 ^5 I# h3 h- O1257755 ALLEGRO_EDITOR OTHER Editing time in Display > Status seems to be logging wrong time ' y# H# v' |% r5 P0 O* W/ o' ^3 C1258029 APD WIREBOND The bondwire lost after import the wire information) S; Q) X4 Z7 v/ y* ?: f/ e
1258979 APD NC NC Drill: There is difference of number of drills.0 u: o0 U/ W! Q4 m/ r, ~. ]
1259484 SIP_LAYOUT OTHER SiP - calc min airgap calculate minimum airgap beta feature improvement, ?6 A6 y# G, f! j& ]$ h
1259677 CONCEPT_HDL CORE hier_write -forcereset cause component prop change.$ X. |6 I. j1 q. O$ f
1259913 ALLEGRO_EDITOR UI_FORMS Unable to save setting of "use secondary step models in 3D viewer"- U! A! R# R0 [0 N8 ]8 j0 ^' E
1261758 ALLEGRO_EDITOR EDIT_ETCH Auto Interactive Delay tune (AiDT) is deleting clines 8 H. _! D$ ^: n' |# |1262543 ALLEGRO_EDITOR MANUFACT merge shape results in moved void" O5 @5 L3 g$ S) Q( X
1264767 ALLEGRO_EDITOR DRC_TIMING_CHK XNET is choosing to resolve to a different name from 16.5 to 16.6 and is causing constraint loss 7 X7 G v1 F" d8 n7 h 6 U# p B" \% g作者: pzt648485640 时间: 2014-4-26 16:28
谢谢楼主分享作者: qq371833846 时间: 2014-4-26 23:23
刚刚弄了26的.郁闷作者: 小明网我的天堂 时间: 2014-4-26 23:36
这么快！坑爹！作者: sunyooh 时间: 2014-4-26 23:49
不能下载。。作者: wanily 时间: 2014-4-27 00:06
谢谢分享作者: tubegong 时间: 2014-4-28 09:50
下不了作者: tubegong 时间: 2014-4-28 10:43
下不了，请楼主将其放到网盘好吗，谢谢作者: szhot 时间: 2014-4-28 11:56
能放在在百度盘吗？作者: dsws 时间: 2014-4-28 12:57
