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标题: 关于JTAG参考电压VREF [打印本页]

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作者: ych634227759    时间: 2014-4-15 18:32
标题: 关于JTAG参考电压VREF
诸位好，想问下，JTAG的参考电压可以接1.8V吗？我的设计是这样的，FPGA的BANK 0的VCCO是1.8V！

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作者: lvsy    时间: 2014-4-16 09:27


可以！对于Altera的FPGA，JTAG接口不是VCCIO供电的，它有专用的电源VCCPD，VCCPD的电压不能小于VCCIO。

2 t# X" g9 G# u如果是xilinx的FPGA，7系列也是可以的。设置CFGBVS管脚，接GND。
; a1 {# O; F' H& D0 b& q5 ~% l" I
The 7 series devices support configuration interfaces with 3.3V, 2.5V, 1.8V, or 1.5V I/O. The
configuration interfaces include the JTAG pins in bank 0, the dedicated configuration pins
in bank 0, and the pins related to specific configuration modes in bank 14 and bank 15. To
0 Y1 E6 s: Q! Z1 e& w+ Q2 esupport the appropriate configuration interface voltage on bank 0, bank 14, and bank 15,
8 Y# E& M- b; r: othe following is required:
4 d* L: Y8 d$ _6 W& Z• The configuration banks voltage select pin (CFGBVS) must be set to a High (VCCO_0)
or Low (GND) in order to set the configuration and JTAG I/O in banks 0, 14, and 15
for 3.3V/2.5V or 1.8V/1.5 operation, respectively. When CFGBVS is set to Low for
* I' P, f" M$ H" k6 \- a1.8V/1.5V I/O operation, the VCCO_0 supply and I/O signals to bank 0 must be 1.8V
+ Y1 `, |0 S5 x3 K: a! H( }5 q(or lower) to avoid device damage. If CFGBVS is Low, then any I/O pins used for
7 o( v# [# E9 _$ E7 Econfiguration in banks 14 and 15 must also be powered and operated at 1.8V or 1.5V.
5 J% W1 d5 y. K6 r# _9 ~3 e

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作者: ych634227759    时间: 2014-4-16 11:11

lvsy 发表于 2014-4-16 09:27
( D7 j4 `/ A  x0 W/ Y可以！对于Altera的FPGA，JTAG接口不是VCCIO供电的，它有专用的电源VCCPD，VCCPD的电压不能小于VCCIO。
0 U1 q9 q( ~7 y2 _4 \% i
4 I) L: K7 \+ P" g  \3 K ...

0 l# V1 D2 c% U2 r* E* @三克油啦！

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作者: ych634227759    时间: 2014-4-16 11:12

lvsy 发表于 2014-4-16 09:27
/ [* S% |/ o; P& R* q) w可以！对于Altera的FPGA，JTAG接口不是VCCIO供电的，它有专用的电源VCCPD，VCCPD的电压不能小于VCCIO。

4 u2 ?+ ]* q- G! c0 Q ...

* F( ^+ f# b) ?7 g" ?' q你也在搞7系列FPGA吗？有空交流下啊，我QQ:634227759！感激不尽！

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