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标题: Hotfix SPB16.60.008已经发布，附bt种子，求网盘连接 [打印本页]
作者: Jason022    时间: 2013-5-2 11:34
标题: Hotfix SPB16.60.008已经发布，附bt种子，求网盘连接
本帖最后由 紫菁 于 2017-9-14 14:38 编辑
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5 _, z, ]* c" @/ {1 \  `3 o1 oDATE: 04-26-2013 HOTFIX VERSION: 008/ {4 h/ t  \9 R* r
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CCRID PRODUCT PRODUCTLEVEL2 TITLE9 Z4 I4 I! t! G9 ~% j; X7 R
===================================================================================================================================
- j- b6 k# L4 o( {876711 ALLEGRO_EDITOR GRAPHICS Mouse wheel will only zoom out using Win7 64 bit
9 P0 f6 T' ?8 v8 A5 ~1080386 CONCEPT_HDL CORE Unable to highlight netclass on every schematic page using Global Navigation
6 a& N7 A$ K7 p; r1082587 FSP FPGA_SUPPORT Support of Xilinx's Zync device. }- f) c) `2 x6 z
1105286 FSP DE-HDL_SCHEMATIC FSP crashes while creating board in Schgen if it does not find any available license.
% \6 i% |( s* b' V6 U  }9 T1105461 ALLEGRO_EDITOR DRAFTING Dimension Enviroment deletes Diameter symbol whenever we add anything to Text section
( B) L$ D* h- C1105504 PCB_LIBRARIAN CORE PDV on Linux Move pins by arrows does not stop when release arrow key but keeps on running$ z0 b' I2 O; P2 ^6 \8 D
1110126 ALLEGRO_EDITOR GRAPHICS Display Hole displays strange color.
6 y0 z, C/ W% P) ?- R+ n1113518 CIS DESIGN_VARIANT Incorrect Variant information in Variant View Mode for multi-section parts with occurrence
. Y" Z) `6 w- w* O. y1117580 SCM OTHER DSMAIN-335: Dia file(s) error has occurred.% ~# |0 ~6 m9 r+ \4 M
1117845 FSP DE-HDL_SCHEMATIC Schematic Generation fails without a reason" T# D: c6 q& |* \/ `$ ?9 i( V
1119864 FSP TERMINATIONS Auto-increment the pin number while mapping terminations.
6 N, {' V0 f$ t5 f: c/ N1120250 ALLEGRO_EDITOR MANUFACT Why is the parameter File altered?, o  D' p3 {3 t1 U" |
1120414 ADW LRM TDO Cache design issue* K3 Z6 S/ f4 |- D, @/ n: H3 V' {
1121044 SIP_LAYOUT SKILL axlDBAssignNet returns t even when no net name is assigned to via
4 H: Z1 k4 T, h/ ^' l# B) c1121148 ALLEGRO_EDITOR PLACEMENT Ratsnests turns off when moving symbols with Net Groups
" w$ I9 W' u, J* b1122440 ALLEGRO_EDITOR DATABASE Cannot unlock database using the password used to lock it
' f) w& c$ x& s" V) C1122449 ALLEGRO_EDITOR DRC_CONSTR Uncoupled length DRC for diff pair shows different actual length value between show element and CM.1 M2 F1 Y/ L, x  U% g# n$ |- [
1122990 ALLEGRO_EDITOR INTERACTIV RF PCB Symbol which is part of Reuse Module cannot be replaced
1 M. D1 F, X$ O. H1 ?; }- z1123083 ALLEGRO_EDITOR PLACEMENT Saving after mirroring a Place replicate mdd create a .SAV board file.7 }3 b. a6 e0 A4 {
1123257 SIG_INTEGRITY SIMULATION some of the data signals at the receiver are not simulatable2 }( Q9 u6 Z1 N2 G% n( Z# N
1123764 CONSTRAINT_MGR OTHER Allegro crash while importing DCF file7 k7 f8 i* t% S0 V+ ^
1123816 CAPTURE PART_EDITOR Movement of pin in part editor1 }8 S" ~' d) \" u
1124183 ALLEGRO_EDITOR EXTRACT Output from EXTRACTA gets corrupted with refdes 50+ E1 @' m( D6 s- F% p+ K1 `
DATE: 04-13-2013 HOTFIX VERSION: 007
% h  A) z, z. l) z! _2 \7 s===================================================================================================================================. M5 ?8 i/ a- [; r6 c  e
CCRID PRODUCT PRODUCTLEVEL2 TITLE! v# t. Z7 R  \6 ]1 E
===================================================================================================================================" P% {) L+ _! O* w- ^. Y& u
1107397 SIP_LAYOUT PLACEMENT Place Manual-H rotates die6 b$ C2 K& y$ F4 m: ~
1111184 ALLEGRO_EDITOR PLACEMENT NO_SWAP_PIN property does not work in 16.6, o7 P% C" q7 m$ G/ {
1112295 APD DXF_IF Padstacksї offset Y cannot be caught by DXF.
) ^; a' H. O( @7 F6 ]1113284 ALLEGRO_EDITOR INTERFACE_DESIGN Rats disappear after moving components! S! J: F  @* N- @6 s+ V9 m: Q% G
1113317 CONCEPT_HDL SKILL skill code to traverse design not working properly
3 E, ?- V  a* y. f, S( z* Y1115491 ALLEGRO_EDITOR SKILL telskill freezes command window: q# Z& W! ~0 J  Y: c) p
1115625 ALLEGRO_EDITOR SKILL Design extents corrupted when axlTrigger is used.
4 h1 L9 g6 C+ i' B0 ]+ P! D1115708 ALLEGRO_EDITOR INTERFACES Export DXF is outputting corrupt data on one layer.
  h; d+ {0 m9 B4 p& h: L6 Z1115850 ALLEGRO_EDITOR GRAPHICS Text edit makes infinite cursor disappear6 H  J; K' n$ d
1116530 ALLEGRO_EDITOR MANUFACT Import artwork show missing padstacks; P- n1 r7 H5 e$ P3 ^
1117498 ALLEGRO_EDITOR DATABASE Why does dbstat flag LOCKED?
0 Q' n3 {4 s! n/ E! [5 ]1118407 SIP_LAYOUT DIE_EDITOR net connectivity is getting lost when running die abstract refresh
! z) g" w9 \& a  i9 f% F: X) C8 f1118413 SIP_LAYOUT DIE_EDITOR pin number is getting changed when running die abstract refresh
; J$ G# i0 x& {+ V. D4 ^! y) ^1118526 CONCEPT_HDL CONSTRAINT_MGR Upreved design now has Constraint packaging errors) _  ?, x! \) l# R
1118830 ALLEGRO_EDITOR SHAPE Performance issue when moving/refreshing shapes in 16.6
, n+ V5 l2 Y/ T$ H; {1119784 ALLEGRO_EDITOR INTERACTIV ipickx command gives drawing extent error inconsistently
2 X* u, p5 N% C, O* v8 p5 |. u1120469 SIP_LAYOUT DIE_ABSTRACT_IF use different padstack for different, but look-alike bumps
& b# w3 ?+ L& ?) t2 ]) A# t& D1120669 CONCEPT_HDL CORE DEHDL crash on multiple replace of hier blocks. t; L; n1 v" b! p5 Y
1120810 ALLEGRO_EDITOR EDIT_ETCH Cannot slide cline segment.6 m( ?! }- k8 W7 y
DATE: 03-29-2013 HOTFIX VERSION: 006
& S% F* |( M" S& M8 N+ u# }  q===================================================================================================================================
) A& n, q0 B1 K5 G# F% }CCRID PRODUCT PRODUCTLEVEL2 TITLE
5 Z3 }3 M1 b# r  w6 y===================================================================================================================================
- J1 [; L) {% A% s110139 FIRST_ENCOUNTE GUI Error in Save OA Design form/ b; T' L, X1 D, X! E& ^4 Q
625821 CONCEPT_HDL CORE publishpdf from command line doen not work if temp directory does not exist.# c: r/ O% p; v, ?2 k7 u7 Q3 v; \7 n/ J
642837 PSPICE SIMULATOR Option to disable Bias Points when Primary Analysis in Active Simulation Profile is DC Sweep
+ N9 v9 U# u7 i) ~. }650578 ALLEGRO_EDITOR SHAPE Allegro should do void only selected Shape without "Update Shape".% _# C7 f' b1 m! x# C0 I
653835 ALLEGRO_EDITOR MANUFACT Double character drill code overlaps with "cross" in NC drill legend
  T* v* m; z/ o+ x/ ?/ h8 @9 x687170 SIP_LAYOUT DRC_CONSTRAINTS Shape to Route Keepout spacing DRC display incorrect4 ?6 E& s  a& m# \, u% K
787041 FSP DE-HDL_SCHEMATIC FSP Refdes inconsistency when gen schematics% C( O- Y( R: E4 J
825813 CONCEPT_HDL CORE HDL crashes when copying a property from one H block to other
* ~7 _1 L. N# S1 f* t5 S834211 ALLEGRO_EDITOR SHAPE Constant tweaking of shape oversize values is time consuming1 z% Y# C. u+ p3 Y0 Z, L
835944 ALLEGRO_EDITOR OTHER Customer want to change for Jumper symbol by other Alt symbol.
' j9 Q5 i+ W8 J" J3 n868981 SCM SETUP SCM responds slow when trying to browse signal integrity( L; c! P/ l8 C8 E5 [. T* K
871899 CONCEPT_HDL CORE 'Multiple:' column of Grid window in DE-HDL option is too wide8 f. y1 |' c8 L# N$ ~$ V0 d
873917 CONCEPT_HDL CORE Markers dialog is not refreshed
5 `" C8 \9 f9 W0 J887887 CONCEPT_HDL CORE Option to find unconnected Pins/Nets with DEHDL L License
. E/ V, g5 t9 W( J888290 APD DIE_GENERATOR Die Generation Improvement
: e% K( k* y/ q* R2 X' J892857 CONCEPT_HDL CORE packager treats R? as a unique reference designator% h6 P. X3 M( |7 ?+ O6 k' Q9 ]
902908 PSPICE SIMULATOR Support of CSHUNT Option in Pspice
* z' z+ e1 P" U- k  v% {' L908254 ALLEGRO_EDITOR INTERACTIV Enhancement request for DRC marker to have a link to CM
( {' @' }9 s( l  m7 M8 [922422 CAPTURE NETLIST_ALLEGRO Netlist errors when using mix of convert and normal symbols
# j+ J5 \. e; i! z$ k, r4 `923361 ALLEGRO_EDITOR INTERACTIV Stop writting PATH variables in env file if no modifications are done using User Preferences: T+ c- p2 S9 n3 c9 e& d5 F: p+ i3 n
935155 CAPTURE DRC No any warning messages listed in the On line DRC window even executed "Check & Save" to on line DRC9 _% K3 t! o1 D3 p+ M) T
945393 FSP OTHER group contigous pin support enhancement8 P* F$ ]/ Y+ O. b% b
969342 ALLEGRO_EDITOR DATABASE Enhanced password security for Allegro database
( h9 `$ ]. s& x# [* L" {, ^1005078 CAPTURE ANNOTATE Copy paste operation does not fill the missing refdes3 P- b- |* r  G) a/ V* O/ Z8 M- q
1005812 F2B BOM bomhdl fails on bigger SCM Projects
2 q: y: E( f2 ]2 H5 P- i1 ?1010988 CAPTURE OPTIONS ENH: ADD ISO 8601 Date Time format to Capture
% A: u6 y9 m+ |) y6 n1011325 ALLEGRO_EDITOR PLACEMENT Placement replication creates modules with duplicate names
* ?4 l0 V! ^/ W, b4 ?! K7 k- ]7 M1016640 ALLEGRO_EDITOR PLACEMENT Error/Warning Message for not finding or unmatched mechanical symbol or fiducials or which are not on a net4 x  `5 O$ L6 ], W0 \* Y& S
1018756 CONCEPT_HDL CONSTRAINT_MGR Match Groups with Pin Pairs are not getting imported into the schematic CM during Import Physical7 `6 u' |- ^; [2 n2 m
1032387 FSP OTHER Pointer to set Mapping file for project based library.' a$ T3 ^. d2 f) A+ U3 }/ F
1032609 FSP IMPORT_CONSTRAIN Import qsf into FSP fails with їLL PLL_3 does not exist in device instanceї
3 C4 V7 P, k2 C3 T: \1040678 ALLEGRO_EDITOR MANUFACT Text spacing is inconsistant for top and bottom SM layer in xsection chart% G8 n& @) _2 W$ M+ g
1042025 APD WIREBOND Order placement of power rings for power/ground rings generation with using Perform Auto Bonding
7 V: u/ N8 B. K' V6 Y/ }1045500 CONCEPT_HDL CORE Why Search results does not display the correct Physical Pages.. F3 f0 |; ~7 I" Z
1047259 CIS EXPLORER Sorting in CIS Explorer is not Numeric even for columns which are of Numeric data type
( ~  S9 a3 D, o$ `6 k. f/ `1047756 CAPTURE NETLISTS Not adding user defined properties in netlist generated by orDump.dll) K# @0 E1 q1 r" f$ i
1052455 RF_PCB DISCRETE_LIBX_2A RFPCB IFF Export to fix port direction for ADS for footprint having the same pin rotation( G4 M% G3 F+ s/ \  `
1054314 CONCEPT_HDL CORE Zoom of custom text is different from other schematic objects0 v. E7 R& E8 m/ j( ?
1061529 CONCEPT_HDL CORE Space can be included in LOCATION value and cannot be checked by checkplus+ k) I4 x; y* L! R3 M2 Q
1064035 CONCEPT_HDL COMP_BROWSER Component Browser crashes on part number search using a library containing >23K parts. d- U! U& l* `% _
1064604 ALLEGRO_EDITOR MANUFACT Enh - Include ability to add slot notes to designs4 V' r0 O0 B- j6 u1 i
1065636 CONCEPT_HDL OTHER Text not visible in published pdf- s* p  b0 X( Q. X$ A  C7 d6 ?
1065843 CIS PART_MANAGER time stamp on library from different time zones triggers part manager lib out of date warnings
6 e% Q7 }; P8 I- F& ?# d' M$ I& U1066701 ALLEGRO_EDITOR OTHER Missing padstack warnings not in Symbol refresh log summary* @' ]8 E# p# M* ]& y
1067283 SCM PACKAGER ALLOW_CONN_SWAP does not work for lower level schematic parts
- z! I+ k6 U% Y/ v1067400 CONCEPT_HDL CORE ERROR(SPCOCD-171): Port exists in symbol but not in the schematic( |1 |* D7 p% a- t! t3 U& y
1068878 CONCEPT_HDL CORE Rotating symbol causes the pin name to be upside down
' X. w" j. F( q- Z6 ?! ?. @1069896 ALLEGRO_EDITOR EDIT_ETCH Cline changes to arc when routing even when Line lock is set to Line 45
4 f: j; D1 B/ k1070465 CONCEPT_HDL CORE Why does ConceptHDL crash on renaming a Port Signal
' z2 L$ j( D$ H: O4 _) F- o1071037 PSPICE SIMULATOR Provide option to disable Index Files Time Stamp Check
- X- p. L# n3 N' ~1072311 CONCEPT_HDL OTHER Schematics are incorrect after importing design.! Y: ]+ j/ ?' A5 c7 ~
1072691 CONCEPT_HDL CORE Customer has the crash from Run Script of DE-HDL 16.51 again(#3)
9 d$ B! Y3 v# Q! f! r1072859 SIP_LAYOUT DIE_EDITOR padstack selection window crash from Die Editing: Component editing of Co-Design Die& i0 s/ n  J: s4 ~, U1 A
1073354 CONCEPT_HDL CORE Bubble defined on symbol pin is not visible on the schematic! H; d5 `* z; m  _) t4 G2 ^
1073837 ALLEGRO_EDITOR GRAPHICS Some objects disappear on ZoomIn ZoomOut
& J# r4 n+ a* B( l/ Q1 [- T& t1074243 ALLEGRO_EDITOR GRAPHICS Allegro WorldView window does not always refresh after dehighlight of objects/ Y/ G' {1 `5 F$ F! X
1074606 ALLEGRO_EDITOR INTERACTIV Enh - Cosmetic change in Filter Option UI of Replace padstack to indicate multiple pin entry format
. b6 c' ^) [- l! T  h: \* \1074794 ALLEGRO_EDITOR REPORTS add commonly reguested via reports to Allegro and ICP reports. Via per net, via per layer per net
( E: ]$ k! W6 t) {/ N1075587 CONCEPT_HDL PAGE_MGMT Unable to insert page in schematic
- i  u9 @9 h* q) Z1076117 PSPICE PROBE Copy & Paste text/label in probe window changes font size and later gets invisible
5 ^" m. u; j$ L7 _& s+ ^1076145 SIP_LAYOUT DIE_ABSTRACT_IF Issue message in Add Codesign and Refresh Die Abstract if Pin Numbers from Die Abstract exceed 31 chars.0 Q5 N2 {+ b0 [, Q$ B
1076566 ALLEGRO_EDITOR EDIT_ETCH Sliding diff pair cline that has a min/max prop rule displays the HUD meter inconsistently.
* P, d! M+ Y& t( L$ z: E+ B- s& Y7 y( E1076604 ALLEGRO_EDITOR SHAPE Sliding via in pad corrupts surrounding shape and generates false DRC Errors( y( b+ O1 B; B/ T; _
1076820 SPECCTRA FANOUT Fanout fails to stack vias in bga pads.: ?$ J7 A- J; s$ Z" I
1076868 ALLEGRO_EDITOR PARTITION Symbols become 'read only' inside a design partition
4 |# G  N8 N: R2 M* E3 t1076879 GRE IFP_INTERACTIVE Plan Column should not be present in Visibility tab for Symbol Editor
1 ^$ m  J, l- Q6 a. m" d9 P  y9 H# W1076898 CONCEPT_HDL CORE User can not increase logic grid size value continuously using Up button on Design Entry HDL Options
3 S1 p9 z: _0 W: n8 v1077026 CIS LINK_DATABASE_PA fonts changes while linking db part in 16.5
6 v9 k8 c+ E; {/ `" A1077187 ALLEGRO_EDITOR DATABASE DBDoctor appears to fix database but nothing is listed in the log file.
3 a4 [  h# Z1 X* H1077527 CONCEPT_HDL CORE ConceptHDL net with name U cannot be found using Global navigate
# p) ]: ?) O6 K7 l2 m1077621 CONCEPT_HDL CORE DEHDL crashes when saving page 3
" |8 ?/ ?! y3 N; u+ _# T" s$ K1078270 SCM UI Physical net is not unique or not valid1 Y/ J) A/ O2 d& [7 b
1079616 CONSTRAINT_MGR CONCEPT_HDL Packager error in 16.5 which is resolved when system is re-booted( P# G  M, g7 y& ~
1079821 CONCEPT_HDL CORE Project Setup does not respect $TEMP variable for temp_dir and creates a directory in project calle
4 ^; v7 `5 R3 h# m1 t1080142 CIS CONFIGURATION peated entries in Allowed Part Ref Prefs- @# W0 o9 Q6 M! x) T! [9 X/ N. o
1080207 ALLEGRO_EDITOR INTERACTIV Separate the 2 types of SOV violations."Segments over voids & Segments with missing plane coverage"
; t1 b1 j/ h* H9 k1080261 PSPICE SIMULATOR Encryption support for lines longer than 125 characters+ ~7 B! B! @" h( v2 c
1080336 CONCEPT_HDL CORE Backannotation error message ehnancement
2 t/ E6 L/ R2 ?8 c3 P1081001 ALLEGRO_EDITOR PLACEMENT Package boundary is not visible while manually placing a component when using OrCAD license% l8 ~, L& ?& U1 s( x9 F
1081237 ALLEGRO_EDITOR PLACEMENT Place replicate > apply does not apply component pin properties stored in .mdd! E. `" y% w$ t6 j* Y1 `
1081284 MODEL_INTEGRIT TRANSLATION Space in the file path will create a bogus error
9 p( B* X2 ~2 F8 ?1081346 ALLEGRO_EDITOR INTERACTIV With Place manual, rotation of the symbol is not updated.
1 a0 n3 m& w% N$ ~1081760 FSP CONFIG_SETTINGS Content of їFPGA Input/Output Onchip terminationї columns resets after update csv command
4 j$ G% _( o# S5 r9 R& ~1082220 FLOWS OTHER Error SPCOCV-353
0 o: K3 C% I7 ]1082492 ALLEGRO_EDITOR PLACEMENT Place replicate create does not highlight symbols.. L7 p6 {: D+ _' p
1082676 ALLEGRO_EDITOR EDIT_ETCH HUD meter doesnot display while sliding / add command/ f& W) }1 _2 W) y
1082737 CAPTURE GENERAL The їArea selectї icon shows wrong icon in Capture canvas.2 l2 f" ]. |4 @5 T2 {$ ~
1082739 CAPTURE OTHER The product choices dialogue box shows incorrect name
9 b' W0 x) \; r, F; H5 P* _1082785 CONCEPT_HDL CORE DE HDL should clean the design with non sync properties in some automated way3 e5 r% k0 a, I' e, a5 t; M( m
1083761 CONCEPT_HDL OTHER AGND text missing from PDF Publisher
2 h  Q# N" C# i( l1083964 CONCEPT_HDL OTHER Do not display Value and other attributes on variant parts which are DNI; g( S$ K+ ?- g. b- W# _
1084023 PSPICE MODELEDITOR Model Editor is slow/unresponsive while opening a Model by double-clicking on .lib file
3 a/ o! w, R% j4 I0 n2 h9 j: s1084178 ALLEGRO_EDITOR SHAPE Spike create on dynamic void.2 }1 @' `( b7 p9 i% B
1084637 ALLEGRO_EDITOR INTERACTIV Enhancement: Pick dialog should automatically be set to enter coordinates* g! E) H- B! v: }
1085010 CONCEPT_HDL CREFER Crefer crashes if the property value in the dcf file has more than 255 characters% L( Y- u$ @  T8 s( j# }8 n
1085347 CAPTURE SCHEMATIC_EDITOR Replace cache results is loss of net graphic changes.
  o1 r6 p& C( r- `1 ]' f3 K5 @1085522 ALLEGRO_EDITOR INTERACTIV Allegro add angle to Display->Measure results' w4 z4 t& C5 _+ ~, V
1085791 CONCEPT_HDL CORE Publish PDF can not output Constraint Manager properties into PDF file.* ~8 S8 w9 F& m; B3 ^
1085891 ALLEGRO_EDITOR INTERACTIV about DRC update$ U) Y9 s5 q3 a/ K" k9 j: h
1085990 CAPTURE DRC B1: "ERROR(ORCAP-2207) Check Bus Width Mismatch" should be INFO
8 U4 Y2 P+ j# |& @: {1086514 CONCEPT_HDL COMP_BROWSER Component Browser placement restrictions not working7 C- [6 S0 ]- w: _6 l' ?) Y* Z( k
1086576 CONCEPT_HDL CHECKPLUS CheckPlus hangs when running Graphic rules.
% J* i9 D0 e% W- f, C" Z1086671 PSPICE SIMULATOR SPB16.6 pspice crashes with attached design
$ }5 _7 Q! {5 v1086749 ALLEGRO_EDITOR MENTOR mbs2brd: DEFAULT_NET_TYPE rule is not translated9 }' S" K- f: O# c
1086886 CAPTURE PROPERTY_EDITOR "Is No Connect" check box in property editor doesn't work for power pins, G6 H* m" D# h4 [5 U0 N
1086902 CONCEPT_HDL INFRA Problems occurred while loading design connectivity, i! t3 M" A8 N) [# t
1086937 PSPICE ENVIRONMENT PSpice Color map getting doubled leading to crash after colors are modified number of times.% g0 V3 b$ U- g7 v
1087221 CONCEPT_HDL OTHER Part manager could not update any parts.8 E2 J8 e0 |$ \+ h
1087223 CAPTURE CROSSREF Cross Probing issue when login into system with user name containing white space
. i, C: a8 i- a; p9 }1087295 SIP_LAYOUT EXPORT_DATA Enable "ackage Overlay File for IC" for concurrent co-design dies too- o' @" L1 B: E) U! n9 h- d! H
1087658 CAPTURE PRINT/PLOT/OUTPU Lower level design pages are getting print twice/ f, L; @' F) o3 J- X) ~8 E0 I
1088231 F2B PACKAGERXL Design fails to package in 16.5
, ~; ~0 k4 i4 k) d  A* e. C  ^1088252 CONCEPT_HDL CORE Menu commands grayed out after Save (with 16.5-s035) when launched from ASA., g8 ?( h% B% L
1088606 ALLEGRO_EDITOR INTERACTIV Pin Number field do not support Pin Range for Symbol Editor
# K! Z, A' ^$ P3 _. P1088983 CONSTRAINT_MGR CONCEPT_HDL Units resolution changed in 16.6 Constraint Manager
+ \- V) ~0 [( ^5 u. N; h1089017 ALLEGRO_EDITOR SHAPE What is the cause of the shape not filling?
/ o. c) T$ f' [0 n/ Q1089259 SCM IMPORTS Cannot import block into ASA design7 Z1 P  s3 @0 x  n* X5 L
1089356 SIP_LAYOUT DIE_EDITOR Distributed co-design : launching die editor taking more than an hour to bring up edit form- n0 H8 T5 Y0 K4 x2 q
1089362 PSPICE STABILITY Pspice crash on pspice > view simulation result on attached project
8 Y1 D7 _1 s) s) t6 H# K9 y1089368 SCM OTHER Can't do Save - cp: cannot stat ... No such file or directory
: W; X( T( {& j+ U) j1089605 CONCEPT_HDL CONSTRAINT_MGR Power net missing from the CM opened from DEHDL Schematic editor.
% z, g8 L4 t3 d4 Z7 T1 p2 x, {1090068 ALLEGRO_EDITOR SHAPE shape priority issue in SPB165
" e2 T+ a: E8 q& W- V6 R- u9 b7 r2 V1090125 ALLEGRO_EDITOR DATABASE Q- The rename resequence log file is not giving correct message.
1 G, {& I3 N2 e1 \7 l1090181 GRE CORE AiDT fails for the nets with errors SPGRE-21 & SPGRE-22
% v; s2 ?5 i/ b  C" G+ ]/ f1090930 CONSTRAINT_MGR CONCEPT_HDL DEHDL-CM does not retain customized worksheet.
4 X) z! i2 u7 P: ?# v4 S1091335 CONCEPT_HDL OTHER Color change cannot remain in some situation.
: J$ ?0 l: @* o4 {1091347 CAPTURE TCL_INTERFACE The Project New link on Start Page doesn't work when Journaling is enabled
: t0 X3 e3 M! ^. t0 K1091359 CAPTURE GENERAL Toolbar Customization missing description3 k' F/ }" ?& N$ Z/ g
1091662 CONCEPT_HDL CORE Incorrect behavior with the SHOW_PNN_SIGNAME directive  C( D- |0 J$ [! t7 j8 V
1091714 CAPTURE PART_EDITOR More than one icons gets selected in part editor at the same time
4 x. a/ E" D8 K0 C/ V$ r; y( G1092411 CONSTRAINT_MGR INTERACTIV In v16.6 CM multiple net name selection under net column is not working as in v16.5
* S- h% F4 l7 T7 A0 o3 `1092426 CONCEPT_HDL CORE Getting ERROR(SPCOCN-1993) while saving a Hierarchical Design
- U+ l  x# c4 C* I3 J1092874 CONCEPT_HDL CORE DEHDL wire short during move not detected with check enabled
: a7 _9 q& ?& |# [5 S# P1092882 ALLEGRO_EDITOR EDIT_ETCH AICC should be removed from orcad PCB Designers design parameters5 J: [8 R1 o4 ^: k2 ]$ h, R
1092918 CAPTURE GENERATE_PART Generate part functionality gives no/misleading information in sesison log in case of error
. D1 ^$ p6 T  `# {4 n1092933 CONCEPT_HDL OTHER PDF Publisher saves the pdf generated in the previous project folder; x+ N) h( a7 S' [+ @
1093327 CONCEPT_HDL OTHER Getting error SPCODD ї 369 Unable to load physical part in variant editor
1 K6 w7 t2 A+ G2 Y1093391 CONSTRAINT_MGR OTHER Setup > Constraints > (domain), doesn't open correct worksheet with OrCAD PCB Editor Professional license.
: t& U& g1 @0 n" M, h. Y1093886 SPECCTRA HIGHSPEED Pin delay does not work in PCB Router when specified in time4 Z. f5 `0 d/ m' L! S8 e
1094223 CAPTURE PROPERTY_EDITOR CTRL+S does not work in Property Editor but RMB > Save.
& p0 s* d1 i& p: H7 Y# F1094513 CONCEPT_HDL CORE How to display $PNN for which SIG_NAME is not visible?- B/ ~9 j3 o+ i% P( h4 _
1094611 CAPTURE PROPERTY_EDITOR E1: 'Tools->Update Properties' should list parts which are present in .UPD, but not schematic* z5 x& T- }0 \8 X1 n
1094618 CONCEPT_HDL INFRA Unable to uprev the design in 16.5
8 b4 l! s+ r: w( O' E$ V1094867 CONCEPT_HDL CORE Page Up / Down Keys are hard-coded assigned to Next /Previous Sheet
* ]9 Z1 q; r* d: C1095449 SIP_LAYOUT LOGIC Allow netlist-in wizard to work on a co-design die
0 f! f! @7 k+ j2 d1095701 CONCEPT_HDL CORE Replace part in replicated block only preserves the Refdes in 1st instance of the replicated block/ u3 Y; P0 q! i  a
1095705 CONCEPT_HDL CREFER Cref_to_list not updated on repl icated blocks in 16.5 release worked fine in 16.3, S, S" N, m# f. O: E5 s- P
1095861 F2B BOM Using Upper-case Input produces incorrect BOM results1 Q  C6 J8 w- N* Q# x; k7 i, d
1096318 ALLEGRO_EDITOR INTERFACES IDF import not removing MCAD tagged objects during import, t1 C) ]9 E9 T$ p% w
1097241 CONCEPT_HDL CORE Concepthdl - zoom in to first object in Find result automatically
# a1 D3 K0 t' k  o$ Y# E3 A0 W! E1097468 ALLEGRO_EDITOR INTERACTIV Need ability to hilight and assign color to vias
* v; L1 c' `+ s) d  \+ q8 s" f1097675 CAPTURE ANNOTATE Enhancement:Option to have Incremental reference Update to be checked at all times when we click on Tool>Annotate1 b  z% d  |$ R( C1 K: r
1099151 SIG_INTEGRITY SIMULATION All Neighbor crosstalk numbers reported when there are no aggressors- L# X: U' }+ r, k5 J) M5 N& {
1099175 CONCEPT_HDL CORE CPM directive that enables the Command Console Window in DE-HDL
1 b  J4 t! U' |2 G" f7 l: K) ]6 F1099838 CAPTURE TCL_INTERFACE TCL library correction utility is not working correctly.
4 p6 M3 L+ C5 l. M& i1099903 ALLEGRO_EDITOR PLACEMENT Mirror and rotating component places component mirror side
! W  T, ~: B: X  K( J' z1099941 ALLEGRO_EDITOR PLACEMENT Problem in rotating bottom components when using Place Manual or place manual -h command5 F7 n/ P  o2 s
1099998 CONCEPT_HDL CHECKPLUS CheckPlus marker file not locating signal when signal name includes the # character.
- C0 c0 k2 q( T2 X& n1100018 CONCEPT_HDL COPY_PROJECT CopyProject gives errors about locked directives# K  v9 ^" I" a. |% }
1100449 ALLEGRO_EDITOR ARTWORK Pad with Net_short property and shorted to shape supressed wrongly with Pad Supression in Artwork0 G% x3 \' k. t! k* a
1100758 CAPTURE LIBRARY Import properties does not update pin numbers of multi section parts
- Q+ b) P, P, X1 x8 L3 q( b1101009 CONCEPT_HDL CORE Cursor stays as arrow after performing File > Save Hierarchy
' V- y7 d# t- J  P1101497 ALLEGRO_EDITOR UI_FORMS Allegro PCB Editor crashes using attached script when working with RF PCB Clearances.
$ R+ |2 y; l+ H! P1101813 SIP_LAYOUT DIE_ABSTRACT_IF Support die abstract properties" O  _( B0 c7 O: V2 X; C
1102531 ALLEGRO_EDITOR GRAPHICS Allegro graphics distortion infinite cursor 16.6
; N! }9 R: w, o9 v% l, S4 H1102623 ALLEGRO_EDITOR SHAPE Strange void around the pad
2 G9 `4 `$ p- w2 s3 e' c( n1103246 FSP FPGA_SUPPORT New FPGA request - Arria V - 5AGXMA1D6F31 - IN2P3
" l% U/ F2 r  {  v3 z0 `! Z. D  E1103631 MODEL_INTEGRIT OTHER Model Integrity license when using orcad1 a8 }+ `7 Y) p& t
1103703 F2B DESIGNSYNC Toolcrash with Design Differences
0 n" I* Y6 c( e$ x  F1103712 CONCEPT_HDL COPY_PROJECT Copy Project crashes on customer design attempting to update symbol view; Q! y- E' V7 b4 X
1104068 CAPTURE DRC "Check single node connection" DRC gets reset in 16.6/ u+ h1 J8 v0 }4 ~9 G  l0 x# t% M
1104121 PSPICE AA_OPT їarameter Selectionї window not showing all the components : on WinXP. s7 d1 L' d' V" Q/ m  F
1104575 CONCEPT_HDL CORE Allign does not allign offgrid symbols correctly' v9 t0 P5 x6 p/ v% O
1104727 CONSTRAINT_MGR SCM Net Group created in sip does not transfer to SCM! N. e6 K; X4 I
1105128 CONSTRAINT_MGR DATABASE Import dcf does not clear out user defined schedule.; i) B5 j/ C: k  |4 ~; h
1105195 SIP_LAYOUT WIREBOND Request that Tack points default to a "fixed" position after Generate Bond Wires.4 {+ K) @/ r1 }6 F, ^
1105249 ALLEGRO_EDITOR OTHER PDF out--- component user defined prop doesn't list the prop selection form# F4 p; m8 w5 k+ a( e! k% n
1105443 PSPICE AA_OPT Parameter selection window in optimizer does not list param part6 l; c4 A7 u  [7 ~9 b  X' [, H
1105818 ALLEGRO_EDITOR INTERACTIV Menu-items seperators are clickable and menu goes away when clicked3 F% F8 a8 Y7 x
1105822 ALLEGRO_EDITOR SCHEM_FTB Netrev failing with compact pin syntax
9 c( @( {% g0 O0 O' v1105993 SIP_LAYOUT LOGIC Import netlist no longer works with co-design die in SiP 16.6
! W. s" ^' X2 @4 E1106332 SIP_LAYOUT OTHER sprintf for axlSpreadsheetDefineCell writes characters in upper case only
7 w* f! P5 Q  B! Y1106786 CAPTURE SCHEMATICS Bug: Pointer snap to grid/ B7 S0 G+ b$ ^: m0 @* t2 ^% m
1107132 FSP OTHER Altera ArriaV (5AGXMA5GF31C4) support.
' n0 U7 s0 l+ f3 F+ @5 w+ c1107151 ALLEGRO_EDITOR ARTWORK Shape filling removed when changing artwork format to RS274X in Global Dynamic Param
) M7 _/ G$ L( ?7 j% `$ n, Y# Z1107237 SIP_LAYOUT WIZARDS Updating a Die using the Die Text In Wizard will error out and not finish
2 z) \4 Q9 ^+ N$ N1 {2 ]% I1107371 ADW COMPONENT_BROWSE ADW preset Warning filter is spelt incorrectly. (Wraning).
6 a4 n6 f0 v5 m2 E0 }1107599 CAPTURE STABILITY Capture 16.6 crash when trying to invoke  L3 a$ a7 S- i  W) y8 J
1108118 ALLEGRO_EDITOR OTHER PDF Publisher pad rotation messed up with flashed pad.
4 l$ f/ i' I2 r, M" O1108574 ADW COMPONENT_BROWSE LifecycleStatus functionality does not work when in Metadata mode. Work correctly in PPT Mode
# C6 N5 A/ t/ U. r1109095 SIP_LAYOUT WIREBOND Bondfinger move in hug mode create drcs
% v! S  p4 w( S( j. {2 D1109113 ALLEGRO_EDITOR DATABASE Allegro Netrev crash with SPB 16.6
6 C1 z8 b0 F0 F, c1109622 SIP_LAYOUT DATABASE In a wirebond design, the ratsnests with 'Closest Endpoint' should not point to the die pins.* O/ i+ u! v' [% y
1110077 ALLEGRO_EDITOR DRC_CONSTR Duplicate Drill Hole DRC's are not shown for Pins overlapped in same symbol unless "Min metal to metal" DRC is turned ON
: J5 S7 I* n1 e1110256 ALLEGRO_EDITOR SHAPE Auto void on dynamic shape is not correct in 16.6
, w1 R) x8 e6 D. a0 V1110264 RF_PCB FE_IFF_IMPORT IFF Import in DEHDL has component offset2 n& j7 m# k. C5 o
1111226 ALLEGRO_EDITOR DATABASE Name too long error with Uprev command when output file name exceeds 31 characters
& w6 C8 e* S9 {; E( D, j% I1111234 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figures triangle, hexagon and octagon in NC drill legend
$ ^% |; Z( n' X7 B, x2 v4 H1112431 SIP_LAYOUT COLOR Frequent crash while working with latest version of CDNSIP
: h( \" e( K9 g5 M! i0 {1 K1112493 ALLEGRO_EDITOR DATABASE Customer does not like 16.6 Ratsnest points Closest Endpoint+ V% n6 ^6 L( h5 ^, ]  @" Z- {
1112774 GRE CORE Allegro GRE not able to commit plan after topological plan% Z1 C, ^% {; {! U' Z& J
1113908 ALLEGRO_EDITOR COLOR Dehilight command fails to remove highlight pattern on a cline, without removing net custom color.
2 U6 d) k1 F; j1 I! e1114815 ALLEGRO_EDITOR OTHER Q1: Switchversion error when reading -fa file/ _% H2 y# w0 c( g1 O" H
1114994 ALLEGRO_EDITOR DATABASE Getting an error after upreving components to 16.6
# w" ]& i( }: w3 H% W
作者: weigaozu    时间: 2013-5-2 13:18
感谢分享，呵呵。
5 H+ g5 y, {6 v' Z; k8 ~( p" ^& t
作者: l81004666    时间: 2013-5-2 23:38
最新的补丁包含了之前版本的补丁内容吗？
作者: lgl2466    时间: 2013-5-3 12:02
作者: Jason022    时间: 2013-5-3 15:23
l81004666 发表于 2013-5-2 23:38
, q, d, R  J7 y8 g$ a5 V3 X最新的补丁包含了之前版本的补丁内容吗？
# {6 P% i5 e! _" U/ W
包含，只需装最新的补丁就行。
作者: l81004666    时间: 2013-5-4 08:56
谢谢
作者: wolf343105    时间: 2013-5-6 08:43
谢谢,ding
作者: wxmcumtb    时间: 2013-5-7 09:25
更新的好快呀。。。。。。。。。
作者: ydw13    时间: 2013-5-14 15:10
0 g4 e; S- r/ L* \6 R" |4 Q* C
感谢分享，呵呵。 百度网盘已经被干掉了
作者: icebluexiong    时间: 2016-2-12 15:42
谢谢分享
作者: wkls201    时间: 2020-2-29 18:10
下来看看~~~~



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