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标题:
求教ALLEGRO 做 database check出错
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作者:
大江奔腾
时间:
2013-4-10 22:37
标题:
求教ALLEGRO 做 database check出错
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********************************************************************************
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* Performance checking for design G:/My project/TSQ-8A/PCB/TSQ-8A.brd
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********************************************************************************
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Ratsnest schedule check
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-------------------------------
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* OK.
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DRC check
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----------------------
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* The number of physical/spacing csets is 0.080000 larger than the number
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of nets Suggest examining constraint model.
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ISSUE: Misuse of the Allegro constraint model such as using a spacing
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cset for each diffpair in the design. Result is system
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performance degradation.
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Constraint region check
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-------------------------------
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* OK.
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Dynamic shape check
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-------------------------------
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* OK.
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Sector table check
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-------------------------------
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* The ratio of design extent to route keepin extent is too large (50.050670). Suggest reducing design extent.
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Constraint set check
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---------------------------------
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* OK.
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NODRC_SYM_SAME_PIN check
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---------------------------------
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* OK.
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Cross section check for bad dielectric constant values
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--------------------------------------------------------
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* OK.
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Padstack size check
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---------------------------------
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* OK.
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2 problems found. 0 maintenance problems found.
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作者:
大江奔腾
时间:
2013-4-12 18:50
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