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标题: 关于锁相环芯片的外部环路滤波电路的问题 [打印本页]

作者: 一只小鱼儿    时间: 2024-9-23 11:24
标题: 关于锁相环芯片的外部环路滤波电路的问题
锁相环芯片的外部环路滤波电路接在了CPOUT管脚,手册上推荐该滤波电路需要靠近管脚放置,想请教一下,外部环路滤波电路如果不靠近CPOUT管脚放置,会有什么影响吗?
作者: 超級狗    时间: 2024-9-23 12:44
本帖最后由 超級狗 于 2024-9-23 12:56 编辑 6 u1 X- Q2 q" v' X

: N8 Q0 P1 V0 y. yCPOUT
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Charge-Pump Output. Connect a PLL loop filter as a shunt C and a shunt combination of series R and C.6 J2 ^, U9 b& S2 [
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作者: 超級狗    时间: 2024-9-23 12:50
踢哀TI)E2E 論壇# ~9 _9 X2 }! h/ m
As for the CPout pin, this is the charge pump output which can range from 0 to 2.5V, as it is powered by a 2.5V regulator. If this voltage falls below 0.5 V or goes above 2.0 V, then the Vtune lock detect will consider this unlocked. When the VCO is calibrated, this targes a voltage of around 1.2 volts, but this voltage can "tune" to adjust the VCO frequency.
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作者: 一只小鱼儿    时间: 2024-9-23 16:12
超級狗 发表于 2024-9-23 12:50
2 g2 w: q0 V* ?! n9 c1 c踢哀(TI)E2E 論壇4 t7 q/ o) b, O
As for the CPout pin, this is the charge pump output which can range from 0 to 2 ...

$ `; C/ w: y* h, D感谢,刚看TI的资料,这应该会对相位噪声有点影响。/ p- N% \. g) q+ x# F* z- ^! w





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