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标题: 秘密的事情，这个不要到处传哦，大家应该知道用法吧？你懂的 [打印本页]
作者: yejingang    时间: 2012-2-21 14:58
标题: 秘密的事情，这个不要到处传哦，大家应该知道用法吧？你懂的

9 |  [( q, O$ d! r) V+ S0 oDATE: 02-17-2012   HOTFIX VERSION: 016
# I( i0 J  b: p; y/ @9 q  \===================================================================================================================================
# t" X* f3 Q0 h( }. O' s$ zCCRID   PRODUCT        PRODUCTLEVEL2   TITLE& A! c8 y/ u6 N/ r1 _
===================================================================================================================================
/ @8 K  ]! J; ^, U9 A, [840105  PCB_LIBRARIAN  USABILITY        PTF subtype is getting changed when Save As option is used in PDV
! ]3 |: ^+ b  G4 l8 Z& z1 o8 O, J873075  PSPICE         PROBE            Decibel of FFT results are incorrect.) [  H  W8 I) L+ ?! m5 F& }
938744  ADW            COMPONENT_BROWSE Need ability to customize shopping cart columns to include any Part property
. U6 O( e5 S. C5 W5 P943003  SCM            REPORTS          The dsreportgen command fails with network located project. H% g* G5 O. Y9 C8 _) ]
961530  ALLEGRO_EDITOR INTERACTIV       The problem of Display measure command- S9 Q5 e. I& p% B
962157  CONCEPT_HDL    CORE             Where is the setting for enabling the Enable PSpice Simulator menu?
9 f5 G2 v  u: ]7 J7 z962206  CONSTRAINT_MGR CONCEPT_HDL      Import physical not passing all constraints from the board to frontend
1 I9 u' d* Q5 G, E; t+ W- z968205  PSPICE         DEHDL_NETLISTER  Change SPLIT_INST property to PSICE_SPLIT_INST for Quad Switch type of design.
% \4 k' |* h: _5 L' W968509  PCB_LIBRARIAN  METADATA         Incorrect pinlist.txt was generated if DIFF_PAIR_PINS_POS/NEG was set.
9 T% b3 G! q. D; f* i969450  LAYOUT         TRANSLATORS      OrCAD Layout to Allegro Translator crashes# F3 o* @: e9 V! j# U3 Y9 X
969997  CONSTRAINT_MGR CONCEPT_HDL      ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance pro~
3 L6 q, Z9 T) e6 Y8 ?4 p: j2 T4 }# _1 v971193  CONSTRAINT_MGR UI_FORMS         Copy and pasting a formula causes the application to crash on windows.* A" f$ N( `3 |4 z% n
971601  CONSTRAINT_MGR CONCEPT_HDL      ERROR(SPCOPK-1053) and WARNING(SPCODD-66) because of directory structure
  [' g9 _/ p7 ?0 U3 W. V973398  CONCEPT_HDL    OTHER            It should be not packaged with error while working the packaging process if the design has a ERROR
& q9 p% X+ c" J3 w. h. r- H! d1 @$ I973859  PSPICE         ENCRYPTION       Pspice crashes with encrypted model( k! g9 o  A  i# n: X/ [/ L/ m/ S
973938  PCB_LIBRARIAN  VERIFICATION     pc.db is missing) [( \5 A( A; _( N' O
974540  CONCEPT_HDL    CORE             Graphics updates are real slow
/ b; F5 x, @  F6 S974791  F2B            DESIGNVARI       Variants are not back-annotating to schematic and turning to ?
5 ^) R- |* ?# p0 g7 C( H974818  ALLEGRO_EDITOR NC               Backdrilling produces 0 plunges yet no errors reported.
% ~, ^6 b, v0 U* x974945  ALLEGRO_EDITOR SKILL            Why is axlPolyOperation is giving different result and not working5 i4 @' b8 }, @/ @' Q
974946  MODEL_INTEGRIT TRANSLATION      ibis2signoise returns the error - Delay measurement fixture must contain V for ECL technology
) j' C3 q2 C/ y9 N975396  CONCEPT_HDL    CONSTRAINT_MGR   Constraints are dropped after migrating from 16.3 to 16.5; j- S  e+ r1 G
975633  ALLEGRO_EDITOR GRAPHICS         'dynamic_layer_visibility' option in 3D Viewer when checked or unchecked should not change (until next change)3 G6 N5 A0 G+ }$ U2 e9 H
975720  ALLEGRO_EDITOR DRAFTING         Datum dimension lines not adjusting to text move9 G+ F6 h5 w& T
975745  ALLEGRO_EDITOR SKILL            cdsServIpc different 16.2 vs 16.5 when Allegro exits5 P) H8 ~! c7 D5 e) c- q- r
976013  CONCEPT_HDL    INFRA            Power pin connection of FPGA symbol is missing in netlist.
! M, ?; V8 V0 Q( l( X976058  CONCEPT_HDL    COPY_PROJECT     SCM Copy project does not create the con and dcf files in tbl_1 views
$ Y# y5 B( Q* w0 [  X+ E* U# V$ c976073  CONCEPT_HDL    COPY_PROJECT     All the constraint data is lost in the SCM copied design' A4 k! H- d  ^. F$ T4 Y- z3 E& {0 v
976160  CONCEPT_HDL    CREFER           Cref fails due to some Caeviews error in the design
* a7 E2 o' k( S( q' `1 m976204  ALLEGRO_EDITOR DRC_CONSTR       Application falsely reporting Mechanical Pin Antipad to Shape Spacing DRC
  e& g+ Y: V: v, s* L# [3 N) k  b976448  F2B            PACKAGERXL       ERROR(SPCOPK-1069): Invalid POWER_GROUP property value
  W& m1 J" r! W8 F, _976521  ALLEGRO_EDITOR DRC_CONSTR       multi-thread update DRC causes the application to crash' X: L1 @1 l1 `/ k: N0 `2 U
976838  SIG_INTEGRITY  OTHER            Unable to create XNET for highlighted nets on attached database even after assigning proper Signal Models.1 [. a  M7 j; _' W- Y& @$ L' F
977517  F2B            PACKAGERXL       Export physical fails after update to 16.5 from 16.36 K4 ]2 H: t3 v) B
977902  ALLEGRO_EDITOR DATABASE         generate module is crashing allegro8 u1 s+ k7 r- w% a7 h8 f6 c/ d
978652  ALLEGRO_EDITOR PADS_IN          PADS_IN fails with ERROR: Finished with errors.
7 o/ {+ G% \+ @8 f& I978744  APD            DEGASSING        Some shapes will not DeGas on this design6 Y7 U# K) ]1 D) i
979940  SIP_LAYOUT     OTHER            SiP Layout Leadframe autobonding with profile selection
7 r; q& u, g' T  F/ l# \, P981699  CAPTURE        HELP             Start Page still shows Hotfix 14 after installing Hotfix 15
7 {) g8 s5 G/ B+ X
0 M! v! `, t, O5 WDATE: 02-03-2012   HOTFIX VERSION: 015
6 A8 n5 b  G8 |& Z! A===================================================================================================================================1 V0 e( }' F* V, [
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE, B+ c1 a7 ~% v. t, ?
===================================================================================================================================& {5 ]$ K& e6 \
871567  CONSTRAINT_MGR SCHEM_FTB        Ability to filter out Single Node Nets from Constraint Manager4 j, K# N2 u/ ^! X* P, F
921436  ALLEGRO_EDITOR MANUFACT         Change in 'decimal place' for new dimension changes the already placed dimension! H: s7 K2 s- U/ _) {/ W: G
941433  CONCEPT_HDL    COPY_PROJECT     16.5 Copy Project should warn if trying to copy a 16.3 design5 L* e/ d. m! t+ F7 C
954375  ALLEGRO_EDITOR MANUFACT         Change dimension accuracy for few instaces of associative dimensioning2 h- r( x$ L3 f% w! U  \3 C' }
961646  PDN_ANALYSIS   EMVIEWER         EMViewer Help > About shows wrong version
7 g9 u* {3 H$ X, T) v964912  CONCEPT_HDL    COPY_PROJECT     ASA project crash after using copy project
* U3 _- f  m& a/ h967223  ALLEGRO_EDITOR MANUFACT         Bug:Oval slots orientation in one direction only, j( j7 n/ V* C8 @5 y  L
968865  SIP_LAYOUT     DIE_ABSTRACT_IF  load of die abstract fails due to differences between component and symbol
2 H/ A+ \, d  @# ~969485  ALLEGRO_EDITOR SHAPE            Shape does not update correctly in 16.5
' h8 |* d0 Q# m! d% z970331  CONSTRAINT_MGR ANALYSIS         Impedance worksheet shows a zero value for impedance; \) _, O6 \9 a6 ]2 S) e) o! Q9 G/ H
970600  SIP_LAYOUT     SYMB_EDIT_APPMOD Option in Die Editor to be able to "physically swap" pins, b) o4 K$ F  K( A# \
970910  F2B            PACKAGERXL       Our customer has problem with pin color after pxl 16.5.4 s$ A( {; I6 w1 Z, b2 P6 z
970970  SPECCTRA       FANOUT           Fanout Vias is placed far away from decaps and does not change the Fanout length even when max_length is reduced., c8 J/ O; ~0 d6 J
970985  SIP_LAYOUT     OTHER            Importing a .spd2 database file using NA2 will cause the APD/SiP tool crash
1 O% W  j9 r! G1 ~8 w971757  CONCEPT_HDL    INFRA            Crash while Saving/Packaging the Design' _, }4 E" F, h4 U& Q6 B
971923  ALLEGRO_EDITOR MANUFACT         Allow to change decimal accuracy for dimension instances8 t" S; l7 W$ t, f
972568  CONSTRAINT_MGR UI_FORMS         Tools >Excel missing from CM( J. I# T& I7 _" Q  g; o
972821  CONSTRAINT_MGR CONCEPT_HDL      connectivity server warning: Unable to add property WEIGHT
% E) T+ y; j( D- t$ k" q973185  SCM            CONSTRAINT_MGR   ASA2 block not seeing all instances in a package.
) I: v- Z) {1 e- I973211  ALLEGRO_EDITOR INTERFACES       IDX Object Type Change not recognized
7 z: F% \" m7 e' n973214  ALLEGRO_EDITOR INTERFACES       IDX import package keepout height value change assigns incorrect value
6 K+ k' \) `3 D9 O2 u3 |973384  CONCEPT_HDL    CHECKPLUS        The multiple SIG_NAME has to be occurred an ERROR at the SPB16.5.
( v. F3 r- f& X973514  SIG_INTEGRITY  OTHER            Mapping error when Ecset is updated to constraint manager from extracted net5 v7 i( b0 x- A9 d" m) P& H
973950  ALLEGRO_EDITOR SHAPE            Update to smooth crashes application
" @. W& B/ S4 p9 b$ E974533  SIP_LAYOUT     OTHER            Crashes in Edit > Die Properties and obviously has a setup problem.$ n! M' c, @% _8 u- T; s/ L6 p
974809  ALLEGRO_EDITOR SKILL            argument available for hiding a property with function axlDBCreatePropDictEntry is not working7 q1 S+ o" s7 [6 C5 H
976179  INSTALLATION   ISR              Installation of ISR S014 to 16.5 on windows is breaking the documentation index+ t# Z( a, ^' Z% d) z
2 t$ q* B0 P. n* e8 o; h6 D
DATE: 01-20-2012   HOTFIX VERSION: 0143 ?8 U3 ^. U* M* f3 @; ^3 n2 }
===================================================================================================================================
; X6 ~# f4 B6 e! F" ~9 Z# `CCRID   PRODUCT        PRODUCTLEVEL2   TITLE" W) t) w2 ~! X& F# [
===================================================================================================================================# A" d3 z+ E* Y+ @6 c2 T
733285  PSPICE         SIMULATOR        Enhancement:In server-client installation use existing index file from server" h* h4 p" I' S
941020  SIP_LAYOUT     OTHER            Soldermask enhancement( [3 R+ i6 |2 c5 b9 t
946407  CONSTRAINT_MGR TDD              When is it safe to open a 16.5 design in 16.3?1 P" }, F4 ]0 p1 R3 p
953067  CONCEPT_HDL    OTHER            Variant Editor "Error/Warning messages" form is unusable
  f6 R) ]* `/ p+ ^954818  CONCEPT_HDL    COMP_BROWSER     Replace button turns to Add in component browser when a component replace is done on the schematic
, ?& b6 P+ M/ A) t7 e( T4 L1 ~8 J956450  ALLEGRO_EDITOR DRC_CONSTR       Analysis always shows analysis failed in uncoupled length in some diffpairs
, k5 p( E+ v' m* \7 e8 c) s958259  F2B            DESIGNSYNC       ds.exe crashes on a big design when accessing the design from network drive
# u* g8 {  V6 B; S5 M: b) `& k958395  ALLEGRO_EDITOR SHAPE            shape voids won't merge1 E/ t7 l: U- }. D4 k0 _6 a
959212  MODEL_INTEGRIT PARSE            Attempting to use "Mark qualified" option on DML File results in dmlcheck and Modelsim wanrings.
* ?3 o  }" N0 n  G959940  APD            AUTOVOID         Void all command gets result as no voids being generated., G: l; k. S( K- \9 `5 N
960252  PCB_LIBRARIAN  CORE             Splash screen in PDV prevents showing error message
( C- {9 \8 g$ H5 H5 F, |9 \0 z961634  PDN_ANALYSIS   EMVIEWER         Cannot launch PDN EMViewer from withing PCB SI: o- X, W4 ^1 d' T. ]( h# U, z3 L
961645  PDN_ANALYSIS   EMVIEWER         Standalone EMViewer will crash when opening any result file in the form of *.emv file.& U- {0 W' g' u. e. a
961700  ALLEGRO_EDITOR SHAPE            dbdoctor reports ERROR(SPMHUT-144): Illegal arc specification- R- |; h# P1 G' n6 _& V
961733  ALLEGRO_EDITOR SKILL            Allegro crashes.  Appears to have a memory leak.
- [" ?  u% A+ K& c: w3 w961758  ALLEGRO_EDITOR DRC_CONSTR       DFA check produces no DRC when the dfa bounds are not a rectangle." K# ^$ g, P. w% M
961887  CONCEPT_HDL    CONSTRAINT_MGR   Match Group created from ECSet cannot be deleted in the same session of CM/ h  ~" q  N, Z* i* c1 y6 G4 z
962552  APD            EDIT_ETCH        BUG:APD crashing when we try to slideget information but move works fine1 P, C& v1 {  j3 q1 P. D, @
962869  CAPTURE        STABILITY        Capture crashes after RMB click on rotated parallel wires" |8 s  J+ \+ t8 |4 _
963232  CAPTURE        MACRO            Macros not being played in Windows7( u% @1 u* U$ h- ?3 b
963300  ALLEGRO_EDITOR DATABASE         Create > Module crashes in 16.5 but not in 16.3
% ~) G( j: @5 G: z( I, k963651  CONSTRAINT_MGR CONCEPT_HDL      ECsets are renamed after packaging on linux/ M3 ^$ \( Y% Q$ ?/ ~
963663  CONSTRAINT_MGR ANALYSIS         Q- Why the customized worsheet for Diff pair Impedance not analysing at all for this SIP design
1 j- |  T7 n. c5 q- n963715  SIG_INTEGRITY  OTHER            Application only adds the bottom conductor thickness for the via z-axis length
' U' |/ n9 q% a4 K; m- x964068  ALLEGRO_EDITOR INTERACTIV       Allegro crash when using move alt sym mirror alt sym...
0 ^0 O/ N/ s7 h4 L$ X% i( w964267  CIS            PART_MANAGER     Capture become non-responsive, working on Part Manager and creating CIS BOM, for large designs
: @2 D0 a' f0 L964597  ADW            LRM              Issue of LRM license checkout after renewal license by 16.5 (ADW15.5_S23+SPB16.3)
1 X- N/ L5 e( `0 R1 w966148  APD            INTERFACES       Character Limit for DIE Files (*.die) Import. U1 j$ A$ U6 v7 @
966416  F2B            PACKAGERXL       Cannot package this design
) o& x- U! x/ T966421  CONCEPT_HDL    CORE             DEHDL Crash when applying property on components in duplicated blocks
5 r% r) C9 e% W# M966693  CONCEPT_HDL    CORE             DEHDL crashes when doing model assignment if CM is open2 j% h8 S( |9 H
966795  ADW            ROLLBACK         rollback utility does not honor -product option from command line8 |) j/ v+ ~$ O6 ?& R
967089  SIG_INTEGRITY  OTHER            Matchgroups created by ECSet not deleted when ECset is removed from object.
; k2 X% V: O0 C3 l7 Y4 }) {967222  ALLEGRO_EDITOR OTHER            PDF export is leaving data off the drawing- p$ Z8 s% H0 A: Q/ u1 S0 R; x) r
967240  SIP_LAYOUT     WIREBOND         Change default bond fingers selected on multi-site leads during "bond to leads" program
1 o, D, U% X/ M: x2 G967297  ALLEGRO_EDITOR OTHER            Dynamic Fillet&Eliminate unused stacked vias cannot be used as the Miniaturization option.
+ r5 H" \& X7 Q8 C967576  CONCEPT_HDL    CREFER           Occurrence location property values do not appear in flattened schematic generated by CreferHDL
3 C+ y! A7 m3 n1 Y968096  ALLEGRO_EDITOR DRC_CONSTR       Mechanical Pin to conductor spacing is not followed.1 E! U# l0 p6 x+ f( @
968222  SIP_LAYOUT     DIE_EDITOR       die pin loses IC net for a co-design die with multiple ports within IO-cell
% l% W( ^7 q. f3 M! N! r968358  CIS            PART_MANAGER     Capture crash on removing a part from subgroup in part manager/ e3 u1 u+ C, |
969594  CONCEPT_HDL    CORE             The dcf file is not updated with schematic changes  B$ ~6 V* A3 f) s( p7 {# H, R7 R+ O

* D3 z/ ~, |# N" QDATE: 12-16-2011   HOTFIX VERSION: 0135 X: D, C" W2 {9 Z2 E
===================================================================================================================================
. @0 W) n4 ~1 P% j2 E# a$ ]CCRID   PRODUCT        PRODUCTLEVEL2   TITLE8 I3 I7 M: E4 o5 ^. k# J( z
===================================================================================================================================0 a3 }! {( j/ K
875695  SIG_EXPLORER   INTERACTIV       Enforce Causality check box doesn't work.
0 Y! Z5 L* X' g( l: D4 w" [  c927148  CAPTURE        PROJECT_MANAGER  Capture crashes on creating scehmatic folder with name which already exists in design& y* q, U9 L2 O7 W3 F
938013  CAPTURE        NETLIST_OTHER    The netlist in RINF Format contained two identical lines for PCB FOOTPRINT$ ?" ]2 g( @6 y+ P6 B
941409  PSPICE         PROBE            BUG : Search accuracy wrong in new cursor window
# j, U. {, P+ z, w- j+ T! u; W945242  SIG_INTEGRITY  SIMULATION       Unable to select "shapes" in find filter for 'show parasitic ' command5 x4 S# K$ R# Z5 m& _3 e
946293  CONCEPT_HDL    ARCHIVER         Archiver hangs if there is a whitespace at the end of the path of cref.dat0 ]  A0 I" D0 o1 n9 j5 H6 x& b
946770  CONCEPT_HDL    CORE             揤iew Design� function is missing in Windows Mode after reseting the menus.
3 _2 y" v5 k, c2 M950994  CAPTURE        NETGROUPS        Problem in expanding the netgroup in Auto Connect to Bus function
8 ~0 E$ w; X8 T/ I0 R953530  SIG_INTEGRITY  GEOMETRY_EXTRACT Display Parasitics is displaying wrong results for EMS2D Field Solver compared to topology extraction using Probe.
. A- }4 B* t$ D953713  CONCEPT_HDL    PAGE_MGMT        Random page replacement/duplication in block
3 P3 ^- o; D8 H& i0 W6 K! y0 |953917  CONCEPT_HDL    ARCHIVER         archcore should handle errors correctly
3 i- {+ f$ Y5 N/ w953971  ALLEGRO_EDITOR MANUFACT         NC Drill files not generated correctly when using the option "搒eparate files for plated/nonplatedholes�* @& |  E4 \3 j* X  V
954400  CAPTURE        NETGROUPS        BUS members of NetGroup are getting converted to Scalars in Export-Import NetGroup.: _4 E* c1 s& Q2 M: `
954498  SCM            B2F              SCM crashes when importing physical1 E) a' \! c1 D* v
954623  ALLEGRO_EDITOR EDIT_ETCH        Unable to complete connection with Add Connect - related to soldermask to cline check?
. |: B" |4 }$ p+ [* I5 J# S* b954894  ALLEGRO_EDITOR MANUFACT         Dimensions disappear when opening database in v16.5 from v16.3
) I; u3 p! G1 J# P955029  CONCEPT_HDL    CORE             custom text font size not recognized in symbol view
6 n2 @% M# r- q955133  SIG_INTEGRITY  FIELD_SOLVERS    The Field solver creates the differential trace model which is reversed T(D1) and T(D2) of bottom side.
: \. t9 x$ l) X9 f. y/ {  w; I955290  CAPTURE        DRC              Description for UPD0014 missing in the Browse DRC markers window1 {: c* V9 S/ m8 }0 N
955299  ALLEGRO_EDITOR DRC_CONSTR       drc text to smd pin does not work any more on this database in 16.3 S039" J3 v3 F, l& w
955338  CONCEPT_HDL    CHECKPLUS        Need to change PART_NAME
) v+ U+ S  d  M0 m955447  SIG_EXPLORER   OTHER            Model path set in DE HDL Model Assignment not used by SigXP from CM in DE HDL8 x% x$ @- v7 A$ i3 }* \8 J7 P  C
955740  SIG_INTEGRITY  GEOMETRY_EXTRACT Crosstalk with Timing Windows does not work correctly( A& y& F0 Z. ^) v4 K  `$ _: D/ c
955749  ALLEGRO_EDITOR MANUFACT         show element Info shows symbol dimensions on incorrect subclass% Q1 Q. _. L/ G1 r) A
955912  ALLEGRO_EDITOR OTHER            Shapes with voids that are exported to PDF have gray filled area over the void- `# K: u  O% b8 A! R: K
956129  CONCEPT_HDL    INFRA            DEHDL uprev hierachical design from 16.2 to 16.5 packaging failure.8 D/ Y- e/ k. S' M3 l
956373  ALLEGRO_EDITOR NC               drawing name doesn't display in the log file- L$ f) y$ @0 a8 U9 f1 G
956393  CAPTURE        PROJECT_MANAGER  "GENERAL" and "TYPE" tabs are missing from "roperties" dialogue box.
6 C! s! O+ `6 j1 X6 ?  @956448  PSPICE         MODELEDITOR      Can not generate a DEHDL symbol from Model Editor, because no Capture license found0 t9 J3 O3 P: j( O- _  v
956456  CAPTURE        NETLIST_OTHER    OrTelesis netlist not transferring user properties defined under combined: _9 i$ F0 {# |* f0 @
956489  ALLEGRO_EDITOR MANUFACT         dimensions lost when symbol with diemnsions attached to symbol origin placed on board
5 l3 e- a3 v7 L& D/ z3 s956603  CONCEPT_HDL    OTHER            Part Manager "has stopped working" after changing a component  W7 Z+ `' H" Y; d/ |
956751  ALLEGRO_EDITOR ARTWORK          Import Gerber command does not work correctly
3 M% F9 P# ?) a956847  PCB_LIBRARIAN  METADATA         PDV - Partdeveloper symbol to function linkage broken/changed in 16.56 u* Y& A9 W1 {) ^4 ^  Y8 {. C
956987  CAPTURE        OTHER            Find from "Search toolbar" doesn't gives complete results
% _) [% F9 T5 L1 z) U% p956996  CONCEPT_HDL    INFRA            Correction to ERROR(SPCODD-7): Following Primitive instance causes CM to empty
" Y, q# P( p3 `# u% b957009  CAPTURE        NETLIST_OTHER    Problem getting database property in Mentor PADS PCB netlist! a& U# p2 [  B* f' x: H2 W5 D
957137  APD            DXF_IF           DXF out  command dose not work correctly., v' L) E9 Z( ~8 q
957167  APD            GRAPHICS         Highlighting for Static shape with display_nohilitefont environment variable.
# n. i. i$ {  u! L. f% y957232  SIG_INTEGRITY  OTHER            Allegro crash during Model Assignment.
6 k# S  u* k) k957267  CONCEPT_HDL    INFRA            Packager Error after Import Design
. l& [8 q) ]. J7 S7 Y957866  SIP_LAYOUT     DATABASE         Cavity outline is not getting deleted from symbol file
8 W8 d6 L: @2 v: w4 ]958010  ALLEGRO_EDITOR REPORTS          Wants the ability to extract "Batch"  reports from Partition ".dpf" files.9 P& `; S2 J1 u) w% @" l
958252  ALLEGRO_EDITOR TESTPREP         Resequence testprep with the option - Delete probes too close crashes the design; k$ @% W1 ~& z" G( \  a( E' B5 l0 q
958253  ALLEGRO_EDITOR REPORTS          Shape did not have thermal relief connected to pin but unrouted nets still shows zero.) m2 A) W/ A4 O( s9 N, J
958433  ALLEGRO_EDITOR DRC_CONSTR       False embedded component DRCs1 _7 ~( d4 w2 b8 w2 F; u$ ?
958753  ALLEGRO_EDITOR SHAPE            Dynamic shape is getting corrupted in 16.59 l+ k3 ]' a0 W9 S1 N) j
959011  ALLEGRO_EDITOR OTHER            copy problem of via and cline6 F# e, ~: I# c/ i: j
959101  ALLEGRO_EDITOR EXTRACT          Using extracta with excluding Thermal reliefs
8 \# ^% f4 j6 W6 B$ l. X/ d  h959253  CONCEPT_HDL    INFRA            Design will not open6 |( T9 C, M% T/ h5 v
959299  APD            MODULES          Getting ERROR(SPMHDB-279) when trying to update modules placed on the Top side! C# W( R' {0 ^$ D
959884  CONCEPT_HDL    INFRA            Design Uprev/concept2cm crashes with Application Error/Out of Memory Error.( q$ u- f  I4 G- z3 V  \/ G
959909  ALLEGRO_EDITOR SCHEM_FTB        Site level propflow.txt file is ignored property is transferred
0 O9 K3 `& I8 o4 |2 a, s& }: Z8 V960067  SIP_LAYOUT     PLATING_BAR      Creation of plating bar removes "NODRC_ETCH_OUTSIDE_KEEPIN" property from the clines.' i  |2 _7 W3 {; z
960126  SIG_EXPLORER   EXTRACTTOP       Allegro PCB SI license is used automatically at Topology Extraction of Allegro Physical Viewer.. X: X5 i$ C: a8 u
960143  SIG_INTEGRITY  GEOMETRY_EXTRACT Running simulation in Bus sim happened crash while enable Coulpled Via model to S parameter
) ~$ u9 V, h' Q1 i$ }1 B* P& _961349  CONCEPT_HDL    HDLDIRECT        Motorola designs have broken connectivity compared to 16.3% u1 ]8 q: ~: u
961816  ALLEGRO_EDITOR INTERFACES       Normal Export > DXF fails and offsets  the pins of the BGA symbol
9 v' Q! o! P  b- t: y( N962519  SIP_LAYOUT     WIREBOND         Align option doesn't work for wb_tackpoint fingers
9 u8 v% a3 L- Q5 N
! j4 d+ N" p1 |/ [( b. VDATE: 11-30-2011   HOTFIX VERSION: 012
2 F6 x) j7 M* d: V4 R" k===================================================================================================================================9 y4 Q- c+ s! W: V  h# f) g6 g
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
3 s1 t, v) q2 W$ |===================================================================================================================================  |& T% B( z6 h3 j0 u% F$ C+ b1 O: i# w! f
959581  CAPTURE        NETLIST_OTHER    PCB Footprint is getting replaced by VALUE in OTHER netlist formats1 ?) X& S# W1 O# f

9 ]3 g2 S' v) ~6 g& ^- Q4 N9 tDATE: 11-18-2011   HOTFIX VERSION: 011
: D9 Z, r5 d+ O# Z, p===================================================================================================================================/ k* j9 M" ?/ t, A
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
1 \) y3 O% D7 m1 j===================================================================================================================================
* M1 A1 D8 i7 ?, I735439  PCB_LIBRARIAN  CORE             PDV Moving line-dot pinshapes by arrow keys breaks the pinshape7 h, y- s1 ^% s. T8 Z* D" p$ r$ H
894815  CONCEPT_HDL    COMP_BROWSER     Why does genlibmetadata command give 'Aborted $PROG' Message?% z2 I) E5 k3 F7 Z/ j* a0 y
903073  ADW            COMPONENT_BROWSE datasheetl_url directive should support a display string for URL% u4 y1 y  X* Y8 U, a5 F& q
909919  CONCEPT_HDL    OTHER            Why is the PublishPDF UNIX command line looking for "true" script?
# S4 b# o4 ~) j2 w6 B911561  CAPTURE        CORRUPT_DESIGN   Capture crashes on trying to save the design.3 E. K! b4 P5 d
919579  CAPTURE        PRINT/PLOT/OUTPU Print mode be selected based on schematic mode4 |0 y5 f4 x* M: a( u. c2 u2 k: T
921247  CONCEPT_HDL    COMP_BROWSER     genlibmetadata.bat file does not have err defined
: I0 q/ f% r. Z+ p6 i925182  CAPTURE        PROJECT_MANAGER  ENH: Feature to run update cache on all the parts in design cache at once.
  x( Z, c" O2 x926858  CONCEPT_HDL    CORE             Usability- Modify Component dialog forces user to do 'Reset Filters' to see other ppt rows- h' k9 e) S9 c/ T; P+ k6 @" n
927657  CAPTURE        NETGROUPS        Enhancement: Placement of netgroup definitions under design cache list/ z/ p1 g9 a3 i. H3 z. Q5 z; P
934684  ALLEGRO_EDITOR MANUFACT         The relation between the linear dimension and the symbol breaks.
: G6 t0 G4 G! {4 h0 J935836  SCM            SCHGEN           ASA crashes when generating Flat Document Schematic$ ^& D, [- k) ]+ w# V( j- ]
937165  SCM            SCHGEN           Can't generate Schematic
5 t7 `, Y( C- i8 Y937292  CAPTURE        GENERAL          Memory usage keeps on growing and finally gets exhausted while search; `2 ]; @7 p6 j
937322  CONCEPT_HDL    CORE             Master.tag file alters the sequence of the files and Genview fails
$ i7 V% ], c' I. K! ?1 w939135  CONCEPT_HDL    CORE             Unable to uprev a 16.3 Design to 16.5 with DEHDL-L License  P9 |0 @, G: X! c1 f$ t
940373  CAPTURE        TCL_INTERFACE    Enhancement: TCL command to add nets to Netgroup
# [) Z; R5 r. M5 p6 _940547  TDA            CORE             ERROR(SPDWSD-69): highspeed cannot be checked in
9 A- j% T) k7 y6 V! L1 \940607  SIG_EXPLORER   OTHER            Inconsistancy in License usage for opening sigxp -orcad
: h8 t3 s$ r$ {3 k940790  F2B            PACKAGERXL       User doesn't want to display pin numbers after Export Physical 16.5.
8 S9 ?: b) r3 ]  J+ G. Z" u940944  SIG_EXPLORER   OTHER            Inconsistant license usage while opening Orcad PCB SI using allegro -sq -orcad and allegro -sq
0 E9 D. o/ s' m9 W5 x0 p+ C* r+ Z941354  CAPTURE        NETGROUPS        Enhancement: Option to rename the unnamed NetGroups
# \/ v9 T1 ~0 F/ b941455  ALLEGRO_EDITOR MANUFACT         The Dimensioned mechanical symbol when placed in the board does not show all the dimensions.7 y7 z/ s5 H+ J4 F* b0 ]
941863  ALLEGRO_EDITOR EDIT_ETCH        Different behavior of design in v16_3 & v16_5 when add connect is executed on a segment thru script$ w, \' Q% L: j% B
941881  CONCEPT_HDL    COMP_BROWSER     How can I suppress the dialog from universalbrowser -genlibindex?
) L& ?- j/ D( a4 K1 h3 u942474  CAPTURE        NETGROUPS        NetGroup member type of last added member must be remembered by Capture
- P- f0 o, N) n/ C942522  CAPTURE        GEN_BOM          Export in excel check mark doesn't invoked BOM in Excel
  a8 C1 b. T' u4 R) J942557  PCB_LIBRARIAN  EXPORT_OTHER     PDV Export to Capture crash
6 h: k4 F7 Z3 X5 f942569  ALLEGRO_EDITOR MANUFACT         Dimension  move and change  text deletes leaderless balloon7 n7 ~1 o) c" V3 `! o$ u
942573  ALLEGRO_EDITOR MANUFACT         Balloon type parameter  has no effect on leaderless balloon.
& P# D, f" O8 n5 ^* T$ @942613  CONCEPT_HDL    CORE             Genview supports only SCHEMATIC/SYMBOL/VERILOG/VHDL views as input type.  .xcon not recongnised
- M# n  K9 P: H+ M7 g& E1 k943032  SCM            OTHER            ASA is not passing the correct reuse_module name to Allegro PCB layout.
/ o' \! r3 A7 a  l) h  d) n$ [943401  CAPTURE        NETGROUPS        Alphabetical ordering of NetGroups in Place NetGroup5 O' A$ }. u% v% b
944006  ALLEGRO_EDITOR EDIT_ETCH        Vias added to shapes behave differently8 {" y4 h9 D  e! }' U" E/ }
944367  CONCEPT_HDL    OTHER            Too late to do Model Assingment in conceptHDL 16.59 }. G8 w8 k. n' g3 K7 E6 y
944788  ALLEGRO_EDITOR GRAPHICS         Oblong Pad shows unexpected lines
' Y  q0 ?6 t2 l6 N+ K; w- H945221  CONSTRAINT_MGR RETAIN_CNS       CM Conflict Resolution fails on more complex designs using ECSets and constraints
6 Y* B( D: c+ H- {  A& D946270  ALLEGRO_EDITOR PLACEMENT        The Rotation Type was changed to "Absoute" if the "iangle 90" use at placementedit mode of spb16.50 X7 S$ \8 q* W7 F
946350  F2B            DESIGNVARI       Variant Editor rename function removes all components
1 @! A4 @3 B3 g: m& c946380  F2B            DESIGNVARI       Some VARIANTX properties are hard some soft - why?; y. @, x" z5 s& U- M% y
946419  SIG_INTEGRITY  SIMULATION       Cannot select component on BoardModel for controller in bus setup form
- g6 l8 w, `  j! {. p; O4 z946458  SCM            SCHGEN           Schematic generator adding an unnecessary page
% W# s; r# p3 i! c8 |4 [4 |6 C947667  ALLEGRO_EDITOR PADS_IN          Need support for PADS-POWERPCB-V9.3-BASIC. A, n& D1 B6 ?- _
947789  ALLEGRO_EDITOR MENTOR           mbs2brd crashes during translation on the attached design.
3 M" m" h- q9 L7 f. {948110  CONCEPT_HDL    CONSTRAINT_MGR   Concept HDL craches when opening SigXP from CM
% W  H. Y) }* V; g7 d7 s& Q8 f; n2 O950970  ALLEGRO_EDITOR MANUFACT         Unable to generate artwork, dbdoctor fails to fix errors.0 t/ U7 @# Y" d+ u
951901  ALLEGRO_EDITOR EDIT_ETCH        In 16.5 add connect to same net is shoved' p" S& X0 I/ B) m1 C6 i
951919  ALLEGRO_EDITOR OTHER            Exported package symbol soldermask and pastemask padstack locations not the same as original' T' v: U# T  j3 C
951926  CONSTRAINT_MGR OTHER            What is MaestroNotifyNotSetReport.txt file?& X9 D) b+ e4 [: H7 g
951939  F2B            PACKAGERXL       Uprev to 16.5 is changing refdes for some pages5 a$ w+ l+ ?( @) B# t2 r. i
951983  CONCEPT_HDL    INFRA            Problems converting an Allegro design from 16.3 to 16.5
: L* u6 v$ N) {952057  SCM            PACKAGER         Export Physical does not works correctly from SCM
4 [& c4 L2 b( h% q952217  ALLEGRO_EDITOR GRAPHICS         crash when opening 3d viewer in PCB Editor
) C2 W- G! f, u- y) O+ h, |952634  CONCEPT_HDL    CHECKPLUS        Checkplus logical rule fails on a design which packages fine in 16.5
4 i% p5 I9 G5 r" u2 E! ~( s  ]$ ~953018  APD            REPORTS          Shape affects Package Report result.
" D) R9 ~" k5 b* y5 }6 a2 J3 l953337  ALLEGRO_EDITOR OTHER            Allow netname and padstack names to be visible for testpoint vias when viewed in Allegro PDF Publisher.$ s8 ^- I; W2 k% Y/ S8 u' }
953827  ALLEGRO_EDITOR EDIT_ETCH        Snake Breakout function crashed Allegro! ]$ o2 F6 s5 n. u  G
953918  GRE            CORE             GRE cannot route second and third row of pad in die symbol.0 [; |, `) A+ o4 [1 y
954055  CONCEPT_HDL    CREFER           Crefer fails with UNC install path9 I$ [) u: q  n
954920  SIG_INTEGRITY  CIRCUIT_BUILDER  Each neighbor crosstalk simulation crashes or returns blank report
5 G2 U3 x+ N9 t2 E. q& j! P
( n& W! E: s; X" W8 L: bDATE: 11-7-2011    HOTFIX VERSION: 010
; u" U3 I. r9 p3 g" h* Q===================================================================================================================================0 X/ Y! v0 ~6 Q7 ^9 {: v* _; u
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE) y4 |5 D6 R) a9 {1 f9 f
===================================================================================================================================
2 K# d2 ~1 U  q- s( \* R6 e  }658866  ALLEGRO_EDITOR EDIT_ETCH        enhancement option - so that Sliding a via inside a pad does not create a cline  q( E. u$ |4 B& d; c
928624  ALLEGRO_EDITOR GRAPHICS         Layer visibility control for 3D Viewer2 G) L' X0 C0 b& B
934991  SPECCTRA       LICENSING        Specctra_adv option is not working correctly for PA3100 plus PS3500 license in v16.5 tiering profile2 I* e' Y1 o6 @! O" s0 e* w
938073  ALLEGRO_EDITOR PLOTTING         Plot Page size A0 and A1 with problem- }$ O4 u# I3 _9 M* j9 z2 ~7 Y
938128  ALLEGRO_EDITOR DRC_CONSTR       DRC changes when do update DRC.! z: T9 @" ^1 J; S$ ~8 H
938648  ALLEGRO_EDITOR GRAPHICS         Enh - Requesting a way such that Package keepout appears transparent in 3D Viewer
5 i6 }" {. Y+ K8 o- l* o. ?940518  SIP_LAYOUT     SYMB_EDIT_APPMOD Swap pins command doesn't complete
" Q; V) p' d8 f) K0 |941426  CONCEPT_HDL    COPY_PROJECT     Copy Project fails - Updating opf view This can't happen!
& j0 o; n/ ]8 j0 C- V4 i; `! C941499  ALLEGRO_EDITOR DRAFTING         BUGimit Tolerance isnot working for Dimensioning
4 o/ ^: a" i" q$ q/ _) k/ M941814  CONCEPT_HDL    CREFER           CreferHDL crashes during ScheGen" r. N8 @9 q) @5 w* F7 ?# z) w
942914  SIG_INTEGRITY  OTHER            ZAxis delay calculation
+ l5 s4 d5 t- K- V* V9 t943053  ALLEGRO_EDITOR SHAPE            Modifying the Board Outline shape will cause the tool to crash1 {- X# b3 t' P
945321  SIP_LAYOUT     EXPORT_DATA      generation of a xml file from cdnsip for shrunken die) f: ~1 m8 p1 Q$ a% `  j
945350  ALLEGRO_EDITOR SHAPE            iPick does not work on shape boundary edit.
3 o  U! T& Y8 w5 N% J2 c% g945449  APD            SKILL            When they create a new menu entry with skill APD crashes with next menu selection.1 F  F; J3 m7 ^
946390  ALLEGRO_EDITOR DRAFTING         refresh_symbol crash when trying to refresh mech sym that has dimensions
9 X0 y$ Q! p  H946401  APD            EXPORT_DATA      stream out gdsII results in shorting of PWR/GND nets due to elongated etch. V' R' P0 J) |! _% {1 Z/ f
946819  SIP_LAYOUT     DEGASSING        Shape degass command2 p& D* G9 Z* v: [. J" I+ ?+ L
946869  ALLEGRO_EDITOR OTHER            Allegro PDF arc representation needs cleaned up
! l/ A8 W0 N" z/ R; Q* i947230  ALLEGRO_EDITOR SKILL            Skill execution crash Allegro 16.5 but work correctly with Allegro 16.3
4 N( n& n. j4 G1 p  x% I947603  ALLEGRO_EDITOR OTHER            Component Properties (Default or User Defined) not transferred to PDF file
% t, j- f0 x$ D* O$ ~950995  SIG_INTEGRITY  OTHER            Netrev fatal error when importing logic
  T% y4 q8 g$ |( Z9 L951123  ALLEGRO_EDITOR INTERFACES       IPC fails to output drill hole info in columns 33-376 w' o  O, ^: K0 K+ I
951557  CONCEPT_HDL    CORE             Cannot create the entity folder for old plumbing symbol
* Y) A9 B& g4 k: R" ]) \, B' O- p  g! P! p" I
DATE: 10-26-2011   HOTFIX VERSION: 009
4 q1 A0 C" q" C. _1 f& c6 g===================================================================================================================================
2 d* v6 d: A- Q; V) VCCRID   PRODUCT        PRODUCTLEVEL2   TITLE0 |) v1 j4 c& a9 A  p* `0 O
===================================================================================================================================
1 U$ X' k( a0 d$ p7 P( R# P3 h945788  CONCEPT_HDL    CORE             Some component properties on the parts are incorrectly changed after Import Sheet
7 ~' U% x- z3 L  ^' v( Q% a945789  ADW            LRM              Some component instances are not updated by LRM even though cache ptf is updated from reference
: M- b) {6 W- t7 Q9 E% x% r/ `% c
DATE: 10-21-2011   HOTFIX VERSION: 008
# @& Z" a$ u- a===================================================================================================================================
2 F6 P" e! Q- S* tCCRID   PRODUCT        PRODUCTLEVEL2   TITLE0 w! _9 W9 O. V9 ~4 j5 `  B
===================================================================================================================================
7 O4 F8 o5 {8 [& ~2 T- ]+ z: @906827  ALLEGRO_EDITOR DATABASE         Logic > Parts logic does not work correctly.& B) ?' k4 P9 H
923346  CONCEPT_HDL    CORE             Not able to move the reference designators inside hierarchal blocks after uprev to 16.5
- n/ b; i  f  B926347  ADW            COMPONENT_BROWSE Usability- Libflow Part check in comment should end up in Comments attribute for UCB/Designer to see it+ t5 ^# D& l( \* D% S1 d0 x6 I
929348  F2B            BOM              Warning 007: Invalid output file path name
. |# A# E/ Z. J# }4 _% H929777  CONCEPT_HDL    OTHER            Component Revision Manager gives internal error$ Y) _/ g& Q3 e# P7 K
930783  CONCEPT_HDL    CORE             Painting with groups with default colors
* a# U- S* ^7 V, h" n# `936748  ALLEGRO_EDITOR INTERACTIV       "Unplace Component" menu inconsistent between General Edit and Placement Edit Mode.
6 m( i& e+ G0 Q: O% b; X4 {2 U938143  ALLEGRO_EDITOR CREATE_SYM       Why is this Extra Property 'ECSET_MAPPING_ERROR
/ w' @9 L( J3 N' t$ A/ e& X938281  SIP_RF         OTHER            export_chips creating bad data when symbol is split and contains V- V+ pins
* ^# n! j& t0 ?. B1 L4 u: v0 X4 ?4 k938812  ALLEGRO_EDITOR SYMBOL           Cannot create a BSM with this DRA, errors out but does not state a reason.# E; W) G( y+ _0 W& [* y
939075  CAPTURE        TCL_INTERFACE    Texts are getting garbled in command window
) v: m" b& s6 V: d939193  F2B            PACKAGERXL       ERROR(SPCODD-439): Connectivity server is unable to load the design.4 }% K7 x) `# [% K
939199  CONCEPT_HDL    DOC              "Retain electrical constraint on net" mismatch between schematic (YES) and design (NO)
0 l& F2 G5 E! p0 c939346  ALLEGRO_EDITOR SHAPE            Shape disappears when updating with variable shape_rki_autoclip set.
0 [2 a- v- V+ O939901  CONCEPT_HDL    INFRA            NET_SPACING_TYPE shows �?� on lower hierarchy level nets after Upreving to 16.5 version.
8 n! I+ f$ x9 T6 \939918  PSPICE         PROBE            Print > Preview for output file causes Pspice crash.: N' R" s/ k, k. G" u: _' P& S: W
940217  CONCEPT_HDL    COMP_BROWSER     UCB reports 'No Symbol found for the part'! I, H1 X2 x  c0 v* A
940835  CONCEPT_HDL    INFRA            Desing package different after uprev to 16.5 where comp instance  propeties are lost  lost
0 O# t+ M- T' m. v941125  ALLEGRO_EDITOR DATABASE         Performance advisor doesn't skip non plated slot padstacks
9 ^! @. K* ]: @+ W7 c941876  SIG_INTEGRITY  OTHER            Illegal model name cause pxl fail in 16.3! q0 W0 s# I8 U& J7 {
942210  SCM            OTHER            Is the Project File argument is being correctly passed?, _$ o! U3 k0 Y& s
942274  CAPTURE        PROJECT_MANAGER  Crash on renaming a Design Cache part in Project Manage after doing replace cache( a3 g( T, ~: A" p9 H& d# E6 K( K
942839  ALLEGRO_EDITOR GRAPHICS         Graphics Issue- Pads are not visible
: p$ l. U" H- P; k. a943055  ALLEGRO_EDITOR SKILL            axlDBCreatePropDictEntry causes application to crash
# z: F" h% x0 ~2 w1 [9 d9 D" ^
( @# f  o/ V6 T3 _* ZDATE: 10-21-2011   HOTFIX VERSION: 007( e* Y2 W# ^$ k+ U" N! R
===================================================================================================================================
' z( C0 C; b# p. |9 D1 _# bCCRID   PRODUCT        PRODUCTLEVEL2   TITLE
! u2 c/ `9 ~; t4 C2 I9 C===================================================================================================================================- Y2 e5 F9 \# i' R& S$ {  G
841096  APD            WIREBOND         Function required which to check wire not in die pad center.' |# A4 N! r0 ^, v: h
903263  CAPTURE        SCHEMATIC_EDITOR ENH: Selecting parent netgroup must select the underlying netgroup bits.
" D) A& |: v$ K. o+ }* T0 E( f' ?906692  ADW            LRM              LRM window is always in front when opening a project
3 V% i4 C" s" L* }912942  APD            WIREBOND         constraint driven wire bonding: M" l- s' R( Y. y8 w9 M
912951  CONCEPT_HDL    CONSTRAINT_MGR   Need to manage temporary files on Linux systems- k$ ]& W/ a( g  s+ h/ G
915178  SIP_LAYOUT     DIE_STACK_EDITOR Die Pad names changing when updating Die in a design
1 [& W& \/ _; i; g917887  PCB_LIBRARIAN  VERIFICATION     Part should not be released if the alt_symbols has errors2 g) K  Z: W& y' ~$ e* f
923315  SIG_INTEGRITY  GEOMETRY_EXTRACT crosstalk simulation fails with TMP popup failure: p+ E1 R7 H' u
927382  CONCEPT_HDL    CHECKPLUS        'Verify Symbol' forces the use of 'Concept_HDL_Studio' license; ~$ k3 o( X; v6 a
927664  CONCEPT_HDL    CONSTRAINT_MGR   Internal Error disposeipsp
8 F9 F+ Q" p' `& ~& X3 H$ E930152  CAPTURE        NETGROUPS        Scalar net names when being connected to net group overlap when connections are made one by one
/ I0 |8 w) d- w" G; Q, B930180  CIS            LINK_DATABASE_PA Visible property position on schematic get reset on "link database part" operation# f- d0 e# g2 k. S/ x- b
930188  CAPTURE        DATABASE         Capture 16.5 crashes in being re-invoked.
( V5 H9 o2 x5 e) _; s/ m6 ~/ k930541  CAPTURE        NETGROUPS        NETGROUP element renaming doesn' renames the associated net ?
. V' Y% I9 m# v' v! Q930866  PDN_ANALYSIS   SETUP            OrCAD PCB SI Session crashes when we open PDN Analysis with "OrCAD PCB SI" license.) Q; ]% c0 y5 ^! m% s+ M7 ]
930926  ALLEGRO_EDITOR GRAPHICS         Via and Holes not visible eventhough set to Visible in Color form
/ Z+ j- ^) o& K* N6 B931274  ALLEGRO_EDITOR DRC_CONSTR       Negative Plane Islands waived DRCs reappear after performing update DRC." F" T  e  P+ \* J# x; ]- T
932091  CONCEPT_HDL    CORE             Prop attached to SIG_NAME property
$ H3 B; v9 `* E2 k) V" J  \8 C932255  ALLEGRO_EDITOR GRAPHICS         Change in Zoom level makes arc segment to disappear
3 \5 K% S; v4 n+ Q932292  ADW            LRM              LRM crashes during Update operation on a customer design
; t! f: r) B5 z% u- w3 M, R932639  SIG_INTEGRITY  OTHER            Add Connect command hangs for about 14 seconds and then returns.2 o1 T- C$ V  v) ?# ?: m
932704  APD            DEGASSING        Shape > Degass never finishes on large GND plane) g+ ~( k! v8 G- G
932871  APD            GRAPHICS         could not see cursor as infinite. I' p/ }7 y8 S# Y: K$ f7 Z" ^. P
932882  CAPTURE        SCHEMATIC_EDITOR Capture crash with FIND command - ISR05
7 h" \' ?: f5 E4 K/ K: w# `932969  CONCEPT_HDL    CORE             ConceptHDL crashes when you save the design in 165 > hotfix #059 S% H4 ?" ~  ]% |
933024  CAPTURE        NETGROUPS        Naming restrictions for NetGroup members/ P% T6 a6 p* L5 Q) F' [4 ?3 X4 ]
933145  F2B            PACKAGERXL       Add Subdesign list is truncated in Force SubDesign Design Name pulldown
: ]5 u8 c8 i( T. ]933214  APD            ARTWORK          Film area report is larger when fillets are removed6 Y& \: [2 Z' V0 W, z5 D, J
933356  CONCEPT_HDL    CORE             Net prop display size become 0 if it was attached to SIG_NAME prop.
5 W- N/ `5 E& O" S8 i$ u7 D' Z933532  ALLEGRO_EDITOR COLOR            Bad color assign and initialisation during creation of new subclass/ n( _: [: b  ~$ |
933549  ALLEGRO_EDITOR OTHER            Chart text missing in export PDF file./ {* c$ O8 K3 Y' ]. ]- C# e
934008  ALLEGRO_EDITOR REFRESH          refresh symbol updates symbol text to some unexpected values
: k, `1 c# I7 p934031  ALLEGRO_EDITOR DRC_CONSTR       Bug : Update DRC removes Waived status for some DRCs
& Z% L; y0 p1 I- r934087  CONCEPT_HDL    CORE             Opening DEHDL and Model Assignment before design loads causes crash
* S' ]  w# U( |4 ~934396  CAPTURE        SCHEMATIC_EDITOR Find operation is not searching power symbols with + or - signs./ S$ d) N/ L/ T% _/ ]! g
934533  F2B            DESIGNVARI       The Variant Editor errors are not written to the variants.lst file
/ {9 s9 \8 k  h2 }7 b, o& M934811  SIP_LAYOUT     UI_FORMS         CDNSIP should not hang if contraction value in z-copy command is out-of-bound
: T1 P# k& t/ M8 _934909  SCM            UI               Require support for running script on loading a design in SCM* s; V( j0 k& Z- _$ S
935632  CAPTURE        SCHEMATIC_EDITOR SHIFT+Mouse wheel scroll(horizontal) of page is not working in Auto Wire Mode.+ J. e2 Z. j* J- o9 U+ ?- Q
935794  ALLEGRO_EDITOR SHAPE            BUG:Shape not filled in 16.5 but it does in 16.3
% p# N2 F% Q! i935988  ALLEGRO_EDITOR INTERFACES       When attempting to downrev this 16.5 design to 16.3 the tool will crash
$ a$ C, W. c# ?936056  ALLEGRO_EDITOR DRC_CONSTR       place_manual crash while moving mirrrored symbol) \$ M; J: T. W0 [5 W
936098  ALLEGRO_EDITOR SKILL            axlDBCreateCloseShape does not work correctly." E! d2 Y6 t8 s/ m
936212  ALLEGRO_EDITOR INTERFACES       DXF not created if Blocks created for Symbol and padstack
/ u0 Y& E, B' U) N) j936797  CONCEPT_HDL    COPY_PROJECT     Copy Project crash: |( K& D! k" {
936808  ALLEGRO_EDITOR DATABASE         Allegro crash replace mechanical symbol
% ^8 m. l0 Z+ Z. i) ]$ ?8 o936853  CONCEPT_HDL    CONSTRAINT_MGR   DEHDL crashes when trying to extract net from CM3 b! o% I" G3 t6 Z0 y8 n
937087  CIS            DESIGN_VARIANT   Upreved design becomes very slow in Variant view mode. DELEET THE DESIGN AFTER RESOLVING THE ISSUE3 a2 F9 c. S" R; {
937173  CAPTURE        OTHER            Wrong license information "UNLICENSED" in Capture >> Help >> About
7 Z! E( i' O% i1 P$ @; Y937290  APD            PLATING_BAR      Plating Bar checks does not recognize connection made through etchback through shape.
0 l( [" V+ [8 c: x: }- y937411  ALLEGRO_EDITOR DATABASE         downrev_library  reading from one directory and writing to another hangs the command.( W$ ?8 w( B% \* q
938235  SIP_LAYOUT     STREAM_IF        Die Orientation is not correct after importing a stream file.
0 Q7 N* B& y4 F9 W" E' S* ~938273  ALLEGRO_EDITOR OTHER            PDF export is is not opening viewer with ads_sdlog variable set  T" k9 d* D3 t; J& A/ Z! f  _
3 ?( j8 X0 i7 J( f3 N
DATE: 09-16-2011   HOTFIX VERSION: 006
# ~4 e; D' h9 m  t6 b  q===================================================================================================================================( P. a# v9 ^9 ^7 F- o
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
+ j% p6 B" D- u4 X" S===================================================================================================================================
% g3 |  R0 S$ C, [: H820131  CONCEPT_HDL    OTHER            Moving symbols to other page will make Allegro components unplaced because logical_path changed.
4 q4 E' _2 p6 A2 J3 D! }863860  CONSTRAINT_MGR SCHEM_FTB        CM should display or Local Interface and Global nets to help defining low level constraints
6 S* A- F/ J7 ~; k# U919822  TDA            CORE             Cannot configure LDAP to only list the login name# B* A) r% V- ]* M9 N6 A
922907  ADW            TDA              搇ast_callout_file� directive in the BOM section is empty causes tda for show Access Denied error) K" B' \6 q! ]' }& N
924322  ADW            COMPONENT_BROWSE Random - No instance properties are added on Add To Design (RMB or double click) from Search Results
8 h4 a# i8 n! x$ C5 p% C, D924448  F2B            DESIGNVARI       Design does not complete variant annotation) e% Y3 C( l2 N5 ]5 j( u& h  i
925584  CONSTRAINT_MGR SCHEM_FTB        16.3 upreved Design passes the SLOT/Function Properties to PCB
- A/ f# m, u+ `% V2 n927102  ALLEGRO_EDITOR OTHER            Question of Conductor Detailed Length Report/ b$ Q. }/ y! M9 Z" g! E$ x8 J8 @
927104  F2B            DESIGNVARI       Tools > Annotate variants crashes when there are ASCII characters in the property values; V' w% j4 B8 ^/ i( Q& A( j
927142  F2B            DESIGNVARI       Incorrect pop up asking while executing variant editor from the command line
% ]- O' A; I4 F# A$ \! t, p% h927166  CAPTURE        NETLIST_ALLEGRO  ENH: Feature like NET_SHORT in Capture Allegro flow which allows user to short 2 or more power nets
: o0 l- Z5 n' B' w; n: j927410  ALLEGRO_EDITOR DATABASE         ERROR(SPMHUT-144): Illegal arc specification error when Run DBDoctor
7 s' z' o6 l6 g2 o3 z2 K& J' z927475  CONCEPT_HDL    CORE             About forcereset command of nconcepthdl  ]( X; O9 b0 J' I
927498  CONCEPT_HDL    CORE             Pin_Name starting with minus causes incorrect behavior for $PN display
4 J0 j. J" A; A1 l, b927608  ALLEGRO_EDITOR PADS_IN          Import PADs fails with error message: Failed to close the Allegro database
8 F- h% {. b5 o5 j- X) |: b' c927637  SCM            CONSTRAINT_MGR   ASA crashes on change root and also performance is too slow.! a+ X4 G7 t! p6 a) @) B
928429  SIG_INTEGRITY  OTHER            Request - Package Wizard to work in PCB SI.8 S3 W7 |8 ~0 q2 c9 G0 d5 p8 x
928483  ALLEGRO_EDITOR DRC_CONSTR       Running Update DRC removes Via List DRC Error when via is actually not in the list
6 `( D2 O6 H  I% t0 K. c0 q; y# l928738  PSPICE         PROBE            Y-axis grid settings for multiple plots. o1 }4 k6 W- S  \+ r# a4 a
928748  PSPICE         PROBE            Cursor width settings not saved' C+ _! G2 D/ ~! L7 q- |
928779  CONCEPT_HDL    CORE             Error (1053) occurs on a copied part in SPB165 release
) s. I* ?) d3 O+ R5 W928838  CONCEPT_HDL    CONSTRAINT_MGR   ECSets not migrated in 16.5
. u* }" [* E2 D928885  SIG_EXPLORER   EXTRACTTOP       PCB SI crashes when extracting a net from Probe
2 X1 P1 G  r9 _929284  CONCEPT_HDL    ARCHIVER         archive does not create a zip file
& P) l; ^( t+ d' V929542  SIP_LAYOUT     DIE_ABSTRACT_IF  net issue of multiple ports of co-design die in SiP
- _! O$ h! b. b929656  ALLEGRO_EDITOR PADS_IN          PADS translation fails with Microsoft Visual C++ Runtime Library error
& ^; r5 f& e( k  ~930063  ALLEGRO_EDITOR TESTPREP         Test prep crash Allego when it can not create pin escape
, R# u4 z( N$ j& X& D/ x' F) S930217  CAPTURE        NETGROUPS        Net aliases doen't gets assigend to bus bits if bus name is checked in NETGROUP.
5 Z( q# J' I7 C2 x) N930355  SIP_LAYOUT     WIREBOND         about "wirebond add nonstandard" command/ l6 u- p2 W4 {
930607  APD            OTHER            Layer mapping information is reomved from Layer conversion file upon exporting DXF from board file.
+ {/ L( ]. B' W6 y7 I4 J9 O930646  ALLEGRO_EDITOR DRAFTING         Bug - Adding Linear Dimenstion for ISO standard add the Angle information as well$ h; O7 U! `5 r2 m
930894  CAPTURE        TCL_INTERFACE    PDF export doesn't  creates property file if some symbols are used in page name/folder name9 S) x. G8 s2 x0 P
930944  ALLEGRO_EDITOR OTHER            Setting variable 'appmode' equal to 'none' is not changing the Application Mode when reinvoked) [; T, r. q+ z! ^( ?" P
930978  ALLEGRO_EDITOR SCHEM_FTB        3rd party netin error - Pin is connected to net <netname> not reconnected no longer happens+ {% P6 u* O, W8 b3 U. g
931248  ALLEGRO_EDITOR DRC_CONSTR       Match Group was removed if member nets became xnets.
2 h3 l! u# o% i2 Z  e! n931278  CONCEPT_HDL    INFRA            $PN gets copied when upreving design from 16.2 to 16.5 version5 v* M- O# ?2 a) I1 d
931349  CONCEPT_HDL    COMP_BROWSER     DEHDL craches and corrupts connectivity file when using Modify command extensivly.: f4 V9 f% }0 t! f5 b

4 X, v2 \5 r! c4 u3 \/ YDATE: 08-31-2011   HOTFIX VERSION: 005
1 W* X! E) z6 p& W" |( J& g; E===================================================================================================================================- N# p  \, U  F' U
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
6 X9 _/ [, |" T8 ~' I/ \===================================================================================================================================
/ N/ d, p& u1 }' m$ B8 Q5 {825848  ALLEGRO_EDITOR SHAPE            Shape not filled when edges from 2 RKO shapes touch around mouting hole
- R( ^9 `+ P0 W, J837723  CAPTURE        PROPERTY_EDITOR  Occurrences of external design not related to current root should not show
8 ]! @0 G5 h9 u) x891079  CONCEPT_HDL    CORE             DEHDL crashes with large number of commands in Winodws mode% R( T- R3 n$ P8 F1 e& i8 \
910908  SIG_EXPLORER   OTHER            Cannot open top if Tx AMI dll name contain more than 2 dot.
" ?+ t, i- x  Y. n914036  CAPTURE        LIBRARY          ENH: Option to delete a corrupted part from a library and leaving other parts intact in the library.
  J7 P; E1 [9 E0 Y/ [914679  ALLEGRO_EDITOR INTERACTIV       Custom toolbars are not retained when switching between brd to dra and back to brd file using the File > Recent Designs4 [' Z$ u1 l  w) J/ Q
914870  MODEL_INTEGRIT OTHER            mergedml fails to merger 2 DML files from the model integrity
- m* b. a  T; N0 |' }  i8 _# \915645  ALLEGRO_EDITOR MANUFACT         Allow the user to place the cross-section chart at a desired location% X. M1 ]" E4 R+ k! A* e
915653  ALLEGRO_EDITOR INTERACTIV       unable to delete non-etch shape
* D; }+ \3 Q& W, t" k915711  ALLEGRO_EDITOR MANUFACT         dimensioning tolerancing by limit not working0 Q0 H9 B$ A  o% o& O0 x! [
916321  CAPTURE        GEN_BOM          letter limitation in include file
9 h1 s# o) w1 S- Q916907  CAPTURE        SCHEMATICS       揂uto Connect to Bus� should place the wire through non-connectivity objects
1 N- S# M9 Y& g7 G+ G. F5 X920327  CONSTRAINT_MGR ANALYSIS         The TotalEtchLength predicate in Constraint Manager does not work for a netclass with a bus.1 j: I6 w, D; I' \% l+ q
920753  ALLEGRO_EDITOR GRAPHICS         If I confirm to padshape with zoom-in after install the s002 It was changed to wrong shape.
9 f' X; v/ `. p+ ]# c8 I921097  ALLEGRO_EDITOR GRAPHICS         Padstack seen partail filled when Zoomed in even "static_shapes_fill_solid" is set
% c1 Z* p- e: d921226  ALLEGRO_EDITOR DRAFTING         Unable to select Package Geometry class when dimensioning in the symbol editor.
5 x2 S0 c$ f" b. f, J# A/ k0 J2 Z921623  ALLEGRO_EDITOR GRAPHICS         Bug : Symbol not visible when zoomed in 16.5 S0026 t0 m- A# g* S- d& F4 t
921891  ALLEGRO_EDITOR DRAFTING         dimensions are lost after downrev(ing) a SPB 16.5 design with associative dimensions6 U- \7 I( E% y$ M* u/ I
921937  ALLEGRO_EDITOR COLOR            Padstacks with shape symbol are not showing correctly9 V4 {- u4 ~5 _
922066  CONSTRAINT_MGR ANALYSIS         Custom measurement Actual not being cleared when layout changes.
% k0 i" r0 z4 m1 |0 q, F922117  PSPICE         PROBE            Label colors are not correct in Probe3 \' Y: G( S8 w) x/ M
922519  ALLEGRO_EDITOR SKILL            add_bviaarray command fails for some clines but not all5 i7 o& ]# W' k6 Q; R" T  e9 J
923224  ALLEGRO_EDITOR GRAPHICS         Thermal flash Display problem in Allegro v16.5 Hotfix S002
  C$ k6 d* }0 `- d3 z923286  CAPTURE        DRC              DRC markers not reported for undefined RefDes! o) F( U( r5 w# b3 }( ^3 l
923362  ALLEGRO_EDITOR PLOTTING         Print to Postscript file not correct in 16.59 S: B& j& _0 g& b9 \
923416  ALLEGRO_EDITOR PAD_EDITOR       Pad Designer crash on clicking on the Arrow before Soldermask_top
" J9 f7 k) B7 j' C9 e6 ]! U923507  CONCEPT_HDL    CONCEPT-PCBDW    The function of Import Design in the SPB16.5 Design Entry HDL (for data of ADW15.5_S23 + SPB16.3)7 }1 `' i, f4 p
923910  CIS            PART_MANAGER     Copy & Paste operation from Part Manager copies properties only to first section of the part.- k  N; x2 y0 l9 R; v! U8 S
923913  CAPTURE        PROJECT_MANAGER  Capture runs slow on attached design
0 T, t. F- Q( f0 l7 }2 l923937  CONCEPT_HDL    CORE             Back annotation time significantly increased with the metadata generation on7 l' x  a  d9 ?
923949  ALLEGRO_EDITOR INTERFACES       Incremental DXF_IN gives 'Invalid subclass' error
; m/ S" @) Z% _3 N3 Q* ~& G924458  SCM            OTHER            Project > Export > Schematics crashes* @# N) W$ u' ~8 G* u8 o
924621  ALLEGRO_EDITOR SHAPE            Dynamic shapes are disappearing upon updating them to smooth.
& c2 S' a' P9 P1 |3 m925193  SIG_INTEGRITY  FIELD_SOLVERS    Diffential Impedance (DiffZ0) values computed in the layer stack-up is incorrect
8 o# I; f# c0 j1 F* b! z925195  ALLEGRO_EDITOR DRC_CONSTR       Incorrect pin to shape DRC error# e8 R$ C. ?. m& f' C; ~/ c- [  f
925338  CONCEPT_HDL    CORE             This application has requested the Runtime to terminate it in an unusual way1 z! B. p$ i3 `: {! [0 r2 A
925435  CAPTURE        TCL_INTERFACE    Capture crashes if 揝ave design as UPPERCASE� option is disabled.2 X) S! \2 m; c2 g1 `% c: H
925530  SIG_INTEGRITY  OTHER            Why the single line impedance value for Top and Bottom layers are different for this design?, ^. t  L, j) T+ ]% ~% o
925864  ALLEGRO_EDITOR DRAFTING         Ability to add dimensioning to different CLASS/SUBCLASS$ R, V9 z2 }# E
925976  ALLEGRO_EDITOR MENTOR           mbs2brd fails to import data1 k0 X( T- L1 I. }
926409  SIP_LAYOUT     DRAFTING         Exporting a 16.5 design to 16.3 will cause the leader/dimesion lines to be removed.
  v) \5 u, r# K. k7 W+ D$ T& }926443  CONCEPT_HDL    CONSTRAINT_MGR   In new 16.3 "035" ISR Concept2cm will crash with error.
5 v0 X- m/ o! R926503  CAPTURE        GENERAL          Memory leak Capture/Pspice: W. Z( s* T+ c( d( X, ]% n7 U" y+ s
926553  CONCEPT_HDL    CONSTRAINT_MGR   CMGR ERROR There is no net in the Cset that has pins matching those in net 1 in the Xnet
% C" D& H% q. t8 X. m926691  ALLEGRO_EDITOR OTHER            Crash while Importing Technology File in CM, with Overwrite Constraints.
0 r  N, \5 A& o0 e926887  CONSTRAINT_MGR CONCEPT_HDL      Pin pairs lost after Export Physical6 a4 U- s- F; N0 q
927159  CONCEPT_HDL    CONSTRAINT_MGR   Export Physical fails due to errors in ConCM.log when SIGNAL_MODEL injected property is ''
* ~/ m: V7 u! n! g$ d
* m! T5 |+ T+ w/ E. r6 p6 A& P) N/ dDATE: 08-19-2011   HOTFIX VERSION: 004
; H) E( K& x5 u' v, k; x===================================================================================================================================
. ~( }+ H0 ^) B8 H5 l( v& qCCRID   PRODUCT        PRODUCTLEVEL2   TITLE
$ E5 ?7 \3 @) I: w! J===================================================================================================================================
4 |% m! H  @/ q- z785417  CONCEPT_HDL    COPY_PROJECT     copyprojectui crashes with a Windows runtime error6 W8 ?. u% h2 o( \7 }9 g- r
851044  CAPTURE        GEN_BOM          "Export BOM report to Excel" does not appear in the Standard Bill of Material Window.
: x' A- @$ S& O* ?% H868216  PSPICE         MODELEDITOR      Encryption of subckt names, internal nodes, comments5 S, B  T2 V. e$ C: }2 `
870247  PSPICE         SIMULATOR        Encrypt a model and simulate it, info about inside nodes being dumped in the probe file3 h7 |. X- ^) {3 m) V/ R  P
877091  CAPTURE        SCHEMATICS       Save JPEG, GIF, PNG and other image formats in the database in its compressed form
+ G" C, ?) E$ y2 D9 r8 d894059  CAPTURE        OTHER            Enhancement: Adding column in edit>browse>parts window$ d3 B* J/ J- [8 R9 J0 L
895902  RF_PCB         OTHER            Alphanumerical allegro pin numbers are unusable in ADS 2009 Update 1
( O3 Y/ e" Q' v* U1 M895919  RF_PCB         OTHER            Round trip Allegro to ADS to Allegro requirement2 ]6 G& _2 Y$ Y% S! U
903102  ALLEGRO_EDITOR OTHER            Zcopy shape command for cline seems not to work correctly., b/ V4 C6 A% ]+ k  G: C
905562  SIG_INTEGRITY  SIGWAVE          Noise margin seems not to be measured correctly with Eye Measure function.# y+ N6 q! E# |$ e8 S" W
909469  SCM            TABLE            ASA crashes when opening project
0 S6 `# _9 v8 A0 L. }' G909595  APD            LOGIC            Inconsistency between export die text out and show element after pin swap. W% n0 h( {  r2 G/ t# t
911123  CONCEPT_HDL    CORE             16.2 Design uprev to 16.5 fails with ERROR SPCOCD-152
6 M0 B4 r/ ?% n$ O7 U" \% {911569  CAPTURE        EE_INTERSHEET_RE Q: Why is capture assigning incorrect Irefs in attacehd design ?
& [, F: a5 n+ s/ y3 y5 I% U# ^915657  ALLEGRO_EDITOR OTHER            Allegro PDF Publisher  Mirror capability
- a, M1 _, {, |5 H! Q915755  CONCEPT_HDL    CONSTRAINT_MGR   Cannot view net in SigXP8 N; J# F- b  k" w1 g5 y3 S
916062  CAPTURE        GENERAL          Auto Wire Crashes Capture
# x! P2 Q' A5 G- n! ^5 @( r' c916820  F2B            OTHER            RF create netlist with problem6 Q3 m1 Y. R! R6 N3 E7 t' J
917967  ALLEGRO_EDITOR REFRESH          Update symbol resets refdes location for bottom side components only.
  C! L. B2 T7 [' |- s) `919343  ALLEGRO_EDITOR PLACEMENT        Place Manual is crashing the board file6 S5 v, R: g1 a& g, K
919481  CONCEPT_HDL    CHECKPLUS        CheckPlus isGlobal function is not working
5 B5 T2 D# {1 k. M( R( \919510  CONCEPT_HDL    PAGE_MGMT        takes 10 min to insert page in DE HDL0 P( O* {3 m/ R0 q* P" v
919976  APD            DATABASE         Update Padstack to design crashed APD.8 J$ a$ `( u  s6 u
920418  SIP_LAYOUT     OTHER            SiP enhancement to Auto Assign Pin Use to add ability to change the pin use definition: O  j  x9 ]. V6 e, t1 {' }3 U
920420  SIP_LAYOUT     LOGIC            SiP enhancement to Logic Auto Assign Net to display a dialouge Auto Pin Use assignment should be run- K/ @0 _) V3 y# h8 _
920712  ALLEGRO_EDITOR ARTWORK          Program has encountered a problem ... error when creating artwork6 I' G. F% i1 [0 M; i0 C5 x& S
920763  ALLEGRO_EDITOR ARTWORK          Soldermask gerber missing thru-hole pins+ z! H4 P* W% r% n
920976  ALLEGRO_EDITOR GRAPHICS         Question regarding the difference in the behavior of 3D Viewer w.r.t. height_min9 M1 |2 w$ l/ g0 Y+ q: }3 ]
920993  ALLEGRO_EDITOR DRC_CONSTR       Minimum Metal Spacing Error is detected on Same Net
4 O0 r, D$ j( U% c& k921727  ALLEGRO_EDITOR DRC_CONSTR       Pad Boundary causing P/P drc to adjacent symbol.
3 e; t" h2 r& f8 \5 z4 n. z922579  CONCEPT_HDL    CORE             Xcon file gets corrupted upon Save of Hierarchical design with Global nets tied to interface nets, U1 R3 `; l) U$ ?( F
922592  CONCEPT_HDL    CORE             DE-HDL does not report illegal connection when  Global Net  tied to  interface net using an Port symbol and named$ R0 W* J3 ~+ e3 K' Q
922758  ALLEGRO_EDITOR DATABASE         Allegro crashes while placing second mechanical symbol with route keepin8 t5 A) W' m: |6 w4 @8 S/ D
922839  ALLEGRO_EDITOR DFA              The DFA drc display is unstable.
. W1 T% Q2 V" h  Y4 \" c923293  ALLEGRO_EDITOR INTERFACES       File> Export> IDX is failing for this design while creating an empty error log.; |, v$ l( ]  `8 x8 X$ o
924772  ADW            PCBCACHE         Import Sheet is not bringing in Parts used in the source pages into target cache ptf2 d1 V  v. o% l) W5 `
* W0 `) ~( a* ^* K& Q' o1 L
DATE: 08-4-2011    HOTFIX VERSION: 003
! q& Q& H, m1 m$ r' K===================================================================================================================================! F: p. ^; E9 s+ U8 c& q; [
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE" \% [5 y8 m9 T
===================================================================================================================================
( [! v7 i, ]1 G% y4 i# Q' ?787414  CAPTURE        PROPERTY_EDITOR  Part value can抰 be moved on schematic if a part has been copied to a new design and not saved yet.
8 w( t1 l4 G# z903898  PCB_LIBRARIAN  GRAPHICAL_EDITOR PDV move symbol graphics and Undo causes corruption in graphics
( Z. t. g# k, E! y# ?0 Y( q904287  ALLEGRO_EDITOR ARTWORK          some cline with arc is missed, when creating artwork.$ A$ v/ m# U# H# y; q
904418  CHANNEL_ANALYS SIMULATION       channel analysis sim does not give valid result; J! V8 b: S0 b2 `3 f3 x0 O
905777  SIG_INTEGRITY  SIMULATION       User gets popup message that halts an analysis until it is acknowledged
" g$ S* [  X: {- `906139  SIG_INTEGRITY  OTHER            Bus sim result were cleared at the next run even if no preference changed.+ J& [4 N- q# X
908680  SIG_INTEGRITY  OTHER            Extra prop delay due to resistance
( N6 ~- X, w$ P909583  ALLEGRO_EDITOR SKILL            axlPolyOperation AND operation is not working correctly.5 y+ @+ H- T4 o- Z4 {3 X# o; E
910315  ADW            LRM              Import Design with ADW causes partmgr and pxl errors
$ q. l  {8 S. i* r: I3 m910689  CONCEPT_HDL    CONSTRAINT_MGR   NO_SWAP_COMP warning after uprev to 16.5: t: P/ r! K0 A
911684  CONCEPT_HDL    CONSTRAINT_MGR   Attribute Definitions are incompatible for attribute 'HEADER'. when attempting to place in 16.5' x6 k2 C2 D, d, C" _3 @
912343  APD            OTHER            APD crash on trying to modify the padstack: ~# w6 Y* q, P0 ^) z
912384  PCB_LIBRARIAN  CORE             PDV Symbol Editor often freezes when moving groups objects by arrow keys3 ]8 H8 {* L1 l6 u4 V
912853  APD            OTHER            Fillets lost when open in 16.3.  m8 S( i, P4 `9 z
913586  ALLEGRO_EDITOR ARTWORK          Cannot create the drill figures in this design.
% V, r% s# E2 h0 W914009  ALLEGRO_EDITOR DRC_CONSTR       Diff impedance worksheet showing almost zero impedance for differential pair in attached testcase.
. Y! i" T) A+ X. y! J/ ~1 [914110  CONCEPT_HDL    OTHER            DEHDL 16.5  Uprev overides property values  on hierachical blocks
2 [: D. E9 K6 s1 x( M914264  F2B            OTHER            Cross Probing from DEHDL for global nets present inside block doesn抰 highlight in PCB Editor.9 M. O( ^& ?$ u" v2 I& s# Z" I
914309  CONCEPT_HDL    CORE             16.5 DEHDL crash on saving the user design
! H6 g1 w7 G2 j+ a914558  ALLEGRO_EDITOR ARTWORK          Gerber6x00 output creates unpainted niche in a shape2 R, d2 ~/ ]5 V  T8 i3 D
914633  ALLEGRO_EDITOR ARTWORK          Artwork failing in v16.5 while the same design when downrev'd to 16.3 is working fine.5 k' k% L% i/ G: P/ y
914634  ALLEGRO_EDITOR SKILL            IsThrough flag for a padstack is reset3 g+ Z0 l& X0 E/ b1 g
914746  ALLEGRO_EDITOR DRC_CONSTR       DRC Update repeats takes longer on each successive pass.
4 Q, \' o$ g* z914962  ALLEGRO_EDITOR SHAPE            Corruption with Shape filling
& X1 E& h4 {' ?3 l2 f+ V! ~915583  CONCEPT_HDL    CORE             performance issues in 16.5 compared to 16.3# m* B& J; o* X& o& d5 \# Q5 i
915630  PCB_LIBRARIAN  OTHER            Error when running SI Model Interface Comparison using IBIS models
6 d4 k* t6 Q/ S7 |  z6 H6 O" {915742  CONCEPT_HDL    HDLDIRECT        I get a newgenasym error and crash when trying to save the symbol( t4 I9 n% V4 W8 [0 |8 N9 h
916154  SCM            NETLISTER        scm crashes when exporting physical database to allegro, q0 V7 L; W  X0 a
916448  CAPTURE        NETLIST_LAYOUT   Capture 16.5 Layout netlist contains errors
2 e4 t3 y4 {* n2 P" j, ?916462  ALLEGRO_EDITOR DATABASE         Edit>Split_plane>create hangs Allgro PCB Editor
/ L. J1 Z( r* A% X% `4 B916469  ALLEGRO_EDITOR REPORTS          One Unrouted pin does not show in Unconnected Pins Report) w- R% m7 L+ ~) M( C
916495  ALLEGRO_EDITOR INTERACTIV       Pick selects components from invisible (Off ) layer
5 G" i3 {2 x4 a" o* g* T916889  CAPTURE        NETGROUPS        How to change unnamed net group name?
9 T- O6 R( b+ x8 b; B( N  k" O917002  ALLEGRO_EDITOR OTHER            Allegro PDF Publisher creates extra circles not available on film
. U/ p; b! `5 j3 ^917434  APD            OTHER            Stream out GDSII has more pads in output data.
! F/ x) M& E8 n1 u+ o& V7 S+ P917739  CONCEPT_HDL    INFRA            Global Net tied to port is getting split into 2 nets in 16.5, in 16.3 it is treated as a single net( B. U8 g& Q! Z+ d7 c/ q& q
918187  CONSTRAINT_MGR OTHER            Missing acGetTotalEtchLength predicate.
0 j3 v- e% q$ s918576  CAPTURE        DRC              Incorrect DRC is reported for visible power pins which are connected to power symbol
* f& h$ m$ B  E
3 ?1 z+ L% [) J  k/ I! j4 wDATE: 07-24-2011   HOTFIX VERSION: 002% x0 R0 u0 K; m  R. R, G6 X
===================================================================================================================================
; u0 o7 g% r, L) G$ ^$ ]9 K6 RCCRID   PRODUCT        PRODUCTLEVEL2   TITLE
* H( _$ Q" C" W, h: \9 z===================================================================================================================================
' J$ g! D( [0 ]0 q! B527444  ALLEGRO_EDITOR EDIT_ETCH        Slide command needs to be enhanced for same net spacings+ e+ k+ P  i* \$ F8 |
583257  ALLEGRO_EDITOR EDIT_ETCH        Add Connect and slide command needs to be enhanced for same net spacings.( B2 M, K6 ^/ C! G  H* G7 o8 b
592956  ALLEGRO_EDITOR EDIT_ETCH        Same net traces will not push and/or shove each other.. h0 V. v/ x) v( b3 t! A
745285  ALLEGRO_EDITOR EDIT_ETCH        Requesting a true "shove" in Route > Slide for Same net routing.7 m3 G* F! W. [( i! E3 c- F
773503  CAPTURE        OTHER            Doing "Mirror Horizontally" creates extra un-connects or extra junction dots in Capture V16.3.
, M' ]1 U: x* E  e& T774270  F2B            PACKAGERXL       Require to ignore space in Pattern setting to prevent duplicated Refdes.
6 @" A8 W4 T: B) j8 M7 V799984  ALLEGRO_EDITOR INTERACTIV       Enhance the Fix command to select just cline segs
4 `; I3 {+ g& N7 f809008  CAPTURE        SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".
: P2 [$ g) i. L( j( u, }810058  CAPTURE        SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".: E! c+ E( u$ ]5 `
821133  ALLEGRO_EDITOR MANUFACT         Output artwork for pad data that are suppressed unconnected pads with Gerber 6x00 format* i/ A$ }9 V5 j& U
831710  CAPTURE        SCHEMATIC_EDITOR Capture adds extra junctions to design by itself% o& ~( c  M  P2 |8 Q' R
842410  ALLEGRO_EDITOR EDIT_ETCH        Ability to slide with "Shove" for "Same Net" segments/vias.
0 |) |4 O. K& ~7 a854971  ALLEGRO_EDITOR INTERACTIV       Capability to add cline segment in a temp group
6 m. Y$ Y) w0 j860772  ADW            PCBCACHE         Save Shopping Cart (pcbcache) is crashing component browser
/ ]/ T6 C7 J7 K5 y" v9 S$ _867842  CAPTURE        PROJECT_MANAGER  Capture crash with 'Open File Location"4 m2 t7 a- i) ^
868306  CAPTURE        CONNECTIVITY     mirror vertically removes junction creates extra nets
# z  o" z% I4 k: w- g5 p. ]882677  EMI            RULE_CHECK       bypass_plane_split fail if BYPASS_XXXX_EFFECT_DISTANCE& ^6 v6 g9 U- h7 D
891439  ALLEGRO_EDITOR INTERACTIV       moving cline segments
& u2 k; @' f" U# s! F893544  ALLEGRO_EDITOR INTERFACES       IPC-D-356A netlist issue with BB vias.
: |/ Z" Z, m. B7 s+ y" F893765  ALLEGRO_EDITOR PARTITION        Mail command not sending out email on Linux platforms.5 \; ?# _1 |/ S
894390  SIP_LAYOUT     EXPORT_DATA      Generate all balls in the xml file for export to EDI's readPackage command
0 P) {" G* `+ f# I7 l. j; K895933  APD            DATABASE         Update Symbol shifts the center of the Dynamic Fillet and creating DRCs: D+ D. G$ h* \9 L- Z/ o$ ~7 v5 A& c
896598  ALLEGRO_EDITOR PLACEMENT        error message is misleading
+ [. p0 L& I0 A; V! G# Q9 D897196  CIS            LINK_DATABASE_PA Schematic Contents are not shown in CIS window while link Dbase part for parts placed from library8 h! g7 O& x2 V2 A/ Q* m( B
898598  ALLEGRO_EDITOR MENTOR           Negative planes from Mentor Board Station not being translated.
# n4 `/ L2 L  i+ u899556  ALLEGRO_EDITOR ARTWORK          Import artwork seems not to work correctly.
0 P4 \. M% N0 U6 B900501  ALLEGRO_EDITOR PLACEMENT        "lace Replicate Apply" is showing lot of DRC's during placement of replicated circuit in 16.5- n5 k0 g* u8 ]+ H3 F0 @. D  B
901141  CIS            EXPLORER         Japanese character appear garbled in CIS explorer window.5 Y* {' S4 |( E- ?' `4 [, e
901666  CAPTURE        OTHER            Home page of Flowcad-Switzerland and Flowcal-Poland is not preserved on captre restart on start page
# J5 L' I( \$ r3 i7 m902066  ALLEGRO_EDITOR DRC_CONSTR       Shape in Region not follow the constrains
6 y$ C' \4 G; z& W902349  CAPTURE        LIBRARY          Capture crashes while closing library
8 I. P+ L" w: h! e" `902508  F2B            PACKAGERXL       SPB16.5 Packager-XL consumes much more memory than 16.3
- c) _! c' x* W7 P- F! x9 Q* m902841  CAPTURE        GENERAL          Capture Start page does not show  Y0 q0 L8 a1 ]
902876  F2B            PACKAGERXL       Packager fails on the design upreved in 16.5  f8 s* ^; N; k  V) @& j- }
902959  CONCEPT_HDL    HDLDIRECT        HDLDirect Error while saving design
2 h% i6 k' P* Z: `6 y  i903171  PSPICE         NETLISTER        Why Capture is treating hierarchical power ports as floting nets in complex heirarchy designs?) U# s7 b4 J' H. V: t
903713  ALLEGRO_EDITOR PARTITION        Placement Replication do not work fine in the Design Partition
% ^# Y3 q, z9 J- \903799  SIP_LAYOUT     DIE_EDITOR       Disappear die pins after exiting co-design die editor# R3 C, s: e) W* R9 ]
904021  ALLEGRO_EDITOR OTHER            Export PDF from SPB 16.5 produces a file not text searchable$ ^! ^6 Z* K1 ?' N# L1 g5 i6 W
904339  CONCEPT_HDL    CORE             new design crashes using the attached CDS_SITE
1 g; D' \. g- g, ]  x! W- c9 z2 P4 i904522  F2B            PACKAGERXL       Part will not package in 16.5  but packages in 16.3+ k( T( k4 C4 A: {* Q
904764  APD            OTHER            Enhance Scale Factor of Stream Out to support 4 decimal places+ d. v  g4 Q# c- P' P
904771  ALLEGRO_EDITOR MANUFACT         Pin Number display issue.
/ n8 {9 \" @7 J: ]: }  v904853  ALLEGRO_EDITOR GRAPHICS         Enhancement for showing Static shape as it was seen in 16.3
. g. M0 O/ \* m% Y905144  CONSTRAINT_MGR ECS_APPLY        Min Line Spacing is larger than Primary or Neck Gap less(-) Tolerance but No Warning in CM/ E# a2 M0 Y+ y' p
905314  F2B            PACKAGERXL       Import physical causes csb corruption$ _0 t/ s  S: \! O9 \8 l3 s) K
905337  CONCEPT_HDL    CORE             ConceptHDL crashes after Import Design process.
* L7 u& U2 l7 Q. n8 i0 A8 @905533  ALLEGRO_EDITOR INTERACTIV       Pin numbers for components on BOTTOM Side are moved in Preselect mode,when the BOTTOM layer is invisible3 B' ~6 Q' C) _0 r& e
905796  CONCEPT_HDL    CONSTRAINT_MGR   Fujitsu CM issue inaccurate concept2cm diff pair issues. o, T* m! O" m% k6 Z0 U4 L
905811  CAPTURE        EE_INTERSHEET_RE interesheet references in the form of grid grid page number instead of page number grid5 U3 k$ c, a9 P3 h9 d2 L
906118  CONCEPT_HDL    CONSTRAINT_MGR   Cannot open CM if SIGNAL_MODEL value was not assigned in ptf.+ b$ X% P  ]  e# T# e* a
906153  ALLEGRO_EDITOR SCRIPTS          Unable to run allegro script in batch mode on the attached board.& V6 u+ I9 l4 j
906182  APD            EXPORT_DATA      Modify Board Level Component Output format
) L- _4 |( N+ h: ]906200  ALLEGRO_EDITOR DFA              Enh- DFA drc invoked in Batch mode returns false constraint value in Show Element
6 H5 D0 s2 k5 n' x4 H0 |906517  PSPICE         PROBE            PSpice new cursor window shows incorrect result.3 I% j  v) w! j" X4 X5 U
906627  ADW            COMPONENT_BROWSE ppt options are not read if ucb is launched from FM. works fine if launched from dehdl.
( A; l2 |8 T% c' _* G906647  SIG_INTEGRITY  LIBRARY          lib_dist creates a signoise.log in current directory (with backup files like ,1 ,2 etc.) on each run& E6 q" J5 L9 t( `  G5 n
906673  F2B            PACKAGERXL       Ignore the signal model validity check during packaging8 h7 b3 `! ?3 j' t$ g1 @
906688  ADW            LRM              A copy of source design gets created in worklib of target design after 'Import Design'" m: N4 P$ ?( ~! d0 z
906750  ALLEGRO_EDITOR PARTITION        Importing design partition removes the testpoint reference designation
8 D+ _* [6 y1 b! [1 w0 V906874  PSPICE         NETLISTER        Error less than 2 connections for unconnected hierarchical pin
6 c8 x. T) v! U907095  F2B            OTHER            Part Manager does not show Error as Undefined when directive ptf_mismatch_exclude_inj_prop is used
' _/ D  q9 d9 A; w/ [2 {% O: ^  ?907424  ALLEGRO_EDITOR GRAPHICS         Allegro add option for pre 16.5 shape display
" p+ o3 o/ P# [* h+ j907490  CAPTURE        NETLIST_LAYOUT   16.5 Layout netlist is not correct. It differs form 16.3 layout netlist.% T- U  x% w" p! L: [, u
907884  SIP_LAYOUT     MANUFACTURING    Need to add an "NC" pin text option for "Manufacturing Documentation Display Pin Text"
+ ]/ h2 W% U8 ~/ e9 f8 s1 O1 l* r907885  SIG_INTEGRITY  OTHER            Matchgroup targets lost when importing netlist  to Allegro layout in HF31# U# N9 n$ t( p) A
907929  CAPTURE        TCL_SAMPLE       TCL command to delete a property from parts in a library is not working correctly- x# {: s! b# g- }2 R1 L
907933  SIG_INTEGRITY  OTHER            Single line impedence not working in OrCad PCB Professional; ~# f" `1 T9 h) g
907963  CONCEPT_HDL    CORE             Design uprev issue when moving from 16.2 to 16.5
2 n$ ]: P( m* f2 {9 v  c% ~1 y908000  SIG_INTEGRITY  OTHER            Inconsistence z-axis delay reported on Tpoint when define at via location.
1 |1 S  G/ ^& x5 R908057  CONCEPT_HDL    CORE             DE HDL crash with the cut and paste of a signal name" V, d1 ?( N: W. ?
908060  CONCEPT_HDL    CORE             CTRL+LMB Option not working correctly in 16.3' S. Z+ h4 L( L* O
908210  CAPTURE        CONNECTIVITY     Connection is being lost while dragging a component
  u2 \. F4 W( W% M: D* b6 d908241  CAPTURE        DRC              DRC error column is blank in DRC markers window in 16.5/ X& {6 m( o. {' V. c
908339  RF_PCB         BE_IFF_IMPORT    mechanical holes VIAFC are not at the right place4 x1 A1 N/ o1 k7 p: ?
908534  SIP_LAYOUT     SYMB_EDIT_APPMOD issues with symbol editor and copying pin arrays
7 Y) x9 C) m; A/ d6 n. i  p908535  F2B            DESIGNVARI       When I try to view my variant file the variant editor crashes. g5 S2 i( n3 x
908595  APD            3D_VIEWER        Cadence Design 3D viewer" screen pops up and is all black because the colors have all converted to b
9 D* n1 U% B: K; |/ ]' w3 y908849  CAPTURE        ANNOTATE         Getting crash while annotating the attached design& e+ M' y  Z1 ]
908874  CONCEPT_HDL    CORE             Part Manager - No Part Found error when using CCR# 775788 feature1 q: x# {. q1 T3 g: w. v0 D+ `
909077  CONCEPT_HDL    CORE             After packaging pin numbers remains invisible even when $PN1 R+ q0 R- d8 @& W% u# o
909104  ALLEGRO_EDITOR SYMBOL           Warning message needs to be modified. It does not save the symbol and also not tell the actual problem.
, z+ Z! N/ m  `; A* n  u; H3 E. ?5 Y909417  ALLEGRO_EDITOR REPORTS          "report -v upc" returns 'Segmentation fault' on Linux
3 w9 g- l) l/ D1 N: j2 a909635  SIP_LAYOUT     DIE_STACK_EDITOR Add Interposer crashes in SiP Layout
- Q& X7 Z$ O* i# e" ?909749  ALLEGRO_EDITOR MANUFACT         Allegro Crash during dimensioning
8 u- A% ~2 }1 |909760  SIP_LAYOUT     MANUFACTURING    Create bond finger solder mask doesn't follow the mask opening as defined in the padstack0 W7 h6 _2 ]: x8 D5 U5 Q
909861  F2B            PACKAGERXL       NetAssembler broken within the latest 16.30.031# x7 _1 i. b! p1 t( Z* {4 g" ~5 y
910006  CONCEPT_HDL    INFRA            Motorola design fails to uprev from 16.3 to 16.5, xcon file is getting corrupted.
9 s( e" Y" B( O( a$ A% `' u! }910141  CAPTURE        NETGROUPS        Modify NetGroup definition does not update Offpage Connector
& q! ]$ R& c7 }6 B9 J910340  ADW            LRM              Import design in schematic, only 1 page import,  the entire block is getting imported.
& n; V" R) H* y1 J$ v, F910678  SIG_INTEGRITY  OTHER            The Analyze> Model Assignment> Auto setup is not creating/assigning models to discrete components in 16.5! @2 W6 k1 q/ o$ N: @0 f
910713  F2B            DESIGNVARI       Variant Editor crashes when you click web link under Physical Part Filter window.) p/ W2 g& }8 Y2 X- }: }! h- A
910936  F2B            PACKAGERXL       ConceptHDL subdesign net name is inconsistent1 X  P9 ?$ `  `1 x( w
911530  ALLEGRO_EDITOR SYMBOL           Package Symbol Wizard does not create symbol with the name given5 u+ Z- w- T! G* p6 r2 B# |. S9 L$ ~
911631  CONCEPT_HDL    CORE             DEHDL crashes when opening a design
. y8 q" m5 _- B9 `' a912001  ALLEGRO_EDITOR OTHER            option_licenses entries are made in allegro.ini even when not set as default7 G( d4 R3 q/ N! a
912459  F2B            BOM              BOMHDL crashes before getting to a menu! b, G* B, a3 k( _2 k1 I' ?# r6 h
913359  APD            MANUFACTURING    Package Report shows incorrect data$ c) k- u7 D2 _6 t) C9 Z' {; F2 V
1 N+ [# n3 d5 }1 D* f
DATE: 06-24-2011   HOTFIX VERSION: 0019 C, Z6 Z4 }! Q( W" `2 M- m
===================================================================================================================================
" {5 F; H6 }# U+ H* ZCCRID   PRODUCT        PRODUCTLEVEL2   TITLE: I* L8 Q0 c# j& @. J
===================================================================================================================================
" I: {& D) G& w" M7 A% S7 ~293005  ALLEGRO_EDITOR DATABASE         Allegro crash when attempting to move mech. symbol
& h0 B# u& X2 B1 ^- N298289  CIS            EXPLORER         CIS querry gives wrong results
4 H% M2 ^2 M) Q4 S$ n366939  ALLEGRO_EDITOR OTHER            Cannot attach refdes on silk subclass with add text8 X! b, F9 ?3 g8 j/ I2 g+ y% ?
432200  ALLEGRO_EDITOR MANUFACT         Fillets with an arc are required for Flexi designs
3 `- {; A( [9 I: f443447  APD            SHAPE            Shapes not following  the acute angle trim control setting.
5 {* l* l3 e7 Q9 [1 k9 W473308  PSPICE         AA_SENS          Passing variables to lower level blocks using subparam
! b# O: t1 U0 O5 O. S- w517556  PSPICE         AA_SENS          Advanced Analysis does not support variables being passed down the hierarchy. [. T  \3 S8 X) k9 A
548143  ALLEGRO_EDITOR SHAPE            Dynamic shpe on Etch TOP will not void properly.2 X* V4 A: T) Q( P2 M% k  {8 f# [
606959  ADW            COMPONENT_BROWSE Key properties with blank values are not getting read in shooping cart) _2 a. u  j* e. y7 g, Q- S, e
616466  ALLEGRO_EDITOR SHAPE            Solid shapes are not getting filled+ c9 Y5 H' O) H2 V, \9 {
641358  SIP_LAYOUT     DIE_STACK_EDITOR Request for Via and Multi Layer Pin support for DIE stack Area (blue region)$ K9 H3 i% Z/ Q3 Y( N
644122  SIP_LAYOUT     OTHER            SiP Layout - xsection -  ERROR Adjacent conductive layers are not allowed, but these are diestack layers not conductor
) B5 G% \" q7 \4 ^6 ^, t645816  ALLEGRO_EDITOR SHAPE            Slide a cline all removes gnd shapes on board
! g, E3 d8 H" M" C725355  ALLEGRO_EDITOR SHAPE            User can not voided Logo correctly.
% Y1 D7 A/ a6 z( @( E( z763569  CONCEPT_HDL    CORE             Display status of Hide/Show unconnected pins icon in DE HDL UI) p) n; w+ k5 b( |
770021  CAPTURE        BACKANNOTATE     Changing pin group property after pin swap resets pin numbers
* k4 @5 K2 {( V792126  CAPTURE        PROPERTY_EDITOR  Attempt to change display for occ prop resets5 x( Y) C1 E- `. n8 Q
799014  CONCEPT_HDL    CONSTRAINT_MGR   concept2cm errors not shown in export physical after hier_write
2 _( C; U' w8 M' b803147  CIS            LINK_DATABASE_PA Link DB part should not change RefDes of multi package part0 n) T# ~& ~0 ?
804240  PSPICE         DEHDL            Problem in simulation result for a multi-section split part.5 T" ?8 J; m, s" a& S8 \
809118  CAPTURE        NETLISTS         ENH to compare two schematic Capture designs
* W6 r( C  a! P* h  n816568  ALLEGRO_EDITOR SHAPE            shape disappears when update to smooth.. State no etch
+ D  r' m' J* ]1 v5 e: L9 j8 ~830053  CAPTURE        STABILITY        DXF export fails if schematic folder name as /. y. V9 q1 ^4 L- }, G
832108  ALLEGRO_EDITOR SHAPE            Shape void incorrectly.: C2 n% s8 M, V
833542  CONCEPT_HDL    CORE             PDF publisher font is NOT WYSIWIG with respect to what seen in DE HDL
) ^) G7 ^. c4 o835777  CIS            DERIVE_NEW_DB_PA For XLS, donot display table as worksheetName$worksheetName to avoid 8012 error
2 }% I  N" J2 S3 V837640  CIS            GEN_BOM          date format of CIS BOM has broken macros of 16.2 in 16.3 version4 Z" S. p* H: f# S6 T
844074  APD            SPECCTRA_IF      Export Router fails with memory errors.
3 B0 c2 m% T& G/ A5 K9 r, V851595  CONCEPT_HDL    CORE             Pin numbers overlap on the pin and increase in size# o0 Y8 a/ h2 E/ {; }
852832  CAPTURE        BACKANNOTATE     Why is Capture crashing with Mentor back annotation?
6 j; v  \; V& _/ {$ P855015  ALLEGRO_EDITOR OTHER            The rats are NOT connecting to the ends of the clines like they should be.
- z# {* Z: _- y9 `859883  CAPTURE        NETLISTS         ENH to compare two schematic Capture designs/ F! F  b  Z. z0 m$ D; J
866009  SIG_INTEGRITY  OTHER            Net with Pull-up/down should not be used for Diff-pair.
% T* _. c+ h8 `1 H3 S. C866830  SCM            REPORTS          Multiple lines added as separator between title block and report header instead of single line
6 Y! ^2 z9 p2 L866833  SCM            REPORTS          Extra indentation is left in the left side of the report when the Line Numbers are set to OFF
6 u5 V9 X' d3 l" E/ z" V868618  SCM            IMPORTS          Block re-import does not update the docsch and sch view
7 _3 U" n. t& o& y873402  SIP_LAYOUT     LOGIC            pin swap for co-design die in SiP( |8 b, u3 F8 F  @3 Y; o4 C: ~
874010  SIG_INTEGRITY  OTHER            PCB SI crashes when the Xnet is extracted with VARIANT_TO_IGNORE property.
  ~- J& G& u3 p# C8 G/ Z% \7 p874400  ALLEGRO_EDITOR INTERACTIV       Flip mode issue with move command
5 h$ m. K) n# s- Z874966  ALLEGRO_EDITOR INTERFACES       Placed mechanical component do not get Ref Des or part number in IDF file- _0 Z8 l  c1 q! N  ^/ R1 K
875709  ALLEGRO_EDITOR REPORTS          Film area report generated incorrect data at l1' e9 h' x; W7 n/ P! N% b# h# p
876275  CONCEPT_HDL    CONSTRAINT_MGR   Constraint Manager not retaining target net! q* Q1 p; @3 c& S0 y
879361  SCM            UI               SCM crashes when opening project3 h/ M2 M6 {6 F( R( ~1 F) @+ A) {
879496  CONCEPT_HDL    OTHER            Customer wants to have the tabulation� key as separator in HDL BOM./ N. L0 @1 w3 _0 w% u
879514  PSPICE         AA_MC            Monte Carlo to handle equation as comp VALUE.
6 j; i1 A1 o! Y% t; X/ o8 i881845  ALLEGRO_EDITOR SHAPE            Delete island deletes complete shape
- D9 p$ d$ P" j9 Y$ y3 n882413  PDN_ANALYSIS   PCB_PI           PDN Analysis should support routed power nets. }2 b+ l& t) `
882427  PDN_ANALYSIS   PCB_PI           PDN Analysis target impedance should have a variable multiplier( Z# Y8 D  ?! ]( S9 w0 R) E  j
882567  SIG_INTEGRITY  OTHER            PCB SI crash if boolean type prop was specified to VARIANT env.  @, w! @( K& y2 S
882644  ALLEGRO_EDITOR PLACEMENT        PCB  Place Replicate Function automatically match Enhancement
# L- J$ U0 w5 [9 T+ T6 ^6 l* \883164  ALLEGRO_EDITOR INTERACTIV       Vias marked fanout moves away from position when moving component- d% _. N- S) z$ R5 b, A; o; @
883224  SIG_INTEGRITY  SIMULATION       crash while reflection simulation from Constraint Manager
! w/ |- l6 v) b883760  PCB_LIBRARIAN  METADATA         Incorrectly formatted revision.dat file in the metadata folder9 V$ U! m6 q: M1 h; t! T
885391  SIG_INTEGRITY  SIMULATION       RLGC data sampling algorithm and w-element interpolation.
8 {' o( E1 F2 x& N: |885849  ALLEGRO_EDITOR MANUFACT         Silkscreen Audit cannot find Solder mask for the text string' d) d8 w# A* ^$ t# G: C; B9 X9 A
885996  SIG_INTEGRITY  OTHER            The effect of sn_maxwidthlimit user preference is not seen in cross section impedance calculations
2 I* g0 R5 t3 k4 B0 H7 G886090  ALLEGRO_EDITOR INTERACTIV       Add Arc w/Radius does not snap to grid0 H6 ]; Z% e* ^0 }
887180  CAPTURE        SCHEMATIC_EDITOR Signals Navigation window doesnt get updated for Buses
  V% m/ C  h" V) c$ ]  y/ R1 V$ O887442  APD            SHAPE            Copper pour of Dynamic shapes on Top layer which contains many existing signal traces fails.
$ o/ i* E9 w: ?( U887578  SCM            AUTO_UI          Component Replace pops-up the DSPANE-204 Message
# h3 a9 W2 ?8 u) F- O887926  SIG_INTEGRITY  GEOMETRY_EXTRACT Field solution failed if diff trace on bottom doesn't have reference plane.; `0 |. }. ~: ^2 V' \
888414  SIG_EXPLORER   OTHER            View Trace Parameter display the thickness of dielectric incorrectly./ L3 T! m& ^! R1 N( W. W' @9 `: J
888600  CONCEPT_HDL    CREFER           Cross References not added to Schegen schematic" }  n) [# v0 V/ j" c6 E6 W
888679  SIP_LAYOUT     SHAPE            Can't create the Dynamic shape on layer M1_sig without unwanted horizontal openings appearing.6 N7 r* E  P  ~2 q9 R/ H& i9 K
888804  ALLEGRO_EDITOR OTHER            Fillet will become static shape after import from partition board.
, ^- q* b8 l! s7 z888945  CONCEPT_HDL    OTHER            unplaced component after placing module) c7 a% S( l4 M+ b5 s+ c
889222  ALLEGRO_EDITOR SHAPE            Allegro freezes/hangs when adding shape as Polygon with OpenGL ON.
+ @- `3 W3 z7 ^. ^) c5 i! ]+ Y889365  SIG_INTEGRITY  GEOMETRY_EXTRACT top/bottom trace impedances extracted to sigxp are wrong in 16.3* k. f! A4 Z2 M3 ~6 |  \
889404  ALLEGRO_EDITOR OTHER            Incorrect pad size for Top conductor padstack written to column 59-62.( I9 q7 q" g6 v8 {
889426  CONCEPT_HDL    CHECKPLUS        CheckPlus does not find single node net; F) U+ J! D" \1 ]. M5 M9 f/ w6 S+ H
889636  ALLEGRO_EDITOR MANUFACT         Incorrect spelling of "Visibility" in "Film Control" tab in the Artwork Control Form$ ~: D8 ]$ ]7 q
891235  F2B            PACKAGERXL       Packager crashes without creating a pxl.log file
3 j$ _8 ~5 o$ A/ D891292  ALLEGRO_EDITOR SHAPE            arc routing causes weird undesireable shape fill performance* S/ S2 ]( f3 d  t( N5 z0 m
891856  ALLEGRO_EDITOR EDIT_ETCH        crash when sliding diff pairs/ f) g( n5 C8 j( o4 d2 v
892375  ALLEGRO_EDITOR PLACEMENT        Place Replicate Update disband other groups, irrespective Fixed property added or not.& H; U5 b1 y7 P
892455  ALLEGRO_EDITOR SYMBOL           Why the overlapping pins are not reported with DRC?
! g# t  k$ I8 ]6 F892541  SIG_EXPLORER   OTHER            Export/Import layerstack through the technology file is changing the layer thickness& Y# a, b1 B$ Y# S+ }
892766  APD            WIREBOND         Excuting Finger moving cannot push aside finger to move with together by shove all mode6 C- b/ _! L$ h& j% ~! N
892907  ALLEGRO_EDITOR DRC_CONSTR       DRC not reported for etch_turn_under_pin violations1 @  S( w% \# m9 ]2 y
892963  ALLEGRO_EDITOR SKILL            Bad shape boundary created after axlPolyOperation 'OR
& e# I6 \! Q+ @892964  SIP_LAYOUT     LOGIC            Request that Edit Parts List use Dashes "-".& _" Z7 I, w9 b( b! J
893295  APD            WIREBOND         Why move wirebond command does not shove wirebonds? This result in drcs.
7 T: o1 C, ~( C9 }# w893706  CONSTRAINT_MGR OTHER            On line DRC hangs on partitioned board. x0 p& z0 [7 h: p' J
893743  APD            EDIT_ETCH        Route behavior when spanning pads not as expected.! x8 c  P5 P  y
893783  SIP_LAYOUT     OTHER            Padstack Design Editing update File menu with a Update to Design and Close instead of 2 operation
8 A* j# P9 z) f# k, d' u894456  ALLEGRO_EDITOR REPORTS          Request Net names be added to Propagation delay lines of the DRC report.! y; F8 @. ]  E  m8 y/ v5 Y
894499  SIG_INTEGRITY  LIBRARY          Tool crashes when moving a cline or selecting the Info icon with OpenGL on.
1 d4 l& g' u5 m$ N4 e  H% ?5 {! G894582  APD            SHAPE            When making a dynamic xhatch Via shapes surrounding are abnormal.
1 ]* y7 T. @) F. c895542  SIP_LAYOUT     WIREBOND         SIP design crashing when moving bond finger using blur mode BLUR_BONDFINGER_PRESRV_CON
' d1 E  S: R6 z895591  ALLEGRO_EDITOR PCAD_IN          Importing PCAD file fails to get to the point where we can map layers/ h! @6 }; k, A" Q* P' I$ @
895757  APD            ARTWORK          Import Gerber command could not be imported Gerber data
9 c& e9 y. C8 [  [; F5 M. ^895964  CONCEPT_HDL    CHECKPLUS        The CheckPlus command getFileSubstrings is not working correctly' I7 v1 l% G$ h/ W7 l- h
896428  SCM            UI               Changed Ref Des value not maintained in DEHDL block when part is replaced6 M; t. Q% g! ?& S* U
896655  CAPTURE        EDIF             Import/Export Design of Hierarcy design with OrCAD Capture& O1 d  M9 \3 p
896846  CAPTURE        IMPORT/EXPORT    Import edif2cap and capture is crashing7 R/ }6 b7 T  @( @
897155  ALLEGRO_EDITOR REPORTS          Copper coverage in L2 and L7 looks like the same but film area report had large gap.
% ]9 {7 G/ U  O5 j897654  CAPTURE        EE_INTERSHEET_RE Capture crashes on adding intersheet refernces in abbreviated format on attached design.' M% r3 s3 b# ]: A+ W: N- P' P
899344  RF_PCB         BE_IFF_EXPORT    dlibx2iff does not provide the component boundary drawing
- X8 |* r0 t+ d; k+ ]899629  CONSTRAINT_MGR OTHER            ECset for Total Etch Lenght is not present in OrCAD Prof
8 ]7 S9 w; X; E- C900175  CONCEPT_HDL    CONSTRAINT_MGR   Few Xnets are lost from Match Group after packaging and importing the netlist to board file.( f0 m' V) `$ F. e
900481  CONCEPT_HDL    CORE             Genview creates a larger symbol without taking the no. of pin in consideration
+ R- F4 l# G; E900813  ALLEGRO_EDITOR DRC_CONSTR       With rotated pads, pad (pin - via) soldermask spacing DRC is unreasonable.6 Q8 e$ a5 u5 \, v0 l
900905  PSPICE         STABILITY        Simsrvr crash and RPC Server unavailable error while running simulation.1 i6 B  f  W& \2 O8 ]! A! F
901783  CONCEPT_HDL    CORE             CDS_PART_NAME is annotated on the schematic canvas after running back annotation in 16.5& K1 l8 W3 L  p  o% A% M
901909  APD            EXPORT_DATA      The "package_pin_delay_length.rpt" with Z-axis delay turned on seems wrong
  D* r# x- c! A2 d; i& r901987  CONCEPT_HDL    OTHER            SPB16.5 zoom fit does not center the page while ploting the schematic page
/ V4 @" m! Q' v  u! r  n/ Y9 [# d902133  CIS            OTHER            The visible part property value are being shown very distant from part graphics on schematic0 Y' ^" H8 \' m2 [. G7 u
902166  SPECCTRA       ROUTE            Specctra crashes when reading in "bestsave.w" file
( s' x( U, Z8 }) z, H902170  ALLEGRO_EDITOR DATABASE         Diffpair Issues with OrCad PCB Designer Professional
% u, @, D/ z6 V; U4 y8 g902177  CONSTRAINT_MGR CONCEPT_HDL      Option to view the layer thickness in CM worksheet through worksheet customization
$ Q4 G0 d7 ?2 ~# t902463  ALLEGRO_EDITOR INTERACTIV       APD crashes when we click ( show element ) on certain components2 i) m# K1 V* a9 N
902621  CONCEPT_HDL    OTHER            Design Differences (vdd) Crashes( _: ~* w, _4 t2 g
902909  APD            WIREBOND         die to die wirebond crash  `: [# M3 p8 Q5 w
902933  ALLEGRO_EDITOR PADS_IN          Pads_in fails while reading PADS ASCII file body
$ p' {( h% |% c903284  PDN_ANALYSIS   PCB_STATICIRDROP IRDrop voltage gradients are plotted outside of the PCB outline
1 n& x' Z1 T) S+ N, j903680  CONSTRAINT_MGR ECS_APPLY        Constraint Manager not passing all hiearchical member objects to a custom measurement.& \$ L% g5 u) d& M
904403  ALLEGRO_EDITOR DATABASE         Allegro crashes when refreshing module
作者: penny190    时间: 2012-2-21 15:01
有沒有搞錯~~一個月出了兩個HOTFIX+ u' V0 x7 o  ?! D! ]8 @
到底有多少問題
作者: cxyjoe    时间: 2012-2-21 17:40
没看到下载链接啊
作者: jingjing4996    时间: 2012-2-24 18:21
什么东西
作者: ice-river    时间: 2012-2-24 20:03
乱七八糟！
作者: ice-river    时间: 2012-2-24 20:04
给个hotfix链接者硬道理！！
作者: zhangyg    时间: 2012-3-1 17:17
有链接吗？
作者: 蛋炒翻    时间: 2012-3-1 18:45
秘密收藏
作者: ACTODC    时间: 2012-3-2 11:02
这个是什么啊，是补丁的内容吗- [0 a8 E- O* |. U
作者: promissingwh    时间: 2012-3-2 16:50
看起来好象是好东西，有点儿像命令，但是不知道用来做啥的呢？
作者: meimei5192    时间: 2012-3-8 15:09
作者: piedgogo    时间: 2012-3-8 15:17
本帖最后由 piedgogo 于 2012-3-8 15:19 编辑 / h, X& U" y) p/ ~
5 l1 V7 _, T- z2 ]
噗，没认真看
作者: yangtse427    时间: 2012-3-9 09:08
看不懂
作者: kbhf518    时间: 2012-3-12 22:27
表示压力很大 啊！
作者: hellojazz    时间: 2012-3-12 22:44
这是什么
作者: wuyinhe    时间: 2012-3-13 08:41
是什么呀
作者: xjlovex    时间: 2012-3-13 18:30
這是個什麽情況啊····求解釋
作者: lolen    时间: 2012-3-15 14:22
1
: G" p3 t/ X4 L% g" U
作者: tuzhiquan    时间: 2012-3-15 17:14
:'(
作者: s59710210    时间: 2012-5-21 11:31
?
3 e0 i1 t3 c" X& D5 O$ ~
作者: d10miao    时间: 2012-5-21 13:19
什么东西？
作者: smileduty    时间: 2012-5-22 21:04
这个是你安装补丁以后，在程序\Cadence\Release 16.5\README CCR这个文件里面的内容，就是更新说明
作者: Vincent.M    时间: 2012-7-21 12:47
什么东东？
作者: xiyuziju    时间: 2014-12-23 16:53
这些是错误吗，有没有相应的解释造成的原因和解决方法、
作者: winson_wei    时间: 2015-10-28 17:02
发课》法克：伐客？
作者: maikll    时间: 2015-11-2 13:27
什么情况， 不懂
作者: 书生    时间: 2020-9-9 21:40
看看有啥，好好学习，天天向上



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