EDA365电子论坛网
标题:
生成网表出错
[打印本页]
作者:
zxb3558493
时间:
2011-9-17 19:19
标题:
生成网表出错
看了于博士的视频，想把某一页的原件快速放到pcb上，添加page 参数，设置page参数，按照视频上的 ，设置输出网表参数。
5 l' I: s8 Q: W" J# d$ N8 P3 ~
出错了。
' h+ y7 R/ L; n: T2 s
以前能够正常输出网表。 那个大侠能帮忙啊
6 P m% Y/ ]+ {: i
session log的内容如下：
+ V: x. f9 {" c& q
Design Name:
_. b7 u1 [- o/ q! M. \% F: N
G:\lianxi\dsp\dsp.dsn
' E# l8 V, T3 `* \8 g" D
Netlist Directory:
5 G3 r1 j3 Q( U: I! u8 o
G:\LIANXI\DSP\ALLEGRO_PAGE
, L! V7 h: @$ l9 |$ j
Configuration File:
4 C! C2 U( J* I2 G
D:\Cadence\SPB_16.3\tools\capture\allegro.cfg
, X0 V i* S" Z% u
8 o! u: j/ s, s: Q
Spawning... "D:\Cadence\SPB_16.3\tools\capture\pstswp.exe" -pst -d "G:\lianxi\dsp\dsp.dsn" -n "G:\LIANXI\DSP\ALLEGRO_PAGE" -c "D:\Cadence\SPB_16.3\tools\capture\allegro.cfg" -v 3 -l 31 -s "" -j "PCB Footprint"
1 L- S z E% g1 C w
#1 Warning [ALG0051] Pin "GND" is renamed to "GND#1" as visible power pin of same name already exists in Package AUDIO_RJ , J6: SCHEMATIC1, OPA_BUF (360.68, 53.34).
" D8 _3 k8 N) Z& G7 ^3 L9 I
#2 Warning [ALG0051] Pin "GND" is renamed to "GND#6" as visible power pin of same name already exists in Package AUDIO_RJ , J6: SCHEMATIC1, OPA_BUF (360.68, 53.34).
: \+ u) r# B- O2 v5 `) P+ D
#3 Warning [ALG0016] Part Name "SW PUSHBUTTON-DPST_RESET_DSP-RESET" is renamed to "SW PUSHBUTTON-DPST_RESET_DSP-RE".
5 J( ]8 e; S4 |+ P ~( f6 l
#4 Warning [ALG0016] Part Name "TMS320C6713GDP_BGA272DSP_TMS320C6713GDP" is renamed to "TMS320C6713GDP_BGA272DSP_TMS320".
; j. l: ~. p) r3 o" y$ {" B
#5 Error [ALG0013] Conflicting values of following Component Instance properties found on different sections of U6.
& K0 O T. a! Y* e& s1 h i- c j
PAGE
( X' S) { W8 F* t
#6 Error [ALG0013] Conflicting values of following Component Instance properties found on different sections of U6.
' E- t9 I: C: a! [9 M% @' i
PAGE
, f8 A) \1 w5 d9 \
#7 Aborting Netlisting... Please correct the above errors and retry.
. X/ T7 i6 g1 j& ^6 q
9 z) P9 H t* c( c. l6 x) _7 Z
Exiting... "D:\Cadence\SPB_16.3\tools\capture\pstswp.exe" -pst -d "G:\lianxi\dsp\dsp.dsn" -n "G:\LIANXI\DSP\ALLEGRO_PAGE" -c "D:\Cadence\SPB_16.3\tools\capture\allegro.cfg" -v 3 -l 31 -s "" -j "PCB Footprint"
4 O; l, ?3 X" i2 h* V
4 y' }9 k7 `, G+ D- Y$ z
, ?% S$ U4 `$ {
*** Done ***
# o3 W& j6 c5 p
作者:
gn165625076
时间:
2011-9-17 19:45
U6不同部分发现相互冲突的元件实例属性？
6 l: r" [3 M! ^ W# w8 M7 e# V
大概你是层次设计的吧？
B8 P. C" p! [" e5 b
我没用过层次设计，不大了解啊。
欢迎光临 EDA365电子论坛网 (https://bbs.eda365.com/)
Powered by Discuz! X3.2
