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Solder Mask - A green layer of Solder Resist is coated on the external layers of a PCB to prevent the copper from oxidizing when exposed to air for a long period of time. The Solder Mask is the opening that exposes the Pad for Soldering, preventing the solder from flooding the adjoining copper. J! S5 U" J% R8 k4 H! D( }, M
Pad - Through Hole Pad has large hole and is used for mounting and soldering Leaded Components to the board. Via pad is usually smaller as it is only used for inter-layer connection. Surface Mount Devices, the pad does not have a hole in it. ' y `: v! @& D. ~
Solder Paste Mask - Solder Paste are used only on Surface Mount Devices, the paste is made up of tin and silver alloy which is printed on Component Pads by pressing it over the Solder Paste Mask. It melts into liquid form when passing through a Reflow Machine and solidifies as it cools attaching the pins of the component on to the pads. ! n' R) M* V+ v+ A4 P1 y6 D4 _: _: ZPlated Through - The Plated Through Hole is used for inter-layer connections, linking the electrical Hole signals from one layer to another by plating the walls of the hole with metallic alloy. The Through Hole Pads and Vias in multiple layer designs have plated through holes. The plating also serves to improve mounting strength for Leaded Component. . t; k/ h$ H* R$ x# P: x8 \% HRelief Connection - To prevent the heat from leaking too fast from the pad to the plane, creating Cold Joints, Air Gaps are introduced. The resulting Relief Connections are used for connecting the copper plane to the pad or via having the same Net. Plane Clearance - As a Plane is almost all copper, any Via or Through Hole Pad introduced that belongs to a different Net will certainly be shorted to it. To prevent this, an Anti-Pad or a cut out must be made to allow clearance for the hole to go through without touching any part of the Plane.
作者: changxk0375 时间: 2007-10-18 16:42
提示: 作者被禁止或删除 内容自动屏蔽作者: tianhao 时间: 2007-10-18 17:27
一步到位！！！作者: superlish 时间: 2007-10-18 21:13
顶！没啥好说的！作者: 309007 时间: 2007-10-23 08:16
顶l作者: coco 时间: 2007-11-12 10:56 标题: 不错 俺也顶一下,因为焊盘描述的太形象啦!作者: droden 时间: 2007-11-16 13:09
好帖！！太形象生动了，我一直都在琢磨这个问题作者: killerljj 时间: 2007-11-16 16:09
good！0 g4 x! S9 h4 B7 l5 X
以上两位老兄能否提供下资料来源以供兄弟们参考？: \ N, t3 G) @
谢谢！！！！) P- H `5 x( T( r* N+ F- i/ G, U( j
5 I; e5 i v( G) f/ N# t[ 本帖最后由 killerljj 于 2007-11-21 20:55 编辑 ]作者: killerljj 时间: 2007-11-21 20:49
偶也跟一贴！ 8 L0 T6 G3 L3 _6 s3 N. Y I以下内容来自《high speed digital system design》。 9 ]% a5 x. @! V( W/ w* b$ K0 D& M9 w 8 \! _. a+ n$ K; xA via is a small hole drilled through a PCB that is used to make connections between various & p7 u2 V q5 r2 Zlayers of the PCB or to connect components to traces. It consists of the barrel, the pad, and 0 _4 f* X# U* ~5 h9 o2 p7 m3 u Pthe antipad. The barrel is a conductive material that fills the hole to allow an electrical9 Z' p- k5 y/ p+ F4 ]# g& N
connection between layers, the pad is used to connect the barrel to the component or trace, 2 d- u1 R* R+ ^" H6 J% k1 W; _and the antipad is a clearance hole between the pad and the metal on a layer to which no 1 ~, ^& G" Q2 c/ R# ?1 Wconnection is required. The most common type of via is called a through-hole via because it 5 Z( j8 l- A/ a9 lis made by drilling a hole through the board, filling it with solder, and making connections on6 r1 o; N& c7 @" d5 o( K
appropriate layers via the pad. Other, less common types of vias, used primarily in multichip $ d. }( L! L4 _, Kmodules (MCMs) and advanced PCBs, are blind, buried, and micro-vias. Figure 5.1 depicts) F1 Y; x1 ?+ i, U$ `* K
a typical through-hole via and its equivalent circuit. Notice that the pads used to connect the9 }% u1 B5 F$ m5 i$ A
traces on layers 1 and 2 make contact with the barrel and that there is no connection on0 z1 U4 n- H; L! i# Y
layer 3. Blind and buried vias have a slightly different construction. Since through-hole vias2 B2 a5 P: y+ Z: ]: j
are by far the most common used in industry, they are the focus of this discussion.! Y! ~9 M7 n3 g& J1 M8 |- b
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Notice that the via model is simply a pi network. The capacitors represent the via pad9 R$ T. F* U6 i5 N' @
capacitance on layers 1 and 2. The series inductance represents the barrel. Since the via 4 F) h1 u2 E) R# i9 k5 pstructures are so small, they can be modeled as lumped elements. This assumption, of1 i4 ]# E8 p3 e( m1 z: a/ |! s3 c) C, O
course, will break down when the delay of the via is larger than one-tenth of the edge rate. - D" y0 ^ g1 O$ _8 \$ Z! UThe main effect that via capacitance has on a signal is that it will slow down the signal edge* n. b! r; Q4 z+ _& U; Y
rate, especially after several transitions. The amount that the signal edge rate will be slowed- E5 j% f5 q" W
can be estimated by examining the degradation of a signal transmitted through a capacitive z# e* \* E# L0 s& \3 V2 Kload, as shown later in this chapter in equation (5.21). Furthermore, if several consecutive 2 N; W$ ~& S( g, u M) G1 ?vias are placed in close proximity to one another, it will lower the effective characteristic * q( g! O% L# [* Zimpedance, as explained in Section 5.3.3. The approximate value of the pad capacitance is 0 \7 ~! l; k9 y z: W1 w) E[Johnson and Graham, 1993]
俺也顶一下,因为焊盘描述的太形象啦!
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