) G, i- v+ M7 R7 S0 n: P4 i-----[Print the board config pathname(s)]------------------------------------ - S* v" j1 {, |1 X# I K2 | 1 Z. S) m6 g8 }; c2 z) M, t8 cC:\Users\ADMINI~1\AppData\Local\.ti\4084209646\) y8 D/ s0 O9 L2 m* [, A% w1 U
0\0\BrdDat\testBoard.dat ( C) V# m7 M; A6 ^8 C y+ P$ c& l$ Z% A( i
-----[Print the reset-command software log-file]-----------------------------, R0 U$ T6 @- Z, d3 ~. n
/ t( O/ h; N2 U" ~This utility has selected a 100- or 510-class product. & F9 E" [( @. B \5 W' lThis utility will load the adapter 'jioserdesusb.dll'.+ {# k" ~: F; [6 h5 g2 W8 s! Z
The library build date was 'Oct 3 2012'. , e) E; G* d3 W% ~. h: B \The library build time was '21:58:41'. - @3 y1 C J" f$ eThe library package version is '5.0.872.0'.) V. D; [- x, m- k
The library component version is '35.34.40.0'.$ F' ~3 ]& `; S6 l7 r# z1 l( V5 l
The controller does not use a programmable FPGA.5 b; K" ?" Q* O1 e! `; t+ U
The controller has a version number of '4' (0x00000004). + @& F5 b2 l8 d6 K* kThe controller has an insertion length of '0' (0x00000000).9 {7 W% t3 \* |. }; p' a7 G
This utility will attempt to reset the controller.% Q4 y$ n7 q2 f, Z4 W) S
This utility has successfully reset the controller. 0 ^1 s. }' n* y( x7 ^4 A/ U- {( ~0 G% ?: r1 b1 B/ O
-----[Print the reset-command hardware log-file]-----------------------------6 Y% m" s: X) D
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The scan-path will be reset by toggling the JTAG TRST signal.% s. N7 S! N" F4 o
The controller is the FTDI FT2232 with USB inteRFace." S' D2 S% z1 O7 E9 {4 _9 H
The link from controller to target is direct (without cable). 1 F6 y; p% n+ _" K M* _+ JThe software is configured for FTDI FT2232 features. 5 m9 ?2 Z( f! s# i! hThe controller cannot monitor the value on the EMU[0] pin. 2 d4 z- w$ n) c1 @+ }/ B8 }2 }The controller cannot monitor the value on the EMU[1] pin. x3 c8 _6 B' [& r0 |% ?The controller cannot control the timing on output pins.3 V. d& l+ a/ f! ?$ O" m
The controller cannot control the timing on input pins. 6 z6 i) v1 \) d; p6 YThe scan-path link-delay has been set to exactly '0' (0x0000).9 L r F: f T* Q5 U6 K) G0 B$ D3 e
# J7 O+ _% L6 X: N-----[The log-file for the JTAG TCLK output generated from the PLL]---------- + y! I) y% `0 i, U; u" [$ _) S3 q! K |) o; Q- U' d3 j/ B0 ?: g" N
There is no hardware for programming the JTAG TCLK frequency.1 y1 c- ~$ @% d' d( ?, c1 z
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-----[Measure the source and frequency of the final JTAG TCLKR input]--------6 u' |8 T8 p0 c2 B# O0 F
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There is no hardware for measuring the JTAG TCLK frequency.$ B7 c) `, ~5 j2 a) M
3 K. x" c8 R$ O9 u# T0 u& \. s-----[Perform the standard path-length test on the JTAG IR and DR]-----------4 a. N$ g! L4 M1 k: z
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This path-length test uses blocks of 512 32-bit words. 9 o3 {/ `4 C. \, Z1 d 1 p$ E" n- @1 A0 m6 LThe test for the JTAG IR instruction path-length faiLED. 3 c1 ]8 A( Y/ |! H, A1 [5 o' RThe many-ones then many-zeros tested length was 6 bits. & A7 C/ S& }+ l2 }5 MThe many-zeros then many-ones tested length was -16352 bits.# n- |$ @) S) b, K, e7 K