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标题: 基于FPGA的单稳态脉冲展宽电路的设计问题！ [打印本页]

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作者: marshal403006    时间: 2008-6-1 23:30
标题: 基于FPGA的单稳态脉冲展宽电路的设计问题！
请各位高手看看本人的程序，编译通过了，仿真却没有结果。我想实现的功能是单稳态脉冲展宽（通过外端口控制展宽宽度）。程序如下：
( F! i/ b9 K- d. h( M计数器（控制展宽电路的宽度）部分：
1 I; {' ?, W# Z' E! N$ y6 C4 slibrary IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
3 [% j3 C; I+ e/ _- h" s  d9 Yuse IEEE.STD_LOGIC_UNSIGNED.ALL;
. i6 t7 Z4 V/ J3 Wentity counter is
0 {8 F# Q; {& [' h( U3 \: |  port(reset,en,clk: in std_logic;
% \0 g# g9 S+ Z4 C3 A% Y( S4 C* K/ x       N1,N2,N3,N4: in std_logic;
; Q  D& x( D7 N6 ~* d0 D6 L! B" ^7 i       feed_out: out std_logic);
  end counter;
: c% T( j; V( i& O/ X  uarchitecture Behavioral of counter is
: `. e' C4 k5 |" [3 tsignal temp: integer range 0 to 15:=0;
  w) n' }) W& D% i* Wsignal k:integer:=0;
begin
  u; \) S6 R! R. f+ J( w  cprocess(N1,N2,N3,N4,k,clk) is
: I, \1 `/ d2 Rbegin
   if(N1='1') then temp<=temp+1;
  elsif(N2='1') then temp<=temp+2;
4 B: R4 J% {' x8 ?  elsif(N3='1') then temp<=temp+4;
  elsif(N4='1') then temp<=temp+8;
$ G) s* s- U1 I  else null;
  end if;
" ?. I3 V* d- Q1 Y  if (clk'event and clk='1') then
    if (reset='1') then
       k<=0;
  x% C* G. ~: G! k7 A3 Q2 H) ~5 }     feed_out<='0';
     elsif (en='1') then   
1 M5 m! I  R& M5 O2 Z9 u    if (k=temp-1) then
( V; ?# z/ A' \6 c# t2 y         feed_out<='1';
         k<=temp-1;
     else k<=k+1;
    end if;
    end if;
4 e# Z7 F& j, ~. Nend if;
end process;
( r4 }  q3 W9 ^, l& f5 vend Behavioral;
D触发器（脉冲前沿产生电路，又是展宽脉冲宽度形成电路）：
6 M4 T/ A0 ]# B5 Blibrary IEEE;
3 P) C3 E- X% s( h6 euse IEEE.STD_LOGIC_1164.ALL;
7 d$ |7 F: @) \7 l2 cuse IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity D_trigger is
" I! {3 R: F- u2 |. z- y; ~8 ?  port(D,clear: in std_logic;
       clk: in std_logic;
4 d7 J# \5 d: P" ~3 g1 k, y   Q: out std_logic);
) Z+ A9 m' P6 iend D_trigger;
% ^3 R( s$ ~# _architecture Behavioral of D_trigger is
begin
2 b7 z+ y7 H$ s8 D4 J$ t6 @process(D,clear,clk) is
begin
5 Z  f* f  [2 J$ x  if (clear='1') then
    Q<='0';     
) _" c! B& p. b9 C0 `8 |4 ?  elsif (clk'event and clk='1') then
    Q<=D;
  end if;
1 M6 Z  m7 I) g& `9 \3 [end process;  
end Behavioral;
; R- B) X% X1 q9 _! M8 [* [8 G% G外部综合部分：
. G! P3 p, G  X( e) y3 Wlibrary IEEE;
use IEEE.STD_LOGIC_1164.ALL;
/ }+ ?" x2 \" p) [use IEEE.STD_LOGIC_ARITH.ALL;
; j( n7 D0 M5 x3 l, g, iuse IEEE.STD_LOGIC_UNSIGNED.ALL;
2 W: h+ ?5 f+ I/ [( x, Y5 a; |entity pulse_expand is
  port(pulse_in,D_in: in std_logic;
6 `) `( {! `) _8 x$ U       clk_in: in std_logic;
) A/ r+ Y$ Z* l8 `/ k& B+ c   n1,n2,n3,n4: in std_logic;
   pulsewidth_out: out std_logic);
end pulse_expand;
3 r: f: l8 K" }% |- E3 }architecture Behavioral of pulse_expand is
  {# `6 }2 I, i- p1 tsignal a1,a2,a3: std_logic;
component counter is
- E) w7 v) U, p! ~8 N) m4 G0 M* K   port(reset,en,clk: in std_logic;
      N1,N2,N3,N4: in std_logic;
        feed_out: out std_logic);
  end component counter;
  component  D_trigger is
     port(D,clear: in std_logic;
          clk: in std_logic;
2 P8 w% Q7 N- b+ E9 K/ a/ S      Q: out std_logic);
0 b+ s; y2 G! o/ z* ~: m  end component D_trigger;
. b" o. M. N" m* gbegin
P1: D_trigger port map (D=>D_in,clear=>a1,clk=>pulse_in,Q=>a2);
, q. L- z* w# S3 \+ G- sa3<= not a2;
+ ]* O* H& L, L4 S5 V& NP2: counter port map ( reset=>a3,en=>a2,clk=>clk_in,feed_out=>a1,
! q# k* i- [- M# P    N1=>n1,N2=>n2,N3=>n3,N4=>n4);
pulsewidth_out<=a2;
end Behavioral;
  N, ^! I3 n7 j
[ 本帖最后由 marshal403006 于 2008-6-2 09:38 编辑 ]

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