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标题: PCB Designer’s si guide [打印本页]
作者: snowwolfe    时间: 2008-5-26 11:07
标题: PCB Designer’s si guide
PCB Designer's SI GUIDETable of Content 0 c! z2 B% e- U
Basics of SI___________________________________________________________________5
$ {, r. U) Y( z/ [4 g# f1.1 When Speed is important? _____________________________________________5
$ [% {# K+ d2 z; _1 k# ]1.1.1 Acceptable Voltage and timing values ________________________________5 * |1 V  B7 ?8 [
1.2 Signal Integrity ______________________________________________________5   `. v  w5 X; j$ x) K1 S/ ^
1.2.1 Waveform Voltage Accuracy _______________________________________5
) w6 J9 z3 _- A0 Z; D2 j( j  J1.2.2 Timing_________________________________________________________5 * ]8 ?8 ?. _3 K- J2 S; D; c
1.3 Speed of currently used logic families ____________________________________5 3 \0 X' A8 j8 J3 b. ?
1.3.1 Transition Electrical Length (TEL) __________________________________6
; V- D5 A( w! Z1.3.2 Critical length ___________________________________________________6 0 D; r  B* A  ]
1.3.3 What is Transmission Line? ________________________________________6
; E" @# Q# Q. {1 s6 ]( u! ?1.3.4 What is moving in a Transmission line?_______________________________6 3 v! }4 Z, J: |; A6 L' w# I
1.3.5 Power Plane Definition____________________________________________6
3 J+ j7 V' A3 D/ P4 C9 d3 m1.3.6 The concept of Ground ____________________________________________7 3 S* g. f0 r2 ~: _8 i% L2 {' X
1.4 STRIPLINE circuit with Electromagnetic field _____________________________7
. p# y* I; f( J0 k, C1.5 RLC Transmission Line Model _________________________________________8 . X5 o& n0 B: c# v5 u) F% a
1.5.1 What is Impedance? ______________________________________________8 - \# z) }4 N/ I, U4 Q9 q8 _# Z
1.5.2 A Practical impedance equation for microstrip _________________________8 6 p6 O$ Z! x: z3 a
1.5.3 What is relative dielectric constant Er? _______________________________9 ( k/ Q, W" G: S0 X7 n

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2 Interconnections for High Speed Digital Circuits _______________________________10
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2.1.1 Summary______________________________________________________10
  I1 n  R0 I8 O! F$ c: n) c2 B2.2 Examples of dynamic interfacing problems _______________________________10
: Z; I0 I+ R% b' L  \2.3 IC Technology and Signal Integrity _____________________________________12 % \5 n* \) y6 w9 _/ Y; _% M' a) t
2.4 Speed and distance __________________________________________________14
/ J5 V8 @( m& H/ _2.5 Digital signals: Static interfacing _______________________________________15
9 b) g! }1 w2 W( W6 |3 K7 U2.6 Digital signals: Dynamic interfacing ____________________________________16 0 l- f1 g0 d4 J1 O
2.7 Review questions ___________________________________________________18
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3 Interconnection Models____________________________________________________20
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3.1 Summary__________________________________________________________20
& A4 _7 `% _1 X+ R! _# F3.2 Reference model for interconnection analysis _____________________________20
8 U- C8 ~7 w3 @  p3.3 Receiver model_____________________________________________________21 7 b9 x" C0 F  y. U+ u, T4 T: q
3.4 RC interconnection model ____________________________________________23 8 {) E5 h& [, X5 w9 [9 X6 x) r
3.5 Parameters of the interconnection ______________________________________25 - w& W6 A  z6 A& [  @: k7 ?% F# `5 R
3.6 Refined models _____________________________________________________26 " v. `, h9 Y/ |; I4 z2 c; R
3.7 Review question ____________________________________________________28 8 }! a1 x- ^5 q( _4 ]3 a1 {" j

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4 Transmission Line Models _________________________________________________31
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4.1 Summary__________________________________________________________31 ) ?% O  o" n7 Q( q
4.2 Transmission line models _____________________________________________31
- L7 b6 a+ L$ a. ~% N! L4.3 Loss-less transmission lines ___________________________________________32
. H1 H; q9 @$ H9 K4 \1 Y+ U' h4.4 Critical Length _____________________________________________________34   ~. [# l( N/ A8 Q( A8 t# p
4.5 Reference transmission line model______________________________________35
: z0 H; o2 T0 O4.6 Line driving _______________________________________________________36 6 g4 z4 F' b, |+ q" p8 [  Z& @1 ?
4.7 Propagation and reflected waves _______________________________________37 4 B, N. J9 E2 Q4 a3 f  O
4.8 A sample system____________________________________________________39
- b( D! X) P, U2 b% {/ I4.9 Review questions ___________________________________________________42 " W6 u0 I- Y& Z
PCB Designer’s SI Guide Page 2 Venkata

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5 Analysis techniques _______________________________________________________45
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5.1 Summary__________________________________________________________45
. V9 D! M& s9 c5.2 Transmission time and skew___________________________________________45
2 }( T: U- S% ~: E4 k5.3 Effects of termination resistance _______________________________________46 6 b+ \) @7 S% v7 S6 m
5.4 Lattice diagram _____________________________________________________48
8 r3 ^9 S' o7 k5 m5 \  E( P5.5 Examples of Real Lines ______________________________________________49 ' |8 e6 s& F+ Y9 V" n+ R! y
5.6 Simulation code ____________________________________________________51 - J7 i$ M( |- B
5.7 Examples of results__________________________________________________54 1 n. r% C- e$ p# p- m3 A% g
5.8 Review questions ___________________________________________________55
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6 Design guide for interconnection ____________________________________________57

$ ?! t  H# f" D% C; {6.1 Summary__________________________________________________________57 ; X& G" {/ K" w( F4 v" x$ W0 H" ~
6.2 Incident wave switching ______________________________________________57 1 z! Y; t1 n; ^8 T/ }
6.3 Effects of capacitive loading __________________________________________58
* [5 j" H( b9 [4 ^) |. E6.4 Termination circuits _________________________________________________59 $ Q' z! x! u) C( e
6.4.1 Passive termination______________________________________________60
8 R9 t# J5 L3 g2 R9 m6.4.2 Low power termination___________________________________________61 ! g4 g; I% x6 o+ o7 U
6.4.3 Active low power termination circuit. _______________________________61
6 v" U; D/ E+ t# o& h6.5 Driving point-to-point lines ___________________________________________62
2 q3 D( x# _2 j3 _* K, i$ Q: \6.6 Driving bused lines __________________________________________________64 . t1 J2 P# [1 d% J& M3 v1 w, N
6.7 Design guidelines ___________________________________________________67 - t; N/ Z/ p; _0 y: [# m. M
6.8 Review questions ___________________________________________________67

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作者: snowwolfe    时间: 2008-5-26 11:09
Signal Integrity in Digital Circuits ___________________________________________70
5 O% }6 a7 N! y4 R7.1 Crosstalk __________________________________________________________70 . R9 Y9 ~0 ^3 L( ^- Z1 a
7.1.1 Summary______________________________________________________70
8 `2 f$ p) P' }8 y: X7 q4 P7.2 Examples of signal integrity problems ___________________________________70
6 k$ c- l! d0 n9 y7.3 Simplified Model for Crosstalk Analysis _________________________________71 ( d2 H3 u7 }# f- z7 ~0 ]$ l
7.4 Forward and backward crosstalk _______________________________________74 : T+ u1 J' W4 Q, t! D9 g
7.5 Examples__________________________________________________________76 : _* V( [0 m3 }# H
7.6 Near-end and Far-end crosstalk ________________________________________80 0 M+ D7 S' c0 U4 s9 z3 E/ G* f
7.7 Review questions ___________________________________________________81
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8 Design Guide to Handle Crosstalk ___________________________________________85

4 i+ E" f! b& h6 X$ s- o$ L* j8.1 Summary__________________________________________________________85 6 Y7 }6 y' y8 Y5 I7 h5 w$ Z/ O
8.2 Effects of Crosstalk __________________________________________________85
5 [5 [6 N' J" Y$ L5 w7 V8.3 Passive countermeasures _____________________________________________86 / d( A% R$ \, L7 }/ z. l
8.4 Active Control of Crosstalk ___________________________________________92
/ p6 Z" X  k8 D$ q9 g! e# N8.5 Review questions ___________________________________________________94
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9 Ground Bounce and Switching Noise_________________________________________97

, \/ G# |& h  {+ @9.1 Summary__________________________________________________________97
! D3 F( y7 T0 y9.2 The totem pole Current Spike__________________________________________97
$ E$ P  t8 C0 W; h; ?- Z9 _+ [$ K9.3 Current flow in the output capacitance __________________________________100
& Z7 W3 r: v2 w  n% j3 u' U$ ?/ B9.4 Total Ground Bounce _______________________________________________100
8 v. b" G$ U( h. T$ ?9.5 Review questions __________________________________________________105
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10 Design Guide for Ground & Power Distribution _____________________________107
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10.1 Summary_________________________________________________________107
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PCB Designer’s SI Guide Page 3 Venkata
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10.2 Decoupling Capacitors ______________________________________________107 3 T% f( q% b( o' w
10.3 Placement of bypass Capacitors _______________________________________113
' h, J" L" ~1 Z0 w4 m4 _% F10.4 Ground and power distribution________________________________________114
5 V* H% q8 e4 c, U10.5 Clock distribution __________________________________________________115 3 @: j; G8 Y; X; r4 t8 M/ e
10.6 Review Questions __________________________________________________118
2 O/ e- b! c5 _! S+ c11 Laboratory Experience _________________________________________________120 ( }; {, `) E$ w. @3 r  U
11.1 Summary_________________________________________________________120 . {3 x' ~3 ]. i& p. ^6 N) e
11.2 Aim of the experience_______________________________________________120 / G; K! A. y5 H, e
11.3 Generator Parameters _______________________________________________122 % S& g/ \( @: P! N) K+ {5 Y( w
11.4 Cable Parameters __________________________________________________123
# i" w1 I9 z: J* Y8 `& `11.5 Mismatch at driver and at termination __________________________________124
3 {+ t2 F- P$ |11.6 Capacitive Load ___________________________________________________125
( [" F4 G; P" R1 a7 u: q2 w$ {11.7 7. Time-domain reflectometer ________________________________________127 ) P) U# e7 z& n2 d0 M# v9 r" e
11.8 Driving the line with logic devices _____________________________________128 / |* P9 n$ e) c  b" Z) k3 ^
12 SI Analysis Strategy____________________________________________________133 # W; D9 v6 ~1 R# @
12.1.1 A modern high-speed design methodology must involve the at least the following: ____________________________________________________________133 ) E. Y3 X+ o! M+ I
12.2 POSSIBLE HIGH-SPEED DESIGN APPROACHES ______________________133 : S  D8 m* C& K! c/ @7 e
12.2.1 There are two fundamental types of conditions that need to be considered for solution space analysis:__________________________________________________134
+ Q: k+ D6 E8 L9 Y8 a" M- [12.3 SOLUTION SPACE ANALYSIS _____________________________________135
- @" X# P9 S; z) s% d% z  h12.3.1" [9 n  B3 ?+ x2 ~8 i
STEP 1 — DEFINING THE INITIAL TOPOLOGY __________________135
$ R! ]( c6 D* M12.3.2 STEP 2 — DEFINE MANUFACTURING TOLERANCES AND THEIR MIN/MAX VALUES ___________________________________________________135 . ^) s! r0 e( `' Q1 `
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STEP 3 — DEFINE THE STARTING POINT FOR DESIGN VARIANCES 136
* v" h) k0 p/ Z" {3 w4 y& Q12.3.46 D9 q8 j: Y2 f8 Q% z  V+ b
STEP 4 — SET UP AND RUN A NUMBER OF SIMULATION CASES _136
" [, T8 N6 b1 w+ v  p% I: m+ I* b12.3.5 STEP 5 — EXAMINE THE SIMULATION RESULTS, IDENTIFY WHICH CASES FAILED AND WHY ____________________________________________136 + [; E) b. X" d2 R' m/ ]
12.3.6 STEP 6 — ADAPT THE TOPOLOGY AND DESIGN RULES AS APPROPRIATE _______________________________________________________137
* Z/ [+ [8 K  A0 \) }* w2 B* x12.3.7 STEP 7 — REPEAT STEPS 4-6 UNTIL THE TOPOLOGY CONVERGES ON A SET OF VALUES THAT PASS FOR ALL CASES ANALYZED __________137 7 C1 Q2 K7 m# P+ n1 a; c4 b3 r
12.3.87 i4 I# y& k$ R! {0 J+ t" Y. o
STEP 8 — DERIVE DESIGN RULES FOR THE TARGET CAD SYSTEM 137 ' F& S6 M- |8 W+ k/ P1 q
12.3.9 STEP 9 — DRIVE THE CAD RULES INTO THE CAD DATABASE, AND USE THEM TO DRIVE THE PLACEMENT/ROUTING PROCESSES ___________138
" H% C) X5 f3 \5 I! f2 \% Y, t* @12.3.10 STEP 10 — POST LAYOUT SI ANALYSIS ______________________139 0 u) g- C( \) I
12.4 CONCLUSION____________________________________________________139
2 r& [/ u/ L: d, p: {  Y13 Glossary _____________________________________________________________141 . C4 j/ @( Q9 B& P( a8 w
PCB Designer’s SI Guide Page 4Venkata
作者: sshunhua1981    时间: 2008-5-26 16:33
了解了解
作者: andy.wei    时间: 2011-7-8 11:30
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