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标题: PCB Designer’s si guide [打印本页]
作者: snowwolfe    时间: 2008-5-26 11:07
标题: PCB Designer’s si guide
PCB Designer's SI GUIDETable of Content ( _" D  L3 u" B7 Z2 x( D
Basics of SI___________________________________________________________________5 ( q- r- x! f; J0 c' F* t
1.1 When Speed is important? _____________________________________________5
, ~% u; t7 [# }1 k1.1.1 Acceptable Voltage and timing values ________________________________5 / u0 _$ R" j* d' n% ~
1.2 Signal Integrity ______________________________________________________5 5 A! k9 ?* }& d$ i( C
1.2.1 Waveform Voltage Accuracy _______________________________________5
; o1 ^; M- ~" U/ V8 _4 v1.2.2 Timing_________________________________________________________5 : K7 M0 L* ?  R, U
1.3 Speed of currently used logic families ____________________________________5 5 g) J, t6 i2 \' ~
1.3.1 Transition Electrical Length (TEL) __________________________________6 6 x4 F" m4 w; h6 T! m0 R
1.3.2 Critical length ___________________________________________________6 1 Y; H% d; q8 [5 s0 o* w3 Z* i5 U! U
1.3.3 What is Transmission Line? ________________________________________6 % n- v* D' {0 g# ]/ h3 `0 [
1.3.4 What is moving in a Transmission line?_______________________________6
4 l& F7 n$ s# Z) ~7 U5 E9 b# p- m1.3.5 Power Plane Definition____________________________________________6
4 c% @' n& D8 h0 N9 s1.3.6 The concept of Ground ____________________________________________7 / {: V& V8 }1 A' ?5 E8 s0 z
1.4 STRIPLINE circuit with Electromagnetic field _____________________________7
! n% @. s/ z  T  ]2 k/ _( |3 k1.5 RLC Transmission Line Model _________________________________________8 # |5 G" T5 A5 Y4 E+ d) i. y
1.5.1 What is Impedance? ______________________________________________8
6 W& R9 s* u. {& F! B& J6 D/ b  n1.5.2 A Practical impedance equation for microstrip _________________________8
% k* i" q6 k4 S1.5.3 What is relative dielectric constant Er? _______________________________9 * b7 ^0 G# y6 O0 a, {, f& s2 `. b  j

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2 Interconnections for High Speed Digital Circuits _______________________________10

. \: Z7 t, @. \& y2.1.1 Summary______________________________________________________10
, H' N2 h. X  i$ S' I: ^2.2 Examples of dynamic interfacing problems _______________________________10 ; c5 h7 U# v  e6 M) {7 w
2.3 IC Technology and Signal Integrity _____________________________________12 ( j7 X- G2 P' Y# n9 z  n- w/ q
2.4 Speed and distance __________________________________________________14 * s# E1 V: c( B, o+ U* r
2.5 Digital signals: Static interfacing _______________________________________15
8 i0 I; C0 q3 U; ?; S& m. M' U5 _2.6 Digital signals: Dynamic interfacing ____________________________________16
0 L6 ^0 r0 t% e; c8 i* w3 S# A: q2.7 Review questions ___________________________________________________18 8 ^" N8 b/ U3 w6 b: X9 `
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3 Interconnection Models____________________________________________________20

2 ^! T# ^  J+ f8 T6 F3 V  L, S9 v3.1 Summary__________________________________________________________20 5 x+ G% V7 Q5 b% I
3.2 Reference model for interconnection analysis _____________________________20 5 M9 O) j8 j+ P: e9 A. L
3.3 Receiver model_____________________________________________________21
* k# N6 h: T! _: S  m4 r! P1 c- q3.4 RC interconnection model ____________________________________________23 3 p( Z3 O' ?$ k: o9 S6 I9 c% s9 |6 a9 F
3.5 Parameters of the interconnection ______________________________________25
4 ?. k& A( O4 |% w, X3.6 Refined models _____________________________________________________26 # `# P  G5 B9 c
3.7 Review question ____________________________________________________28 ; \( j: H" b$ |9 o: |7 J
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4 Transmission Line Models _________________________________________________31

9 U3 Y$ i3 e% v1 e+ s; Y- j4.1 Summary__________________________________________________________31 & D; [0 ~& f; C
4.2 Transmission line models _____________________________________________31 8 n. X, D2 m, j; H- d. V( P- O
4.3 Loss-less transmission lines ___________________________________________32
( Y! R$ _2 }, E, ?& g4.4 Critical Length _____________________________________________________34
! e7 z8 }* V' ~$ Z; J# P* y4.5 Reference transmission line model______________________________________35 3 {8 s7 G0 r) n
4.6 Line driving _______________________________________________________36 0 Y% ]" s- L1 R& P3 Q$ [* S( f
4.7 Propagation and reflected waves _______________________________________37
4 @5 O. p( t; E8 y4.8 A sample system____________________________________________________39 8 c  j6 D" v) k3 a, V' c, ~
4.9 Review questions ___________________________________________________42
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PCB Designer’s SI Guide Page 2 Venkata

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5 Analysis techniques _______________________________________________________45
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5.1 Summary__________________________________________________________45 & u, ~# ?2 E, U6 a* M0 F
5.2 Transmission time and skew___________________________________________45 # @" p! y1 \6 E
5.3 Effects of termination resistance _______________________________________46
: p) L; |- D# x  _" t% m5.4 Lattice diagram _____________________________________________________48 / ]# f) q( Y$ e/ w# I; e
5.5 Examples of Real Lines ______________________________________________49 7 B1 t! ~0 F- @. @8 n
5.6 Simulation code ____________________________________________________51
, b+ t0 p1 `& H5.7 Examples of results__________________________________________________54
: I5 j( v! H( V% r9 [) Y: @5.8 Review questions ___________________________________________________55
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6 Design guide for interconnection ____________________________________________57
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6.1 Summary__________________________________________________________57 5 \) {. x5 r) G* p: A9 V0 x* c
6.2 Incident wave switching ______________________________________________57
) L" E/ S: f' [- \6.3 Effects of capacitive loading __________________________________________58
$ F9 y: ~  [. p5 D6.4 Termination circuits _________________________________________________59 5 B& H9 {5 F5 w6 |* {6 @3 B/ y1 v
6.4.1 Passive termination______________________________________________60 6 c" V2 o8 Z; @6 q+ [0 F1 f. I$ Y
6.4.2 Low power termination___________________________________________61
  i* p- o7 g; `! R3 S6.4.3 Active low power termination circuit. _______________________________61
  F) R$ g5 Y+ {6.5 Driving point-to-point lines ___________________________________________62
. V! ^8 _. e' C. R* }; e6.6 Driving bused lines __________________________________________________64
( n9 }, _) z/ E) b) z6.7 Design guidelines ___________________________________________________67 # C# x- S. q2 ^
6.8 Review questions ___________________________________________________67

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作者: snowwolfe    时间: 2008-5-26 11:09
Signal Integrity in Digital Circuits ___________________________________________70
* t- T+ Q1 f, F) y9 _' ?- m7.1 Crosstalk __________________________________________________________70 & b( v" X/ w! |% n
7.1.1 Summary______________________________________________________70 $ `( T4 @( B$ m2 Q
7.2 Examples of signal integrity problems ___________________________________70
- F5 q6 ~# W: F% i2 K' A5 d& @7.3 Simplified Model for Crosstalk Analysis _________________________________71
+ Y) D6 V/ z: X' [( J6 Y7.4 Forward and backward crosstalk _______________________________________74
1 B  @( D9 F/ {4 f/ Z5 g7.5 Examples__________________________________________________________76 $ R* L" P+ N! Y7 a: y. c
7.6 Near-end and Far-end crosstalk ________________________________________80 $ x0 c3 F# v; g/ ?! v0 p
7.7 Review questions ___________________________________________________81
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8 Design Guide to Handle Crosstalk ___________________________________________85
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8.1 Summary__________________________________________________________85 % B- k# b, A) U; \2 m6 q. }- ]
8.2 Effects of Crosstalk __________________________________________________85
+ H6 w8 o. h( I/ M& c" u% ?: h8 o. k8.3 Passive countermeasures _____________________________________________86 6 s. Y' S' i* Z
8.4 Active Control of Crosstalk ___________________________________________92
- \+ G4 D4 f5 Q8.5 Review questions ___________________________________________________94 3 S6 q) _8 _7 P4 |; S7 f+ X
9 Ground Bounce and Switching Noise_________________________________________97
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9.1 Summary__________________________________________________________97 ; `5 F4 t& Y4 t% a# m
9.2 The totem pole Current Spike__________________________________________97 + h3 |- b# \  Z
9.3 Current flow in the output capacitance __________________________________100
; g+ k6 K7 o8 p) l$ K7 t( i9.4 Total Ground Bounce _______________________________________________100
* Y& V- Z# b, Q7 U7 _' u9 _( I( a7 w0 ?$ _9.5 Review questions __________________________________________________105
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10 Design Guide for Ground & Power Distribution _____________________________107
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10.1 Summary_________________________________________________________107
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PCB Designer’s SI Guide Page 3 Venkata
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10.2 Decoupling Capacitors ______________________________________________107
+ }& X( Y& ^0 J% j* W10.3 Placement of bypass Capacitors _______________________________________113 5 @3 o( v) W1 J  ~
10.4 Ground and power distribution________________________________________114
, A$ @0 ~' D# Q7 A10.5 Clock distribution __________________________________________________115
3 g3 v  W% h( ]- l10.6 Review Questions __________________________________________________118 0 `% n2 c5 N; q
11 Laboratory Experience _________________________________________________120
# s- ^9 S) B, g11.1 Summary_________________________________________________________120 . ^5 q$ E8 u( U% }7 q
11.2 Aim of the experience_______________________________________________120
; f+ W8 N# E9 k% n& R- k1 X11.3 Generator Parameters _______________________________________________122
# A6 u" \% F" X* ?% j$ a& Q11.4 Cable Parameters __________________________________________________123
* M' ^8 [& n, _# z$ O4 W  @11.5 Mismatch at driver and at termination __________________________________124
' O6 Q' v9 [( f- P$ a4 e% Z% D11.6 Capacitive Load ___________________________________________________125 0 `. s. r0 D$ F, i  v
11.7 7. Time-domain reflectometer ________________________________________127 ) _6 z$ T. x! O
11.8 Driving the line with logic devices _____________________________________128
% p9 h* q, F$ ^5 G12 SI Analysis Strategy____________________________________________________133
' Z( y6 b9 C6 g/ X0 z+ a12.1.1 A modern high-speed design methodology must involve the at least the following: ____________________________________________________________133
; N4 O' Q0 ?: q; _  V8 D$ L* T3 [& t12.2 POSSIBLE HIGH-SPEED DESIGN APPROACHES ______________________133
, L/ z6 s( z- j/ r  J; q" r12.2.1 There are two fundamental types of conditions that need to be considered for solution space analysis:__________________________________________________134 # E, f/ b4 D2 Z! [7 j
12.3 SOLUTION SPACE ANALYSIS _____________________________________135
& C9 i% \2 C5 d1 h) `- u/ T12.3.1
. e. A: y1 W& s, {3 N" \# jSTEP 1 — DEFINING THE INITIAL TOPOLOGY __________________135
/ j( H% E9 ]; ^; ^1 q' F% m12.3.2 STEP 2 — DEFINE MANUFACTURING TOLERANCES AND THEIR MIN/MAX VALUES ___________________________________________________135
- P# Q) u& Z/ A8 Y& Z& F5 b12.3.3
1 p* l3 S  j/ Z) a! ESTEP 3 — DEFINE THE STARTING POINT FOR DESIGN VARIANCES 136
: u3 ~/ a4 |! ?12.3.4/ l. M3 m3 u3 E
STEP 4 — SET UP AND RUN A NUMBER OF SIMULATION CASES _136
( _7 m& X3 g4 Z: h6 z12.3.5 STEP 5 — EXAMINE THE SIMULATION RESULTS, IDENTIFY WHICH CASES FAILED AND WHY ____________________________________________136 5 D. X" z5 Z/ [3 W. I
12.3.6 STEP 6 — ADAPT THE TOPOLOGY AND DESIGN RULES AS APPROPRIATE _______________________________________________________137
5 x: p: h' Y/ |# H5 I7 a12.3.7 STEP 7 — REPEAT STEPS 4-6 UNTIL THE TOPOLOGY CONVERGES ON A SET OF VALUES THAT PASS FOR ALL CASES ANALYZED __________137 9 p1 r" _; X& r
12.3.8
( x5 k. l6 }9 Y. V3 Y# v; F, JSTEP 8 — DERIVE DESIGN RULES FOR THE TARGET CAD SYSTEM 137
/ s3 E* F# d( l) J0 P6 d12.3.9 STEP 9 — DRIVE THE CAD RULES INTO THE CAD DATABASE, AND USE THEM TO DRIVE THE PLACEMENT/ROUTING PROCESSES ___________138 * T* q' k5 {2 p! m- [, L
12.3.10 STEP 10 — POST LAYOUT SI ANALYSIS ______________________139 $ y( W; j; ]$ X# {: s& V
12.4 CONCLUSION____________________________________________________139
# M) v8 X; P8 m- Y6 z1 r13 Glossary _____________________________________________________________141
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PCB Designer’s SI Guide Page 4Venkata
作者: sshunhua1981    时间: 2008-5-26 16:33
了解了解
作者: andy.wei    时间: 2011-7-8 11:30
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