9 F% _& r( Y* [8 I: {Hotfix_SPB17.40.012; }3 N. ^* r9 `- A) w% v7 H* E
8 D: R- I8 H2 A# y$ |4 i百度云链接: https://pan.baidu.com/s/1udP4SQr7pERhzD2tHlMuCA 提取码: a6q4 0 L% Y3 S' Z7 p- o6 Y ^ 5 F6 p% n9 Y6 N" f @ ; C& `7 ?/ y5 P% L% \3 @2 M ) y5 C: {2 ~) T1 K. @& \% ~! d' D3 Z: E" j3 p! N* X9 C Fixed CCRs: SPB 17.4 HF012 - Date: 10-30-20203 G0 S \; X" M& A) d
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CCRID Product ProductLevel2 Title, J; {9 m8 @+ ^ I! | S
======================================================================== ' o5 A) m( `$ x& f2324284 ADV_PKG_ROUTER OTHER APR fails to route and does not use the BBVias., l9 Z7 I# m4 p: ^7 K
2346605 ADW ADWSERVER Librarian license incorrectly checked out by data nodes during LiveBOM creation 9 V' e, s* s$ a8 \0 b2317952 ALLEGRO_EDITOR 3D_CANVAS Allegro 3D Canvas does not show STEP models placed on paste mask correctly ! `" |7 U8 o/ S: C- K+ M" ~2192222 ALLEGRO_EDITOR DFM Allegro PCB Editor crashed during check 'Mask' with the setting of 'Via Partially Covered With Mask Opening'+ {# m( R8 G; f2 K, A' a
2197203 ALLEGRO_EDITOR DFM Wrong alert on Soldermask sliver checking- s: L; }7 G1 s0 V3 ?) L& }
2280806 ALLEGRO_EDITOR DFM Importing netlist results in error related to illegal subclass (SPMHNI-234) 0 U0 } u& O6 P+ S7 K v! n2262559 ALLEGRO_EDITOR DRC_CONSTR Copper Features: Minimum Acid traps Angle gives false DRC % ]6 L8 W! ?" b# x+ F" k# F3 p( L2319385 ALLEGRO_EDITOR INTERACTIV Find by Query for Via structures is not working with Symbol field filter 0 f; }3 w! n. I3 S5 \2 Y! o6 V2279179 ALLEGRO_EDITOR PLOTTING File> Plot ignores the printer setup properties and always prints in Portrait format.* i( H \ |( N( E, C
2306419 ALLEGRO_EDITOR PLOTTING File -> Plot -> Properties only accepts 'Portrait' and not 'Landscape' 4 C5 N& N% |/ p" S* S7 Q0 v% t2333930 ALLEGRO_EDITOR PLOTTING The File> Plot always prints PCB in portrait; H, D: r. O; R% d8 B# @
2327088 ALLEGRO_EDITOR SHAPE Design Sync gets a SAV file reported but there is no information about the cause of the problem in netrev.lst+ b# E( k, P2 L0 A
2331947 ALLEGRO_EDITOR SHAPE When adding shape, pressing the 'Shift' key ends the process , R P* |/ k3 F! V& ?2339008 ALLEGRO_EDITOR STREAM_IF Stream import view layers give error- _2 o2 X. p2 c; Q, [3 l! z
2328322 APD DRC_CONSTRAIN Database getting corrupted during artwork creation even after running DBDoctor. 4 p; Z: V# ^# J. G# V3 z2280535 APD REPORTS About the missing fillets report result: Ignore fillets not generated inside via regular pad area# J+ B/ l- A2 O7 ?4 `8 w" O; O5 R
2323629 CAPTURE OTHER Product unusable with DSN file: Operations have significant delays and application stops responding, X0 x6 v5 y4 z+ N" E$ B
2261147 CONSTRAINT_MGR ANALYSIS Setting "Mechanical drill hole to conductor spacing" does not flag DRC ! x9 L5 P, K3 i1 ]2330712 CONSTRAINT_MGR DATABASE Physical Constraints Set value cannot be modified 7 H9 j* V5 ]. o9 Z0 T$ W2333755 CONSTRAINT_MGR SCHEM_FTB CM simplified out-of-sync pop-up form has clipped text6 X1 i9 \% I# ?0 f! `: w/ W& K
2235714 CONSTRAINT_MGR UI_FORMS Using the 'Change all design unit attributes…' pop-up menu option changes only the Min BB Via Gap value ; ^0 {- e. D+ @! ~4 y2288109 CONSTRAINT_MGR UI_FORMS Column sort is not working for match group : R- E6 n% u. t( D. h7 @2306092 CONSTRAINT_MGR UI_FORMS Display Constraints shows empty constraints in Constraint Manager 9 [) g4 j# M1 q/ t1 w2332795 CONSTRAINT_MGR UI_FORMS CMGR Worksheet colums are not sorted as per the columns definitions4 z" |0 z1 p& S1 t" P h
2326995 PCB_LIBRARIAN SYMBOL_EDITOR Graphics and pin number locations are incorrect 1 l7 l" N7 c& |3 N7 e0 v2280766 PSPICE MODELEDITOR Error while converting Verilog-A model * Q# y/ ~5 I3 y2285008 PSPICE MODELEDITOR Model Editor crashes if file name does not match with IBIS model file name2 V& ~: H6 z* w, _
2346048 PULSE ADHOC Importing or File New Block as a designer working on a design that has been shared does not work % D3 b5 u7 `- ~3 h2346643 PULSE ADHOC System Capture crashes when adding a part ( `& N' w! p- M; v+ H2214054 PULSE UNIFIED_SEARC Unified Search does not honor operating system HTTP proxy settings; X% k1 e0 p) x! O4 ]/ v' L5 f
2325635 PULSE UNIFIED_SEARC Errors in Unified Search (vista) using customer database : `+ p7 K# v& w, @* D4 c2326089 PULSE UNIFIED_SEARC Unified search does not show EDM parts and gives error (SPPSUN-1) - X, M* A+ {% A4 a/ J D2 o, p2329750 PULSE VERSION_ON_SA Live BOM data disappearing from migrated DE-HDL design with variants% s9 e2 i3 z/ ^- h" R0 f
2319690 SIP_LAYOUT EDIT_ETCH Allegro SiP Layout XL - Auto-I Breakout Closest End excessive run time: Takes long time to complete: ^" K) U4 W: k/ `$ h2 j; ^
2320336 SIP_LAYOUT EDIT_ETCH Auto-Interactive Pin Swapping /Auto Breakout cannot route in design " O6 E0 C% u5 j" W# ^/ R2333679 SIP_LAYOUT INTERACTIVE Add Offset Via Angle Field) w8 f& ?' p8 T0 q
2344732 SYSTEM_CAPTURE DESIGN_CORRUP Page cannot be loaded because the design database is corrupt* |0 n% m8 n* l3 \! _
2342258 SYSTEM_CAPTURE MISCELLANEOUS System Capture is impacting PCB Editor GUI Readability by Setting QT_SCALE_FACTOR / h2 ^0 N% i: d9 E2337610 SYSTEM_CAPTURE PART_MANAGER System Capture crashes when updating a part with changed PACK_TYPE and Symbol% R- Z, B2 _- b
2341550 SYSTEM_CAPTURE VERSION_ON_SA Projects migrated from HotFix 002 to HotFix 010 have slow performance# d" E) d. @- E/ r8 w
2341591 SYSTEM_CAPTURE WIRING Moving wire segments still leaves odd pieces of wires3 q q) v- T$ i/ @
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