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标题: [ 已解决]在哪能看到各个补丁包的修改内容呢？有谁整理过了 [打印本页]
作者: leilei4908    时间: 2019-11-5 13:54
标题: [ 已解决]在哪能看到各个补丁包的修改内容呢？有谁整理过了
本帖最后由 leilei4908 于 2019-11-8 16:15 编辑
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, m9 k* h( i9 e. e- T看到多数人发的补丁包都附有Fixed CCRs，也就是修改内容的介绍, P/ Z1 k) G1 R- C& X6 L
这个具体在哪能看得到呢？
- G) W8 m% B$ Y1 t) c7 Q在本地有对应的文件吗？
1 U8 E. W- B! U$ X+ F7 Y想知道17.2的029到060一共修改了哪些内容! c1 `3 g- J2 G) c4 |3 j
一个个去找，太麻烦了，还不一定找的全
1 S! V; Q# g, C# i
+ a: t! U0 E0 X2 y3 P找到了，在
! r7 P& m- E& Y$ C%cdsroot%\README_CCR.txt' R6 {) L+ y( M9 o7 h" \; C0 ^& N
作者: lilacbear    时间: 2019-11-5 14:06
Readme for SPB Release version 17.2! K1 U) w* r, K% h; r9 d% F3 i
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Copyright (c) 2019 Cadence Design Systems, Inc.$ J- g& T0 o; ~2 P% n: V
All rights reserved worldwide.
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Fixed CCRs: SPB 17.2 HF060
6 K' D7 h% w7 {0 q4 M0 |; `% _( A10-11-2019# A7 P* d: `) Y' {
========================================================================================================================================================
! }5 U, W5 y9 [( X9 S: ]  `% ?* J& wCCRID   Product            ProductLevel2 Title( F$ {9 T3 ^3 T( M
========================================================================================================================================================' F+ f0 z& P. F9 N4 H
2137594 ADW                DBADMIN       EDM is not allowing to modify step model
' c8 W% }$ f9 G2115805 ADW                DBEDITOR      'BOTH' in ALT_SYMBOLS prevents correct generation of part_table.ptf2 \- I/ s( b& ~" H" }
2135452 ADW                DBEDITOR      DBEditor poor performance in high latency networks
: n: w, I3 G& Y" q: Y) _2142315 ADW                LIBDISTRIBUTI EDM Library Server stops often and adwserver.out file is extremely large, more than 1GB
* s8 [* ?1 d% Y2155396 ALLEGRO_EDITOR     DATABASE      Netlist error when importing from Capture CIS+ H2 w; |& G+ ^' n
2118231 ALLEGRO_EDITOR     DRC_CONSTR    Crash during DRC: DBDoctor exits with error 'Illegal database pointer encountered'
, C1 T8 }; S- E" B0 z2150923 ALLEGRO_EDITOR     DRC_CONSTR    Via at SMD fit DRC not detected with rounded rectangle pads
" m5 I0 N! u5 l: [6 S+ k' b2140441 ALLEGRO_EDITOR     EDIT_ETCH     Drill hole to line DRC while sliding but 'Allow DRC' is not selected in the Options tab
0 o! M7 H% x1 O; F/ @/ x2141329 ALLEGRO_EDITOR     INTERFACE_DES Error message (SPMHSY-49) displayed on running 'Tools' - 'Database Check'4 Y# t& z7 d+ q6 g4 `
2126562 ALLEGRO_EDITOR     MODULES       Create Module File / Place replicate assigns incorrect netname
7 m) w7 O% S2 {2150410 ALLEGRO_EDITOR     SCHEM_FTB     netrev.lst is created in the wrong folder$ y1 p2 g0 o; r2 {" F+ u' X$ d
2136158 ALLEGRO_EDITOR     STEP          Update STEP Mapping Data Only should be seperate Menu/Command.
4 E0 ~$ d, e& G* I! u4 Y2137801 APD                VIA_STRUCTURE High speed via structure instance not adding properly
% w3 @" l6 o& `9 e' {2145072 CONCEPT_HDL        CORE          Error on choosing 'Enable Hierarchical Variant'+ q/ R$ `/ i; @3 I' X
2124843 PCB_LIBRARIAN      CORE          Prompt displayed for license choice marked to be used as default
9 q5 r, j# P" {6 y2 \2141656 PCB_LIBRARIAN      CORE          Part Developer pop-up option 'Edit' for symbols displays an error message
) m0 N6 R: B( E2125794 PCB_LIBRARIAN      SYMBOL_EDITOR Part Developer new Symbol Editor: cannot move inverted pins that contain circle and dot
8 |$ f$ J% M4 z: T( R2161864 PULSE              R2PLM         Second publish with CPM-derived item number and cadName set to $NUMBER causes 'an item is not unique' error5 [; L4 r1 \8 X5 f4 O
1997911 SIP_LAYOUT         ORBITIO_IF    Support keepout translation between OrbitIO and Allegro layout/physical editors
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9 ^1 q# M# @" DFixed CCRs: SPB 17.2 HF059" a4 Z5 r8 ?: t$ D4 S
09-13-2019. ~! z+ i3 A3 q5 R* N5 R1 o& \
========================================================================================================================================================
& E$ p* y; G  l5 E) GCCRID   Product            ProductLevel2 Title- u3 S& \$ A6 @3 D* a
========================================================================================================================================================  Q  p- m  v7 r) W7 h& @
2112454 ADW                DBEDITOR      Icons in DBEditor do not start applications after renaming a model/ b" `- I* N* ^8 k' y; l
2120548 ADW                LIBIMPORT     Missing alternate footprints from vault area after library import.$ V0 J% G' M6 ]" |
2143314 ADW                PART_BROWSER  Component Browser does not start after installing HotFix 057 of release 17.2-2016! S/ t$ p- [( C! e: B5 q& X
2122302 ALLEGRO_EDITOR     ARTWORK       Coverlay details not being output to Artwork data as per the visibility
4 }! ~5 |/ B+ w2 ~  p' g6 ]2135521 ALLEGRO_EDITOR     ARTWORK       Artwork dimensions do not match Allegro PCB Editor
3 z$ S+ p/ Z7 f' K  a; C2054584 ALLEGRO_EDITOR     DATABASE      Through hole mechanical pin in zone area without Soldermask Top still shows a pad on Soldermask Top( X; v2 E1 |: [- v$ ~: X
2111444 ALLEGRO_EDITOR     DATABASE      No soldermask for mechanical holes within zone) X, t* i2 P/ ]% O2 j$ ?
2115596 ALLEGRO_EDITOR     DATABASE      Unused Pad Suppression removes pin connected to shape using Net_short property; i5 Q. d: n( V/ _9 \9 {
2135436 ALLEGRO_EDITOR     EDIT_ETCH     Allegro PCB Editor crashes when routing with VOID_SAME_NET property on cline
: k! Z# ^7 ]# R, C( o8 b: x' ~; E1825020 ALLEGRO_EDITOR     INTERACTIV    GUI ( Quickplace ) not adjusted to current resolution$ @7 F( V, j. A- a
1949705 ALLEGRO_EDITOR     INTERACTIV    Quickplace GUI not adjusted to lower resolution
8 W* V7 |+ L) s, Z2023090 ALLEGRO_EDITOR     INTERACTIV    Dialog boxes do not fit vertically on the screen0 u  \1 u* W3 p% t$ Y8 S% ]* I: L
2109940 ALLEGRO_EDITOR     INTERACTIV    Quickplace pop-up window does not fit vertically on the screen* r& E6 ?" }& `/ N
2136823 ALLEGRO_EDITOR     INTERACTIV    Cannot resize or move dialog box to access buttons
! O! p* p3 e/ Q: C2116748 ALLEGRO_EDITOR     IN_DESIGN_ANA Impedance vision data not available for cline segments for some nets
% _( E: x4 n/ s2138977 ALLEGRO_EDITOR     IN_DESIGN_ANA Impedance check results are incorrect and Crosstalk analysis stops running after updating to HotFix 057' B* M" j) ~* z" d
2132628 ALLEGRO_EDITOR     NC            Improve the User Preference description for BACKDRILL_OVERSIZE_OPTION
4 A. g: F( y  c. Q& S. p0 ~0 w2152244 ALLEGRO_EDITOR     SCHEM_FTB     Netrev.lst is written in the package folder
: ~6 P5 o! |/ d, K& `* S" i: c* T2152493 ALLEGRO_EDITOR     SCHEM_FTB     netrev.lst is not created in the correct folder - error displayed for neltist import
0 p3 X# r5 E! h7 \) Z2104559 ALLEGRO_EDITOR     SHAPE         PCB Editor crashes while performing shape operation 'andnot'/ i& }# x. |4 [- D* V4 x
2108207 ALLEGRO_EDITOR     SHAPE         No Void Overlap option is not working in AMB( U0 b: O3 M/ ^2 c, |( `  N
2125571 ALLEGRO_EDITOR     SHAPE         Allegro PCB Editor crashes for a RAVEL rule9 L/ f' J3 z4 e( ~0 e# V0 p
2140707 ALLEGRO_EDITOR     SHAPE         Allegro PCB Editor crashes on creating dynamic shape6 j" q. Y2 \* f
2078434 ALLEGRO_PROD_TOOLB CORE          Shield Router - cline end caps treated differently than cline-segment end caps
5 ?0 \! y2 M8 ~9 z2101020 ALLEGRO_PROD_TOOLB CORE          Productivity Toolbox Z-DRC with multiple net classes: script selects only the last two classes in a group/ a! l) [% @& t" M
2029279 CAPTURE            SCHEMATICS    Slow response when selecting parts in schematic# C3 s. a2 F* |  \
2039931 CAPTURE            SCHEMATICS    Slowness in OrCAD Capture when ITC is enabled
$ `4 I7 ?9 w( D* f2106942 CAPTURE            SCHEMATICS    Inter-tool communication needs to be disabled to resolve the lag issues in Capture, {6 h, N& [' L4 V8 B
2131683 RF_PCB             ROUTING       PCB Editor stops responding on using RF - Add Connect* D) {* j) U5 ?" a! S
2126505 SCM                OTHER         Thevenin Termination dialog displays resistors incorrectly
' T$ i3 ]) Z9 m2 X8 C! @( ^8 j* K' o2102383 SIP_LAYOUT         WLP           Advanced WLP Non-standard fillets not working properly: fillets not added
; E( z: t; u+ Q/ O4 R
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Fixed CCRs: SPB 17.2 HF0586 V: k) V4 B% W/ E
08-16-20199 N) ]4 u5 \# o$ r/ D/ H5 b
========================================================================================================================================================' @6 B2 E% ?( U+ I9 Q
CCRID   Product            ProductLevel2 Title
4 {; U. r( {' B3 H========================================================================================================================================================6 A+ v* @# J+ s9 m2 j
2113265 ADW                LIBDISTRIBUTI Various DB operations take too long, rebooting server seems to fix the problem9 H+ ?' L1 l& e- B! @9 l* e
2122941 ADW                LIBDISTRIBUTI Lib_dist execution taking too long to run, Capture CIS DBC File appears to be taking the most of the time. F1 B% a' Y7 ]8 q1 b
2127319 ADW                LIBDISTRIBUTI Library distribution fails at cisexport function with error (ORCIS-6250)
  ?% F2 t4 J' ^+ g1 i& C2107578 ALLEGRO_EDITOR     3D_CANVAS     Allegro 3D Canvas shows split layer. v& x/ `+ M/ n. s) e4 f
2099538 ALLEGRO_EDITOR     EDIT_ETCH     'Glossing - Via Eliminate' shifts traces to another layer
& f- H" ?3 G# I5 V% h, x4 S$ ~2031883 ALLEGRO_EDITOR     INTERACTIV    Sub-Drawing: clipboard origin point is not set correctly
- g! g. o1 L# M, i; N' S0 a; Y/ q2100433 ALLEGRO_EDITOR     INTERACTIV    Pad Edit displays error for extents (SPMHA1-69) if pads are at 90 or 270 degrees) u+ y3 M$ \6 o# Q, s
2127239 ALLEGRO_EDITOR     INTERACTIV    Exporting a query result changes the working directory
0 ~0 G1 N1 s$ o, c2117160 ALLEGRO_EDITOR     MCAD_COLLAB   Error encountered when importing IDX file into MCAD tool in HotFix 056
) Z1 y3 w( `1 m7 T+ x2117427 ALLEGRO_EDITOR     MCAD_COLLAB   IDX files exported from HotFix 056 cannot be read in MCAD tool (the same files from HotFix 055 can be read)# S4 W- M2 K4 J
2117839 ALLEGRO_EDITOR     MCAD_COLLAB   IDX file created from release 17.2-2016 with Hotfix 056 is not readable in MCAD tools
! h0 B8 C& o( b( s2118019 ALLEGRO_EDITOR     MCAD_COLLAB   Export IDX is not working in Hotfix 056 but working in HotFix 055
- F: J$ l8 z7 w) h, l4 r$ D2106425 ALLEGRO_EDITOR     NC            Disable undersize regular pad and oversize soldermask pad for start layers/ M5 J+ p+ C4 K4 b6 I$ _  K1 d
2126766 ALLEGRO_EDITOR     REPORTS       Cannot generate reports and export ODB on board
3 K0 T2 J* a3 \* o, B+ o0 t# R2107849 ALLEGRO_EDITOR     SHAPE         PCB Editor stops responding on updating shapes
( B& V% E4 M+ j2 H3 c- k1 v1778109 ALLEGRO_EDITOR     UI_GENERAL    Constraint Manager exits on doing 'Undo' in PCB Editor
+ E2 {- j: H4 W2064092 ALLEGRO_EDITOR     UI_GENERAL    Allegro Constraint Manager closes on clicking Undo in the layout editor
+ v$ Z8 }4 G3 B. M3 d6 {; G) C2093341 ALLEGRO_EDITOR     UI_GENERAL    Show Element incorrectly displays in report window on a single line if an HTML Report is open when show element runs8 u$ E% x# @8 |2 v  h4 N
2110909 CONSTRAINT_MGR     UI_FORMS      Cannot type dot (.) in DFA Table of Package to Package Spacing in DFA of Constraint Manager.; A: {7 k# {1 T" b9 y2 p& d7 \
2096846 INSTALLATION       ADW           Component Browser does not open if adwservice.exe is not added to the Windows firewall exception list
  w  q: k" e1 s4 v& K! m, {8 c2128118 INSTALLATION       ADW           Unable to connect to Component Browser.; U' t. w9 m/ v3 I/ ?& U& |
2116749 PCB_LIBRARIAN      OTHER         Cannot open Part Developer with a Venture PCB license (PA3810)
3 p2 E/ d: M2 P2115302 SIP_LAYOUT         IMPORT_DATA   Performance issues with die text in and pin use codes, function utcle pwrgnd
! a  Z4 l+ s2 q& g; ^( T/ D2103784 SIP_LAYOUT         MULTI_USER    Symphony Server rejects the move void commands on a specific shape instance8 A3 l; I% }- i$ b! J: U1 L
2096239 SIP_LAYOUT         STREAM_IF     Database fails to create stream out file
# k: ]# o) a! t- h; Y, N7 u% M2117572 SYSTEM_CAPTURE     EXPORT_PCB    System Capture crashes with multiple Export to PCB Layout7 }: O! V0 G' ]3 X% J4 N9 S
& B4 ?- k4 ?  E/ S

# I0 z- f- T9 V8 t8 K+ [2 }: E' CFixed CCRs: SPB 17.2 HF057
* `/ f+ S! I5 C* W4 l07-19-2019
" p9 r: v0 Y5 E4 j- S========================================================================================================================================================9 V9 p6 H$ w, M. Z: y1 ~
CCRID   Product            ProductLevel2 Title
6 B# ]5 j3 i! i% j. Z========================================================================================================================================================
$ q1 q4 q; U1 g$ A- A/ R3 m! ^1920958 ADW                ADWSERVER     Designer server will not start due to corrupt inr file' W! R! ^# j/ @3 r, D5 ]( e3 k$ W
2039243 ADW                LIBIMPORT     libimport ignores footprints generated by Library Creator due to changes of attribute names
! I1 u( Z" v1 j4 M# U8 [3 g, u2113226 ADW                PART_MANAGER  System Capture stops responding while importing DE-HDL sheets$ [9 B" E2 m3 D5 c. f9 l
2035942 ALLEGRO_EDITOR     ARTWORK       'Create Artwork' is slow when all films are selected
1 ^* j* ?. h9 `! h, B& X) l2096958 ALLEGRO_EDITOR     DFA           Cannot launch Constraint Manager after assigning CSet and closing
9 [1 y& z$ Z& Q2087181 ALLEGRO_EDITOR     DFM           DFM reporting false positive hole to hole with stacked microvias6 X! `+ j4 S- ~# ?
2099400 ALLEGRO_EDITOR     DFM           Placing a mechanical pin on a cutout causes PCB Editor to crash
6 i! t/ _( ~; l* ~2067214 ALLEGRO_EDITOR     DRC_CONSTR    Constraint Manager crashes for design linked board
; m- J) K/ ~  `! R& {8 ~' Q2097464 ALLEGRO_EDITOR     MULTI_USER    Design data lost if network connection drops in Symphony5 `6 ^# `" P+ o6 w
2108211 ALLEGRO_EDITOR     MULTI_USER    Error: Update #1 (Perm shape) was rejected by server
" F  e. F( r- K/ n2117154 ALLEGRO_EDITOR     MULTI_USER    Error message needed for Symphony  for client disconnections
: \8 L) F( b# x$ H! q2100149 ALLEGRO_EDITOR     REPORTS       Error message (SPMHDX-9) for too many field names while generating dangling via report5 p' Q( {5 o% L# O: n4 ?/ y
2101932 ALLEGRO_EDITOR     REPORTS       PCB Editor internal error (SPMHDX-9) for too many field names when running BOM report3 }8 w* T8 ^5 B* o0 J
2111449 ALLEGRO_EDITOR     SYMBOL        'Layout - Renumber' results in error* B8 q& F( b' I1 a$ c
2102177 ALLEGRO_EDITOR     UI_GENERAL    axlDMBrowsePath returns incomplete information! C/ L3 |5 [" m. j: E5 e  }  A; j0 {
2105342 ALLEGRO_EDITOR     UI_GENERAL    PCB Editor stops responding for 'Show Element - Find - Symbol Type' on a particular board8 h# ~2 a7 p. F. p; z
2085443 APD                ARTWORK       Gerber lacks precision required to void some vias for a design in artwork output: need warning2 W8 O( S# O$ _# t- }3 X, D1 o% ^
2080118 CONCEPT_HDL        CORE          Getting error after adding offpage to bus and assigning a new value to $sig_name0 O% F/ W1 S. q) p& e) s- S+ M! l+ k& p
2099438 CONCEPT_HDL        CORE          Genview allows dragging group of signals in split symbol distribution form2 x* X1 {6 K1 G( r
2108289 CONCEPT_HDL        CORE          Variant data is not in sync with the packaged data9 `7 Q- r4 U9 l) [
2087217 CONCEPT_HDL        OTHER         Variant back annotation will not work if there is a double quote (") in the description field of a part0 H& S( ^% T. h$ m0 t& y& [
2107430 CONCEPT_HDL        PAGE_MGMT     Insert page is not working
! @$ S5 R7 W& @4 P5 b2063875 CONSTRAINT_MGR     OTHER         PCB Editor crashes on deleting match group without closing Constraint Manager6 R9 ^* r2 U2 K- O9 ^2 j
2103729 F2B                DESIGNVARI    Cannot enable hierarchical variants for block
- A9 d' e+ V: P# ^$ T- e! m2099076 F2B                PACKAGERXL    Package fails for 'Save Hierarchy', but succeeds for 'Save'
. ^1 O* N8 F" P5 e: Z! A) _2081132 INSTALLATION       SPB           Part Information Manager cannot connect to EDM server after upgrading to HotFix 053
% U( v, K) ^( R$ D( }5 s; G, `# D1599964 PSPICE             ENVIRONMENT   Version Info displays 'OrCAD Version Viewer MFC Application has stopped working'
& G: c$ _4 r; ~7 Y% b2045497 PSPICE             SIMULATOR     'Illegal Parameter Value in File' error when loading Monte Carlo parameter file
! Y# R8 x6 J9 N" y; o4 \. [3 Z2025997 SCM                TABLE         Copy-Paste Broken in Physical View
; c2 {7 E: t7 A3 J5 }4 }3 h2102652 SCM                TABLE         Unable to copy the Associated Components Ref Des values to Excel0 o2 ~; i; W7 U* M
2054225 SIG_INTEGRITY      SIGNOISE      Cross Section Editor bug after changing the impedance value in Analyze - Preferences
) v8 c! z. P1 b: w4 ~2100075 SIP_LAYOUT         DIE_ABSTRACT_ Refresh co-design die running slow/ @( @6 k2 G6 J3 ^, v# u' I
2106312 SIP_LAYOUT         DIE_ABSTRACT_ Die abstract I/F to bring into SiP Layout and OrbitIO power/ground and signals not designated as RDL/ D, R  p; X; P) d9 x$ C
2106314 SIP_LAYOUT         INTERACTIVE   Large design causing severe lag in Windows Server machine
2 n* m4 s2 O! C. B/ k; j2 K0 _7 X2101622 SIP_LAYOUT         MULTI_USER    Symphony Server rejects the slide commands when tapered trace option is on0 A9 |9 \; H- x* X; j2 z+ ]
2107897 SIP_LAYOUT         WIREBOND      Design stops responding when running Wire Bond Auto Spread in HotFix 055
/ k: L2 k0 y9 d9 _! x& |2 a2104885 SIP_LAYOUT         WLP           Advanced WLP: Metal Density Scan, scan area in report is incorrect
8 b" q7 ]' K3 Y  d! ?% C9 O5 T% d# a& i3 z1 m
1 V" u4 w) t$ d) S
Fixed CCRs: SPB 17.2 HF056( o6 H! K3 e4 m$ q
06-21-20196 u7 n% ^* K- W4 V0 i
========================================================================================================================================================
2 U$ [9 i" a1 v, [5 L0 x1 Z9 i1 |CCRID   Product            ProductLevel2 Title8 K9 x& t7 f& g
========================================================================================================================================================8 a& L; I5 `: C- N2 M7 `
2086463 ADW                PART_MANAGER  System Capture cannot add components when accessing remote machine via Citrix' Q1 f" J3 g) u( V. z" O: a+ ?
2092868 ADW                PART_MANAGER  Release 17.2-2016, HotFix 054: Empty cache.ptf causing injected properties to not to flow from pstchip
* X' c) ~1 w5 q: p8 C) Y2092872 ADW                PART_MANAGER  Import DE-HDL Sheets stops responding4 g8 g: \% L% p, ]% |5 r
2088975 ALLEGRO_EDITOR     3D_CANVAS     Bending in 3D Canvas causes PCB Editor to crash/ i( P) F8 {* `
2088577 ALLEGRO_EDITOR     COLOR         Export color nets does not write all the nets in param file0 D1 _; o9 X5 l0 e
2028867 ALLEGRO_EDITOR     DFM           False DFF Trace to Thru via pad spacing DRC
2 H4 w0 R1 \9 |# x2037361 ALLEGRO_EDITOR     DFM           Soldermask features drawn with a line do not DRC to pin, via, or shape soldermask features/ ~3 \8 c* z. }
2077913 ALLEGRO_EDITOR     DRC_CONSTR    When running a simple SKILL command, the tool will run for a very long time
$ a: m  D3 z' `9 B- _* T! f% t2079642 ALLEGRO_EDITOR     DXF           Drill symbols are rotated in exported DXF in release 17.2-2016
& I( ]/ x5 D! L! A2083493 ALLEGRO_EDITOR     MANUFACT      Manufacture - Cross section chart is not readable for rigid-flex designs4 W; e& b7 }8 U2 Q! r
2073607 ALLEGRO_EDITOR     MCAD_COLLAB   IDX_IN batch program to allow a batch update of an .idx file
0 f# T4 i9 ^8 h% f0 h2095632 ALLEGRO_EDITOR     MULTI_USER    Design server on Symphony stops responding and cannot be closed or downloaded$ F$ B% h3 o1 Y" C
2098221 ALLEGRO_EDITOR     MULTI_USER    Symphony Server Manager allows connection to databases deleted from the project area
6 S0 ]4 p/ k: [% I) J2087315 ALLEGRO_EDITOR     NC            Backdrill exclusions raised on pins of a component, y3 u: r, ^. L4 L+ c  v2 Z
1947929 ALLEGRO_EDITOR     OTHER         The 'show measure' function crashes when measuring pin to pin distance* D1 y. X  n3 S% g1 Q
2091932 ALLEGRO_EDITOR     OTHER         Unsupported Prototypes command missing for the OrCAD licenses. ^2 x5 y# x6 c+ r9 ], B
2089470 ALLEGRO_EDITOR     REPORTS       Summary report shows the exclamation character (!) in the middle of numbers and words) h* p) c" D/ G+ B# w
2067324 ALLEGRO_EDITOR     SHAPE         Netin crash during third-party Netlist import8 q- V/ L9 c$ Y2 u" c. t  o
2075191 ALLEGRO_EDITOR     SHAPE         Delete islands in the design: update out of date shapes and Database Check0 L- @7 P: x8 p% x- w) @
2090604 ALLEGRO_EDITOR     UI_FORMS      Undo/Redo UI grayed out when invoking Color192
; @, \/ V3 C- z) y' c2043825 ALLEGRO_EDITOR     UI_GENERAL    Custom toolbar settings are not retained upon restart of Allegro PCB Designer( u. b) g7 n+ U: T& `8 Q
2090185 ALLEGRO_EDITOR     UI_GENERAL    UI setting in INI file not retained
3 `5 B  y# m! u/ q- {2090517 ALLEGRO_EDITOR     UI_GENERAL    Shape visibility box is not being enabled with the Enable layer select mode option in the Visibility Pane
) N$ k# ?, L4 x3 v2092436 ALLEGRO_EDITOR     UI_GENERAL    RefDes length of input string for Modify Design Padstack is limited to 20 characters
# V+ f) R( M- s1 d7 Q( q2099070 ALLEGRO_EDITOR     UI_GENERAL    UI setting not working properly, Icons missing after restart.
8 ~. {2 b5 i- u- N& v2088484 APD                DATABASE      Some objects (Vias and Cline) cannot be modified (edit, delete and slide) in the mcm database
  f9 [( q  h7 a6 l8 s- k. T1951623 APD                DEGASSING     Shape Degassing fails with specific Void to Shape boundary value- @) L0 ]- @% j3 t; p
2081363 APD                DEGASSING     Cannot degas for specific shape5 @1 }, m% {8 J" E0 w
2083498 APD                WIREBOND      Cannot wire bond from a diepad to another diepad on the same component
% `( a* h3 V. [7 _4 S) S2086589 CAPTURE            NETLIST_ALLEG The generate the CM enabled files from the command line using pstswp.exe.5 l9 D; [2 `" t2 j
2098248 CAPTURE            NEW_SYM_EDITO Ignore pin is not working for individual pins in Edit pin spreadsheet when edited for all pins
& w1 S' I3 t1 o  x! L1773047 CIS                PART_MANAGER  Pin numbers and names for DNI parts will get disappeared in variant view mode if they are relocated in part editor8 ?9 G) C; n+ z+ |2 P! q; B# c
2003818 CIS                PART_MANAGER  Pin name and number of 'do not stuff' parts are not visible in the View variant mode
1 \* V: Q' L% y2076265 CIS                PART_MANAGER  Variant view pinnr/pinname disappears
6 J, t' [# e! a( |) e2 H# W2076282 CIS                PART_MANAGER  View variant does not show pinnr and pinname! E) L9 `! ^5 Q" N! e6 |6 a
2083394 CIS                PART_MANAGER  No pin names and numbers on variant view for specific parts( {5 D) y! H% a
2090027 CONCEPT_HDL        CORE          Cut and move of split hierarchical symbol to another page results in error due to lock or write permission issues0 K3 i; j$ v+ t2 B
2071355 ORBITIO            ALLEGRO_SIP_I Dummy nets creation in die after performing Merge Updated SiP
9 O6 R; T  R# H2 M5 `! ]2067703 PCB_LIBRARIAN      OTHER         PDV crashes immediately for vector pins if MSB is lower than LSB' s+ B. d; _; @0 r4 o! H
2041348 PCB_LIBRARIAN      SYMBOL_EDITOR Grid setting change cannot be saved in new Symbol Editor: i2 l1 C  F# @
2041365 PCB_LIBRARIAN      SYMBOL_EDITOR Improve copy drawing objects in new Symbol Editor" s# A. b* E5 n, Y. D
2067931 PCB_LIBRARIAN      SYMBOL_EDITOR New symbol editor grid issue: documentation grid spacing value changes6 l4 q5 [) [# a% n6 u- v
2093849 PCB_LIBRARIAN      SYMBOL_EDITOR Symbol font text and appearance different when placed in Schematics
" d  A1 T$ k& @' l: |# M1919298 PSPICE             FRONTENDPLUGI Capture crashes on archiving project
' h6 [7 j. J: a! C/ L1953001 PSPICE             FRONTENDPLUGI Archive project causes Capture crash.- ]) ^$ z; d, S+ [% g7 }
2035572 PSPICE             FRONTENDPLUGI Crash on archiving project
: B" H  N. {! `1 m; ?/ h0 p2041286 PSPICE             FRONTENDPLUGI Archive project crashes when using lib as global.% e* k. `% O# H' z+ C
2081796 PSPICE             FRONTENDPLUGI 'Archive Project' crashes Capture in release 17.2-2016, HotFix 053
( K* m, v" a" D7 h2 G% F; A+ a" l2106017 PSPICE             FRONTENDPLUGI Capture crashes when archiving PSpice-enabled project. ^- c5 O. g; c- I
2051450 PSPICE             PWL           PWL Sources application: pop-ups and messages when browsing and placing source
( m: x1 F; A1 F& C% p2090021 PSPICE             PWL           Modeling Application - Sources - PWL Sources Dialog is not properly displayed, U  Y& I/ E% l* a& \1 i5 j
2094548 PSPICE             SIMULATOR     Model undefined error on TL494. v5 [" g: q2 ]* |8 x
2058018 SCM                PACKAGER      Reference designator mismatch in 'exportsch' schematics and board file0 V8 m: H" k7 a* {$ F
1955868 SIP_LAYOUT         STREAM_IF     APD/SiP Layout: Export rounded features as circumscribed and not inscribed polygon in GDS* Z- F& N! y: }
2081914 SIP_LAYOUT         STREAM_IF     Release 17.2-2016: GDSII stream out drops shapes
% h; U: n0 Z* F2013647 SYSTEM_CAPTURE     CANVAS_EDIT   Replacing a vertically oriented RES with a horizontal CAP breaks the wire connections2 C! Z& J# i+ J
, v* L6 p% d. W- z6 i- c0 I
  p8 c2 Q0 Z& G
Fixed CCRs: SPB 17.2 HF0551 @1 R' D6 e' `
05-24-2019# h$ f+ M8 |$ T; s/ Y
========================================================================================================================================================, o) H9 |# @! }) C  Z
CCRID   Product            ProductLevel2 Title0 Y" O+ {" p7 _/ J
========================================================================================================================================================: ?- m  Z$ n# ?) ^' I) s7 _; G* `- ]
2078057 ADW                PART_BROWSER  Symbol Graphics preview is not available in the Designer Server
6 b- n7 U8 F* N+ W2 g' v% }2092863 ADW                PART_BROWSER  Component Browser is not displaying the symbol & footprint preview9 p9 d3 N5 D7 ]( c2 h7 y8 i
2076339 ALLEGRO_EDITOR     3D_CANVAS     Floating parts on bending a board in 3D Canvas with HotFix 053' ]5 e! R' ?2 f2 K# j* L  G
2051075 ALLEGRO_EDITOR     ARTWORK       Incorrect Gerber import in Allegro PCB Editor# v7 h! A3 U9 z3 I% A0 ?5 N
2073407 ALLEGRO_EDITOR     DATABASE      axlDeleteByLayer deletes fixed shapes
! k, i7 n9 s, `$ r2079117 ALLEGRO_EDITOR     DATABASE      Release 17.2-2016: Board file saved in HotFix 049 cannot be opened in HotFix 0149 d, C) a6 D2 x6 q
2079204 ALLEGRO_EDITOR     DFM           Enabling option to update analysis mode and run DesignTrue DFM wizard causes PCB Editor to exit
% ~* v) B6 n& `  g2082394 ALLEGRO_EDITOR     DRAFTING      Angular dimension not owned by the same parent symbol in the layout are not deleted on moving object
; k- l2 ~& F- Q* L: u7 l2067916 ALLEGRO_EDITOR     INTERACTIV    Place replicate module bounding box does not move with circuit after module is updated
! W" W8 g! G9 A3 N/ ?. X9 v2068449 ALLEGRO_EDITOR     MANUFACT      Stackup chart and table shift slightly from original location on re-generation in Allegro PCB Editor release 17.2-2016
7 {' r8 n) D- l  |! L% u( r2065820 ALLEGRO_EDITOR     MCAD_COLLAB   Selected objects deleted from the design on clicking Cancel in IDX Flow Manager Import
+ t3 S: K( Z  {: H6 _5 p9 Y2080164 ALLEGRO_EDITOR     MCAD_COLLAB   IDX outputs two sets of masks
$ P8 A' a8 Z( l* t2081955 ALLEGRO_EDITOR     NC            Artwork file error for via size
. @! f3 x$ @! A+ [6 U$ S2045061 ALLEGRO_EDITOR     PLACEMENT     Setting PSMPATH: axlSetVariableFile() does not update Place Manual but User Preference Editor does
& G" i# r; S# I/ z2049949 ALLEGRO_EDITOR     PLACEMENT     Get import errors and cannot place some parts if user-defined option is turned on for netlist import
2 v" a- A8 w" x7 X/ r/ m2 ^8 e& R2069289 ALLEGRO_EDITOR     PLACEMENT     Cannot place part because attribute definitions are incompatible for the 'DESCRIPTION' attribute (SPMHDB-154): ~: p: |' V' ^3 b
2056573 ALLEGRO_EDITOR     SCHEM_FTB     Import Logic takes a long time when checks are turned on3 m: S  z2 Y' _7 ]$ W
2076452 ALLEGRO_EDITOR     SHAPE         Shape Degassing crashes if 'Inside Shape' is selected
$ ~& e) o  N$ y: R+ J2076873 ALLEGRO_EDITOR     SHAPE         Symbol Editor stops responding on editing shape with a .dra file
( Z6 P- y. s3 V8 j7 B5 _1788703 ALLEGRO_EDITOR     SKILL         axlPadSuppressSet does not work when 'none' switch is used- r4 \7 @1 x4 R" G
1955127 ALLEGRO_EDITOR     SKILL         axlPadSuppressSet( 'off 'none ) returns a warning message and does not work per the documentation
! [% ]4 ^6 ~$ V  Y& W2031711 ALLEGRO_EDITOR     SKILL         Syntax error related to allegro.ini shown if allegro.ilinit loads INI on startup
% f: K0 ]# \, O; x2062527 ALLEGRO_EDITOR     SRM           RF elements are shown in Symbol Revision Manager# D+ r5 Z4 x: F# d( f1 j
2074249 ALLEGRO_EDITOR     TESTPREP      Testprep re-sequence causes PCB Editor to crash if 'Labels with Net Name' is selected8 w& T9 o- G: T. i4 q& n
2070534 ALLEGRO_PROD_TOOLB CORE          Productivity Toolbox bar code generator is creating corrupted shapes in the database, T* i# H+ j( j2 v0 }: I  m  j
2046278 ALTM_TRANSLATOR    CAPTURE       Third-party import fails
2 f7 z( W5 v7 r2052399 ALTM_TRANSLATOR    CAPTURE       Third-party CAD translation stopped with error message
( G) x6 n7 H! B- W2005087 ALTM_TRANSLATOR    DE_HDL        Cannot translate third-party to Allegro Design Entry HDL
4 w& I: d" B% B/ f, I7 d0 d1922222 ALTM_TRANSLATOR    PCB_EDITOR    Third-party translation converts to board with unconnected nets
/ r  O4 [. I) A- o# v+ h4 [- A* W1987263 ALTM_TRANSLATOR    PCB_EDITOR    Third-party board file: copper not imported( v9 n7 z2 m& r! S* X0 @: m' [
2017988 ALTM_TRANSLATOR    PCB_EDITOR    Third-party to Allegro PCB Editor import issues with routes, constraints, size, and accuracy* U" Q0 A) F0 u& s$ [1 F% i; K3 s
2021300 ALTM_TRANSLATOR    PCB_EDITOR    Third-party translator does not show any results on PCB Editor canvas
2 t/ Q$ c/ [1 y7 C2 \) ]1890675 APD                DIE_EDITOR    Mirror Geometry is Mirroring the symbol from TOP to BOTTOM Layer in SIP file$ n/ g! \8 n0 `
2064219 APD                DIE_EDITOR    Applying mirror geometry results in mirroring: moved from TOP to BOTTOM layer
8 Y3 ]2 R2 P- P! R8 u0 X$ ?2086574 APD                OTHER         Duplicate layer text shown on the vias" P# n5 @0 @; O& {  u1 \2 B
1948169 CIS                CONFIGURATION Auto Symbol Refresh Checking not working for shared folders5 {  t3 v3 U" H
2025385 CONCEPT_HDL        CORE          Hierarchy Viewer expands/collapses randomly after clicking the '+' or '-' symbols
5 t- h- Z9 Q/ @1 h) I8 z  _& `) D2050010 CONCEPT_HDL        CORE          Copyproject does not properly copy the variant files
+ w( g% N3 v- J9 D; B' B2063457 CONCEPT_HDL        CORE          DE-HDL: very slow rendering on some systems
- C8 R( `) I" h: H7 @% U2076312 CONCEPT_HDL        CORE          Getting 'Variant out of sync' warning when creating BOM for a design with no variants
" e3 |& E, y7 s+ Q; L2083650 CONCEPT_HDL        CORE          Lower-level signals are appended with _1, _2, and so on
. ]7 A; ~# D% }  r  I2083651 CONCEPT_HDL        CORE          The physical net names still do not sync with the assigned signal name- j9 {" _$ U6 y9 }, B- W- z
2056736 CONCEPT_HDL        GLOBALCHANGE  Global Property Delete does not operate on the entire design unless the top-level page 1 is open
. l3 }% r# l6 L9 u  @9 F6 `1955357 SIG_EXPLORER       OTHER         Signal explorer invocation with OrCAD PCB Expert Suite license$ t1 F9 c) t/ @5 \- {0 c* b
2079071 SIP_LAYOUT         SYMB_EDIT_APP Response very slow after Show IC Details on a very large co-design die9 T) O  s4 G/ }4 |
2081884 SYSTEM_CAPTURE     CANVAS_EDIT   Symbols take a long time to move, and results in DRCs and broken connections& C/ B; v$ L- a' G
1942542 SYSTEM_CAPTURE     IMPORT_PCB    System Capture - TDO backannotation overwrites net names with stale data in lower-level blocks
4 a5 a/ Q4 z% p4 x4 |$ K2071303 SYSTEM_CAPTURE     MISCELLANEOUS cds.lib file is picked up from wrong location
0 B/ A' }+ Y; R& S, C/ A# i, G2058979 SYSTEM_CAPTURE     OPEN_CLOSE_PR System Capture prevents a project from opening by putting a single quote at the end of a line in CPM file
6 v2 z7 N% t3 U; s2088210 SYSTEM_CAPTURE     OPEN_CLOSE_PR The 'enable pspice' entry in CPM file is occasionally corrupted$ j! W6 x3 K4 s4 `6 I" }

# u1 k. H, S0 q
+ i3 m  ]5 e# @  [Fixed CCRs: SPB 17.2 HF054
+ F" q6 E2 F. H* p04-26-20195 _' _9 U- Y" k" }* n7 v
========================================================================================================================================================$ u, P. Q! k: h0 T/ j; K6 h
CCRID   Product            ProductLevel2 Title/ J6 v4 h/ m" u5 O. _
========================================================================================================================================================  X8 C$ e# Z( a) f  {, N
2060269 ADW                DBEDITOR      Unable to create ECAD type mixed-case schematic model attributes
( c' j' P% W1 T0 ^2030086 ADW                LRM           Cache part_table.ptf made by LRM Update cannot be read if it has null value in key property
! U$ z3 T& F* \" \9 ]8 v1975317 ADW                PART_BROWSER  Space at the end of line in CDS.LIB results in zero libraries being shown in new component browser6 X5 R/ ~' {1 [8 ^) M
2076340 ADW                PART_BROWSER  .helix folder needs to be deleted for PTF changes to take effect and to convert a design to cache
% ?9 O& U/ d) u" c$ s4 O( S9 K2025147 ADW                TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name% A- f$ A* `3 E. W. M
2025201 ADW                TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design
% z( F. S3 c4 ]$ X8 X2056694 ADW                TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object8 J2 O0 P+ R5 t
2054243 ALLEGRO_EDITOR     3D_CANVAS     Plating is not shown on stacked vias in 3D canvas" Z# T0 T7 S1 Z
2054327 ALLEGRO_EDITOR     3D_CANVAS     3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation
1 G. Y: _& h8 |2044980 ALLEGRO_EDITOR     ARTWORK       'Import - Artwork': PCB Editor stops responding and no artworks are loaded* [+ B/ z' r: K; v
2060489 ALLEGRO_EDITOR     COLOR         SKILL axlGlobalVisibility() issue in a partition file: VIA/SOLDERMASK_TOP subclass visibility not turned off
0 d9 z/ e! l- A) b: c- k9 h2072695 ALLEGRO_EDITOR     COLOR         Clines of colored nets not colored when 'display_nohighlight_priority' is set" D" p7 S5 U# c+ n" C+ E, ^0 ?+ A
2061203 ALLEGRO_EDITOR     CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone7 \+ B6 x8 x& y+ Y/ i
2010812 ALLEGRO_EDITOR     DATABASE      PCB Editor STEP model offsets should follow origin movements. s9 p! `# D3 i4 H! R8 e/ t- g. n
2011993 ALLEGRO_EDITOR     DATABASE      Change STEP model mapping when Symbol Origin is changed in DRA using Setup > Change Drawing Origin0 B, e/ q- U' N! _5 t
2051596 ALLEGRO_EDITOR     DATABASE      Error for unsupported property in element
! \4 x4 J, w" [& V! ?+ g- N2056497 ALLEGRO_EDITOR     DATABASE      Place manual is slow
2 g3 z) J- l) ^( v. B" j$ p7 S2059489 ALLEGRO_EDITOR     DATABASE      DBDOCTOR in batch mode with argument '-check_only' detects text error- {4 E8 s8 C4 y2 X
2064268 ALLEGRO_EDITOR     DATABASE      PCB Editor crashes when running SKILL code
0 D# P! l6 U6 H) W5 x+ ^2068588 ALLEGRO_EDITOR     DATABASE      Crash on opening release 16.6 design in 17.2-2016
! A9 @6 ?7 I, D# P: B8 [8 a2079131 ALLEGRO_EDITOR     DATABASE      axlChangeNet crashes PCB Editor in fast shape mode with Microsoft Visual C++ Runtime Library Error
7 w% D; _( |; ~; N2034759 ALLEGRO_EDITOR     DFM           Importing DFT constraints on board does not assign csets to design but shows the csets
# z/ W1 _! l( f& L! V: D) o8 n: a2039992 ALLEGRO_EDITOR     DFM           Cset is not set in Pastemask element of DFA when importing XML Constraint File./ i8 ^. }2 Y9 C8 C# w
2046824 ALLEGRO_EDITOR     EXTRACT       Extracta ECL_NETWORK View reports incorrect pin layer.
0 L- D7 |% ^1 t1 i2048912 ALLEGRO_EDITOR     IPC           Running PCB Design Compare - Graphic mode reports ERROR (SPMHA1-273) 'Shape intersects with itself'
( N- ?7 h0 @7 M# Y6 v. F2 r) Z2066597 ALLEGRO_EDITOR     IPC           Graphical compare not completed because of self-intersecting shape locations0 u! ~* k1 k) i
2079719 ALLEGRO_EDITOR     IPC           IPC2581 import fails with error 'Failed to add (LW)POLYLINE'
+ r) X; O5 `! y/ J! i2 ^2066229 ALLEGRO_EDITOR     NC            Tool code missing in backdrill NC file on choosing 'Optimize Drill Head Travel' in NC Drill! {1 i: D9 u4 F0 E! ^/ r+ B
2070379 ALLEGRO_EDITOR     NC            After running backdrill some vias are shorted to other nets7 J: E* ~  @1 ?
2041881 ALLEGRO_EDITOR     PAD_EDITOR    Difference in locations of drill in pad editor and symbol editor- N) d! f" r5 a5 {
2058852 ALLEGRO_EDITOR     PAD_EDITOR    Net associations lost on refreshing vias
/ h# q" P* u* M7 Z. H& x2061580 ALLEGRO_EDITOR     PAD_EDITOR    Lock Layer Span settings specified in padstack editor not reflected in PCB Editor
) d, Y. i/ N1 e5 n) _. z1 A* a, _2048116 ALLEGRO_EDITOR     REPORTS       Extracta command files not visible in Tools-->Reports when there is a space present in the textpath variable  e  T% h! C5 A, z* K% f9 o
2038949 ALLEGRO_EDITOR     SCHEM_FTB     Netrev is slow if there is an input board file with many modified components4 q0 O% i! J9 V4 \
2052758 ALLEGRO_EDITOR     SCHEM_FTB     Connectivity objects are being reported as Added and Deleted in Constraint Differences Report( L  S- a6 D5 Y% A( K+ j1 V$ \* K  }
2066099 ALLEGRO_EDITOR     SCHEM_FTB     Inconsistent net names on export physical after changing net names in DE-HDL" [6 Q! v, Z" i7 c* p
2043882 ALLEGRO_EDITOR     SHAPE         Shapes not updated to 'Minimum aperture for gap width' in Global Dynamic Shape Parameters window% Z- `8 v  f1 N+ o
2048483 ALLEGRO_EDITOR     SHAPE         Shapes not getting updated post backdrill update
4 G6 W0 Z4 o9 ?5 F" ]2052063 ALLEGRO_EDITOR     SHAPE         Cannot import IPC2581 due to 'Shape intersects with itself'( z4 A: M! ~  O' |) V" J/ h0 \
2056478 ALLEGRO_EDITOR     SHAPE         Editing shape by sliding segment causes PCB Editor to fail due to 0-length segment in shape
: s  q- ^5 o: l$ i9 s9 z. b0 Y0 B2058017 ALLEGRO_EDITOR     SHAPE         Shape not voiding correctly when fillets are present
3 \7 j) `& ]/ ~$ J- V! h2066473 ALLEGRO_EDITOR     SHAPE         Teardrops create strange copper shapes
# z8 f* D; g! ~* H- U8 J2079698 ALLEGRO_EDITOR     SHAPE         IPC2581 import fails with error 'Shapes intersects with itself'
( ^9 H2 R! }- x2010569 ALLEGRO_EDITOR     SKILL         Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in HotFix 048.
, L6 ^/ ~3 i0 d( j5 S2055055 ALLEGRO_EDITOR     SKILL         Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash
8 o  G6 Z5 X; C" T- S; z9 i2023755 ALLEGRO_EDITOR     STEP          Export STEP includes enclosure even when it is not selected.
7 z# [6 d2 W- f9 e- B0 L5 m1 b1881233 ALLEGRO_EDITOR     UI_GENERAL    Green/white canvas without grid when creating a board file (File - New), g# {: b) F- v) E
1900525 ALLEGRO_EDITOR     UI_GENERAL    Resizing the update symbols UI causes the options to overlap and jumble up (refresh issue)9 G9 r+ Q( V5 S# S- W
2003861 ALLEGRO_EDITOR     UI_GENERAL    Same y-coordinate returned for different vertical positions when creating board outline in HotFix 048
1 |1 |/ f( Q6 M' ^0 G2033958 ALLEGRO_EDITOR     UI_GENERAL    Incorrect canvas display on creating a design from the Start page and then opening an existing design
' H+ ]. B& D% i2053496 ALLEGRO_EDITOR     UI_GENERAL    Confirmation dialog is behind canvas
( ^2 F0 q$ a3 }9 B2054429 ALLEGRO_EDITOR     UI_GENERAL    Editor stops responding until choosing Done after clicking Zoom by Point twice/ c" K  x7 i5 {* m3 J6 C
2059707 ALLEGRO_EDITOR     UI_GENERAL    'HTTPS' links are not shown as hyperlinks when using allegro_html
/ y2 ^  F3 ?3 ]5 Q2063423 ALLEGRO_EDITOR     UI_GENERAL    Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden
' }- ~0 A/ n7 J8 I) g" X# q5 R/ P2038105 APD                DRC_CONSTRAIN APD crashes on update DRC in release 16.6
2 Z3 t% O- }8 s/ M7 `& V2050674 APD                PARTITION     Cannot remove C-Point from a partitioned design
' a% J" R- V4 R5 z* L' i) [- r2068814 APD                WIREBOND      Bond wires cross on auto-separate; s, g  {, C4 I1 D5 |* ~
1967433 CAPTURE            OTHER         Cannot open DSN or OPJ files by double-clicking if Capture is already open; A' V6 k% K9 T
1967332 CONCEPT_HDL        COMP_BROWSER  Crash in customer environment on clicking on last row border in PIM after filtering$ N7 C' u& f8 [& n$ q1 T
2001759 CONCEPT_HDL        COMP_BROWSER  Using Modify Component crashes Design Entry HDL
4 L1 O9 g- Y6 N; Z+ U! l2020788 CONCEPT_HDL        COMP_BROWSER  Intermittent crash when clicking bottom edge of part selection table in the Modify Component window
% Z( V  N' W1 h+ H! z6 p' m) t2053578 CONCEPT_HDL        CONSTRAINT_MG Values specified for custom properties are not preserved8 @* D  D2 i' g/ `- b4 h5 I0 E
2013002 CONCEPT_HDL        CORE          Ability to regenerate Netgroup names to remove '_1' suffix' |7 i7 I8 _* X4 E6 E; o* g( e
2026637 CONCEPT_HDL        CORE          DE-HDL crashing often when launched from EDM Flow Manager
" f3 q- h2 C1 O" I5 o2041145 CONCEPT_HDL        CORE          Set font size & color of netgroup names and netgroup taps
! R1 D/ b" y' K2 w+ i6 H- a/ N2056743 CONCEPT_HDL        CORE          NetGroups appended with _1_1, some are empty, and inconsistent in DE-HDL CM and Allegro PCB Editor CM+ h+ w9 y0 y, T8 x3 O& i
2065889 CONCEPT_HDL        CORE          DE-HDL Modify command moves location of attached symbol properties
, U7 Q6 t& V: L* z5 n2074410 CONCEPT_HDL        CORE          Full net connectivity not shown in Allegro PCB Editor.  K* H4 a$ m6 V" G. Q$ A7 E! q
2045717 CONCEPT_HDL        RF_LAYOUT_DRI The RF PCB Options is greyed out when doing Import Physical on Linux with enterprise licenses
) r8 j7 ^7 c- P* r- N) X3 _2045274 CONSTRAINT_MGR     CONCEPT_HDL   Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor
" w5 ~, x; J+ G: h# Z7 g  `9 f2050521 CONSTRAINT_MGR     OTHER         Unexpected Xnet removal from schematic when Export to PCB Layout is executed./ P$ ^& N; v+ ~" ?8 E
2066270 PCB_LIBRARIAN      SYMBOL_EDITOR Unable to edit note text containing comma" c+ m* K, u0 }" D" V; P
2069181 PCB_LIBRARIAN      SYMBOL_EDITOR Pinlist window expand/collapse buttons act weird first time when invoked.
& j+ Q: \4 v& T* Q5 ^/ V. D2070007 PCB_LIBRARIAN      SYMBOL_EDITOR Project not found error in Symbol Editor when path contains space character2 N$ w! H8 m: r4 z& ]# X
2072793 PCB_LIBRARIAN      SYMBOL_EDITOR Right-click menu of formatting text objects is not consistent: second and third options are swapped
+ ?' v4 o! l- a% S( ~0 g7 ?2 h2073138 PCB_LIBRARIAN      SYMBOL_EDITOR New Symbol Editor: Do not allow duplicate properties
! d$ V7 y6 S4 Y& e0 y3 _* ^1957458 PSPICE             FRONTENDPLUGI Refresh issue with Bias Display on a new design: bias value not updated* Z+ e8 e9 V% `4 M
2022211 PSPICE             FRONTENDPLUGI Bias Point results are not updated9 j5 ]6 f/ {; O+ {( n/ |  `, ^
2031058 PSPICE             FRONTENDPLUGI PSpice bias values are not getting updated
7 {9 \3 K8 `4 q- _9 c$ g) b2038021 PSPICE             FRONTENDPLUGI Bias display is not updated
' W) a, t) ?8 q, z7 n2055274 PSPICE             FRONTENDPLUGI Capture crashes on SIMSETUP OK when two projects are open" S% x: y0 q# B7 ^
2053432 RF_PCB             OTHER         Property on RF component not transferred to new design not containing the component
5 L  c/ |0 j$ \" Z/ S2003341 SCM                SCHGEN        Unable to generate a schematic for hierarchical blocks
: \" K- K9 |+ k) e# s2 x2069924 SIP_LAYOUT         DIE_ABSTRACT_ Conversion from co-design die to standard die / BGA / anything else must remove floating function pins.
/ x4 c9 f4 A" }0 }# {& a2067894 SIP_LAYOUT         OTHER         sip database size is enormous for a small component definition used in fdesign
3 X- {1 h/ ]" a1 o# O* l2067987 SIP_LAYOUT         OTHER         Orphaned die attachment in SiP Layout cannot be removed
9 ?) Y6 \/ f; k8 ?! v2072857 SIP_LAYOUT         OTHER         SiP Layout crashes when using Find by Query and choosing 'Symbols'
1 e6 N! r/ w6 @5 V% L* Q2068973 SIP_LAYOUT         REPORTS       SiP Layout Missing Fillet report not catching a missing fillet in HotFix 051 and 0522 @( b% m) A7 O$ m8 |+ f' _8 O
2059533 SIP_LAYOUT         SYMB_EDIT_APP SiP Layout: Cannot rotate bumps in Symbol Editor application mode
( i9 |. R- d  _, D* S. g9 n* Z1 v1981749 SYSTEM_CAPTURE     ARCHIVER      System Capture: Archiving a design from the Tcl command window results in error
% Z& N4 t! p% r1 ~2054869 SYSTEM_CAPTURE     AUTOMATION    syscapUtils.tcl command cnsAutoCreateDiffPair is broken due to missing acm_code.il and acm_config.txt files
. L7 q  h: q$ v8 \1966488 SYSTEM_CAPTURE     CANVAS_EDIT   New folder rename box does not show the text typed.0 u1 Q* ^% S+ k5 {+ U* N" b
1814813 SYSTEM_CAPTURE     COMPONENT_BRO System Capture session log should specify the CDSSITE path for the current session7 U, |7 G9 r4 z6 o6 _
1977673 SYSTEM_CAPTURE     COMPONENT_BRO adding reference blocks through add component error when cell name matches design name$ X6 [1 h  G6 I. Y3 i, P, q' e" C
2027100 SYSTEM_CAPTURE     COMPOSITE_FIL pstdedb.cdsz and netlist preview in System capture is not being updated when individual netlist files are written
: D. k2 }. h1 j8 s8 o' ~1961274 SYSTEM_CAPTURE     CONNECTIVITY_ Xnet removed during pin swapping" }: z& @2 W! S! T+ K  ^1 N7 @7 _( \
2041879 SYSTEM_CAPTURE     CONNECTIVITY_ xnets on net with only pull-up resistor
6 }% N: M  q; M- w1889238 SYSTEM_CAPTURE     COPY_PASTE    Wire fails to connect during copy and paste5 `# n3 L0 b5 S
1993146 SYSTEM_CAPTURE     DESIGN_EXPLOR Cannot move page up by only one position" H) z& Z* k. F: x0 w
1910941 SYSTEM_CAPTURE     MISCELLANEOUS Parts that are not in any schematic page appear in netlsit and BOM
7 a5 N/ R3 U# A& s! X2 k/ y7 s- @1902347 SYSTEM_CAPTURE     PRINT         Prints all sheets if one sheet is specified as the print range$ S3 _1 u: p) j6 S! g; @& T
2041272 SYSTEM_CAPTURE     SMART_PDF     Smart pdf displays component outline when component is not de-highlighted.! b, }: [4 P$ @, [* Z' v* }
2065768 SYSTEM_CAPTURE     SMART_PDF     Custom Variable in Table Object not getting passed to PDF( n( |5 W) v+ I; H. ^2 {
1969243 SYSTEM_CAPTURE     VARIANT_MANAG Export variant does not name file correctly if the filename contains a space
7 E+ K0 d, b2 Z% B9 `: l1990258 SYSTEM_CAPTURE     VARIANT_MANAG Cannot paste copied preferred part to multiple parts with the same part number
0 v  f: U! ?6 T6 n6 @& I1992250 SYSTEM_CAPTURE     WORKSPACE     Double-clicking a .CPM file runs System Capture but does not open project# B+ T9 O2 D5 |. }; y+ J  f1 Q# P; T
  @$ T1 S! V9 c# Q1 x* c9 b
; o% {0 K/ @& u' ?+ V) C
Fixed CCRs: SPB 17.2 HF053/ b; m/ j3 ~" S) G) y  l2 E
03-30-2019: B4 t2 V6 V- ]: M! D
========================================================================================================================================================6 r, \. _+ _/ Z- ?% X
CCRID   Product            ProductLevel2 Title0 C3 [" w6 t+ S
========================================================================================================================================================- L+ @; X3 ]! \/ A  g/ P5 ]9 ~6 }
2035766 ADW                DSN_MIGRATION EDM release 17.2-2016: design migration UI is cut off on right* o% A9 V+ \7 e
2044872 ADW                PART_BROWSER  Component Browser: Only one PTF file read for multiple PTF files under Part Table all referenced in master.tag' H4 e  }0 r' J6 v+ S6 G) E! U% V
2025147 ADW                TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name
9 S& [0 e# `9 Y/ a9 \6 F! e2025201 ADW                TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design
( s4 d3 D. F$ z5 {7 |2052046 ADW                TDO-SHAREPOIN Joining projects is downloading 0-byte files due to SSL error' N6 w- T; Q0 D  x* s- r
2056694 ADW                TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object
- `3 n0 V9 a; G2047512 ALLEGRO_EDITOR     3D_CANVAS     Mechanical components do not move when bending in 3D Viewer) y, O' H/ G. S5 D/ p' `! }
2048086 ALLEGRO_EDITOR     3D_CANVAS     Wirebonds are not linked to diepad when component is embedded body down
# B. X. T' {5 B  ^' |2 \2051277 ALLEGRO_EDITOR     3D_CANVAS     3D View Vias are Offset from Board in Z direction
0 H% |+ W0 {# h; N) s2054327 ALLEGRO_EDITOR     3D_CANVAS     3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation+ ~" |( n, D( d% s4 @8 U. V7 J
2056547 ALLEGRO_EDITOR     3D_CANVAS     3D model not shown for component with STEP file assigned
& B1 f5 V2 Q" ~0 [) p& x: h2044980 ALLEGRO_EDITOR     ARTWORK       'Import - Artwork': PCB Editor stops responding and no artworks are loaded
- Y" l8 O" T) `1 o0 w2061203 ALLEGRO_EDITOR     CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone! q' X; \# X- f% d+ W- C1 Y/ K5 Y
1826533 ALLEGRO_EDITOR     DATABASE      Dyn_Thermal_Con_Type not behaving as defined in Symbol Editor after placing on PCB file.- h* K6 l  M! _! R( M& i7 @1 Z- n
1857282 ALLEGRO_EDITOR     DATABASE      PCB Editor slow when Manhattan and Path length tooltip enabled in datatip customization- h& ~; T, I: \/ ~, G7 V
2052767 ALLEGRO_EDITOR     DATABASE      Allegro PCB Editor crashes on editing padstack9 }& x  @( ?' U1 v
1825692 ALLEGRO_EDITOR     DRAFTING      Dimension line text moved by Update Symbols4 r$ o, N9 V6 E$ T3 X5 Z1 {
1874814 ALLEGRO_EDITOR     DRAFTING      'Connect Lines' does not merge overlapping lines
0 H1 z5 I" `+ T5 x1874935 ALLEGRO_EDITOR     DRAFTING      Angular dimension text has extra spaces added before the degree symbol.
' a* W* ~. C+ A2 m$ C' u! ]* K  j$ h1882597 ALLEGRO_EDITOR     DRAFTING      'Trim Segment' should allow trimming for all intersecting segment types
4 k% o0 m+ N1 E6 X2052315 ALLEGRO_EDITOR     DRC_CONSTR    DRC (pad-shape) incorrect when both pad and drill are offset from pad origin.
5 K8 ]4 ?/ R$ r2 z/ }3 {3 M2040603 ALLEGRO_EDITOR     EDIT_SHAPE    Shape is not updating correctly after the 'move' command
' b& {3 i4 f; z' [2050177 ALLEGRO_EDITOR     INTERACTIV    Letters need to remain aligned and uniform after performing Boolean ANDNOT operation
) b+ p% t6 s3 x2052586 ALLEGRO_EDITOR     IPC           IPC356 showing shorts and disconnects for chip-on-board design
4 g  N, ^- E7 O+ }2044350 ALLEGRO_EDITOR     MANUFACT      Cross Section table showing multiple decimal digits for the Tolerance column
' B# c) k! J, R' x4 `: x2051150 ALLEGRO_EDITOR     NC            Counterbore/Countersink holes not being shown in the NC legend table.5 I+ W7 u: s2 Y$ I# R' m9 J. f
2058199 ALLEGRO_EDITOR     NC            'Manufacture - NC - Drill Legend' does not populate the CounterBore/CounterSink row values in the Drill Chart table2 Q; b( r' Z2 b6 I
2061809 ALLEGRO_EDITOR     NC            Counter bore NC Legend does not show any data
# a* i2 D- D" d& P0 q( r, F% D2063477 ALLEGRO_EDITOR     NC            Counter bore NC Legend does not show its value
) w; A8 B  C9 w3 X% `4 k1 L4 x# o9 f2033849 ALLEGRO_EDITOR     PLACEMENT     PCB Editor stops responding when removing a plane that the Place Replicate command added6 h$ L( H/ ]: G9 d: Y7 [$ |1 K6 d3 r1 `
2037509 ALLEGRO_EDITOR     PLACEMENT     Move or Rotate or Mirror of a module/group makes PCB Editor to crash with no .SAV file created
; X6 m/ `# r/ c& ~$ C- U2047480 ALLEGRO_EDITOR     SCHEM_FTB     Importing netlist using Capture-CM flow in PCB Editor is crashing netrev3 v2 ]& a: Q; q2 _
2046276 ALLEGRO_EDITOR     SHAPE         Add notch is not snapping to the grid point9 Q3 L: M2 s/ P4 `9 R  g% g+ ?
2047572 ALLEGRO_EDITOR     SHAPE         Voiding elements on static shape do not void adjacent layer keep-outs and PCB Editor stops responding
  Z# o" w, \! V* N2048483 ALLEGRO_EDITOR     SHAPE         Shapes not getting updated post backdrill update, ]6 ?5 y1 ]" p' D" O$ Q$ d9 u8 g
2050120 ALLEGRO_EDITOR     SHAPE         Dynamic fill is flooding over other etch shapes within a symbol.+ n7 u8 e% @: q, @9 Y+ }* D0 @
2058017 ALLEGRO_EDITOR     SHAPE         Shape not voiding correctly when fillets are present( a% g7 J8 N/ i8 n% x; s! W
2010569 ALLEGRO_EDITOR     SKILL         Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in hotfix 048.
% l& U& z4 P! P2 T7 @4 Q2 @1 b2055055 ALLEGRO_EDITOR     SKILL         Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash4 [4 m* u7 |5 L4 J1 v9 Z
1961689 ALLEGRO_EDITOR     SYMBOL        Pin Numbers are moved from center with Pin Rotation when adding pins to Footprint
7 P& K5 Q' f& O9 L, [/ i, Z2034949 ALLEGRO_EDITOR     SYMBOL        Angular dimension from DRA not created in PCB
/ r8 \0 O; |1 G2046242 ALLEGRO_EDITOR     UI_GENERAL    Searching User Preference Summary results in crash
- O2 X1 b  u, k5 P) Z2 G2053496 ALLEGRO_EDITOR     UI_GENERAL    Confirmation dialog box is behind canvas
7 J" j9 g; G! L6 L: F* H2063423 ALLEGRO_EDITOR     UI_GENERAL    Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden
* G, ]% j8 e# o7 ]5 L1886781 ALLEGRO_VIEWER     OTHER         Opening Color192 in Allegro Free Viewer causes it to crash
( p- ]( S; U# X- I7 F0 @  z1 ^1699433 APD                EDIT_ETCH     Field solver runs when not expected. b% e% s; y  d5 E" e* R$ \
1937159 APD                EDIT_ETCH     Routing clines takes long time
/ r7 E( @% z* x% \8 W6 B& i6 x2050863 APD                SHAPE         Taper voiding process is different in Within the region/Out of Region
9 W  P; s; l# O+ ]; n5 k2047391 CAPTURE            PART_EDITOR   Pin type cannot be changed in hotfix 0512 }$ C, n4 q% @8 m5 \9 p
2049161 CAP_EDIF           IMPORT        Fatal error 'cannot determine grid' when converting third-party design to Capture2 ?! H0 f) E! r' F% H
2053578 CONCEPT_HDL        CONSTRAINT_MG Values specified for custom properties are not preserved
% D8 a* d& i2 ]. Q" ?8 C2047583 CONCEPT_HDL        COPY_PROJECT  Design Entry HDL crashing when trying to open page 52 of copied project" _# R: T* ?' W0 F( y; k
2036239 CONCEPT_HDL        CORE          When cutting/pasting, multiple error pop-ups appear for the same notification, c6 _3 |. o: e+ o
2037572 CONCEPT_HDL        CORE          Warning (SPCOCD-578): Soft VOLTAGE property found is misleading and should be auto resolved when closing CM
" J( s8 t* Z3 Q* J# N6 V2037578 CONCEPT_HDL        CORE          VOLTAGE property gets deleted after copying it from a non-synchronized source, Y& h$ [9 l* Y- |6 q, `/ m5 H
2046958 CONCEPT_HDL        CORE          Moving block pins from symbol right to left places pin names outside the symbol
. R* ]$ A3 Q! M2032480 CONSTRAINT_MGR     CONCEPT_HDL   Incorrect matchgroups created when working with multiple level nested hierarchical blocks
# |+ I! y" K% W2045274 CONSTRAINT_MGR     CONCEPT_HDL   Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor
1 X9 ]3 I* V( j# b4 _  g6 A2046765 SIP_LAYOUT         DIE_ABSTRACT_ SiP Layout 'dump libraries' crashes when exporting library/ k& |0 b& |" C
2067970 SIP_LAYOUT         DIE_ABSTRACT_ SiP Layout cannot dump libraries, viewlog is empty0 p8 r: d" k4 i; x  ?# ]' v
1981749 SYSTEM_CAPTURE     ARCHIVER      System Capture: Archiving a design from the Tcl command window results in error# T8 a4 U$ m2 G7 b4 _4 u
1968437 SYSTEM_CAPTURE     ASSIGN_SIGNAL Net name pasted in lower-case though UPPERCASE INPUT is enabled
  I& |8 F# l# U3 ^# s1983063 SYSTEM_CAPTURE     AUTOSHAPES    Auto Shapes are being shown as part of components
; e3 A8 H& F# V% y, n; x8 `1968463 SYSTEM_CAPTURE     CANVAS_EDIT   System Capture should not allow illegal characters to be entered for net names
& k0 C2 x# y9 F0 ?+ ^) W2006593 SYSTEM_CAPTURE     CANVAS_EDIT   Asterisk in a search string is not treated as a wildcard character
8 S4 d% p' b- P, K1 O+ [1721863 SYSTEM_CAPTURE     CONNECTIVITY_ Net Names move to random locations when the components are moved around the canvas
4 U  g. n! B8 H+ M3 ~% [1960130 SYSTEM_CAPTURE     CONNECTIVITY_ Disconnected nets when using the mirror option
$ N/ E3 f* h2 W, s! N' T1985029 SYSTEM_CAPTURE     EDIT_OPERATIO Net aliases do not drag with circuit, they appear to move after the circuit is dropped
+ C5 |% f$ [/ ~+ D- f1895142 SYSTEM_CAPTURE     EXPORT_PCB    System Capture reports incorrect unsaved changes when closed after running export physical
% q' w: k$ G' [. t& z4 b6 Z1628596 SYSTEM_CAPTURE     FIND_REPLACE  Alias issue in Find: Results do not show the resolved physical net names
" J+ N6 f, e" G; W: s0 c* P, k1988297 SYSTEM_CAPTURE     FIND_REPLACE  Edit > Find and Replace does not replace a net with an existing net on the canvas6 |+ E) E2 @6 W
1843885 SYSTEM_CAPTURE     FORMAT_OBJECT Renaming a net causes it to lose custom color assignment4 Q& M, e6 K. V( ?, i
1969308 SYSTEM_CAPTURE     FORMAT_OBJECT System Capture: Clicking arrows to increase/decrease font size does not work correctly when clicked fast. A/ e2 s% X8 e
1990060 SYSTEM_CAPTURE     FORMAT_OBJECT Bold, italics, and underline formats not visually shown on all selected objects concurrently. n: A  O  b4 \' \$ R& {8 ^
1993208 SYSTEM_CAPTURE     FORMAT_OBJECT Setting font prior to placing text does not work, pop-up does not work, and bucket results in scrolling page* f7 C! o" T0 ]: L3 u! `; r: ^
1981775 SYSTEM_CAPTURE     IMPORT_PCB    Import Physical takes a long time on some designs to launch the UI
! E& {& v; c" Z% G$ T4 I1982320 SYSTEM_CAPTURE     IMPORT_PCB    In the B2F flow none of the *view files are created$ x( S) `- _. J0 ]8 H& e8 @+ E
2010996 SYSTEM_CAPTURE     INSERT_PICTUR Image in title block is at a wrong location in design: correctly placed in library
, Y4 Z) L& G! D9 X! v* Y1967614 SYSTEM_CAPTURE     MISCELLANEOUS Dragging a circuit with net aliases does not move the net aliases with it
' o6 \. h- c6 }; f/ u1980999 SYSTEM_CAPTURE     NEW_PROJECT   System Capture stops working with message regarding Part Manager initialization for a design based on DE-HDL
' B9 Q/ F* B) l5 ^( p5 K1973437 SYSTEM_CAPTURE     OPEN_CLOSE_PR Opening a design crashes System Capture
7 {1 A; K% g4 _( z! u/ n4 M1 J6 r1986566 SYSTEM_CAPTURE     OPEN_CLOSE_PR System Captures stops responding on opening project, cleaning project displays project already open message$ S. x; X+ j) I5 {
1993093 SYSTEM_CAPTURE     OPEN_CLOSE_PR Add option to override the lock file similar to Allegro PCB Editor5 f) j, N) E5 H. d) F5 C
2042360 SYSTEM_CAPTURE     OPEN_CLOSE_PR System Capture will not open nor gives error message when previous lock file present inside the logic folder
3 q3 f- J- @' @1 e1992247 SYSTEM_CAPTURE     PART_MANAGER  Part Manager displays message for undo and redo stack even after specifying not to show message
; N/ G9 x' b* c- U3 y2048000 SYSTEM_CAPTURE     PERFORMANCE   Performance issue when instantiating and moving a component
# x) {7 e$ e+ x: q8 e1892120 SYSTEM_CAPTURE     PROPERTY_EDIT Some parts missing reference designators and some have two properties, RefDes and REFDES; F# z" ^/ D! I. h. j; [
1970009 SYSTEM_CAPTURE     PROPERTY_EDIT System Capture: Right-clicking RefDes with conflict in 'Edit Properties' shows the Hyperlink option- h- q$ E1 h, p' K! r+ C, |
2042707 SYSTEM_CAPTURE     VARIANT_MANAG variant.lst file under 'physical' folder not updated when closing Variant Editor
% j" E/ R2 U0 r
& l+ U: J0 a+ _& `
/ b6 v0 [1 w, `/ u* kFixed CCRs: SPB 17.2 HF0521 `; o" l9 i8 p# D% I/ @
03-01-2019
* b1 w- e9 l5 M8 a4 Q8 v4 Z9 e========================================================================================================================================================
5 [9 e0 o; ^4 l* j/ lCCRID   Product            ProductLevel2 Title1 }( l# F) t: g  p5 I0 h! j' u
========================================================================================================================================================
, [7 z  g% }+ }6 Z4 W) j2020429 ADW                ADWSERVER     Incorrect adwservice status on Linux
2 r/ q+ E  q( h5 Z3 B9 J2034815 ADW                LIBDISTRIBUTI Cannot mark classification obsolete because it is associated to objects in the database1 \" J2 f2 q3 y  r5 }! v. M5 ~
2015461 ADW                PART_BROWSER  New Component Browser should read the mapping of symbol and associated package as it results in error PKG-1005  F/ ~0 S* _; |  t! y8 J
2049380 ADW                PART_BROWSER  System Capture Import HDL not importing complete PTF File data  Y. D4 e3 s5 H& ^2 _# s; F
1948608 ADW                TDA           CUSTOMVAR directive value in project CPM was not updated by TDA UPDATE command.
- i! U# Q6 }- q; Z8 i# ^1992662 ADW                TDA           Custom directive added to the cpm file not updated after check-in3 `) M0 Z2 R  ?. B4 E
1733129 ALLEGRO_EDITOR     COLOR         'Display - Highlight', double-click permanently highlights symbol* x1 x6 I" B0 n0 ]) q6 f( B7 ~
1861938 ALLEGRO_EDITOR     COLOR         Changing layer color changes layer visibility
# S* f% X% H- J2034753 ALLEGRO_EDITOR     CROSS_SECTION Allegro PCB Editor crashes when a cross-section technology file is imported in Overwrite mode  a2 e; @( B+ r4 Y3 s( f  P
2036895 ALLEGRO_EDITOR     CROSS_SECTION Replay script error during import of tcfx Xsection file/ m& K6 ?' s/ ~( b$ n
1929360 ALLEGRO_EDITOR     DATABASE      Via color is inconsistent on Vias with color assigned
( \) B- V& Y5 i) U, {4 O1984203 ALLEGRO_EDITOR     DATABASE      Drill holes not displayed correctly in the Zone area5 F' B/ T# [* E- v* s( ?# B" k4 q
2013596 ALLEGRO_EDITOR     DATABASE      Assigning net name on Vias does not change the Via Color to that on Net Color automatically
0 s# ^- X+ }! l0 l' `' [2025798 ALLEGRO_EDITOR     DATABASE      Assign net to via changes color of the via to the default color: b1 z; G" y" `; d% @3 E
2032678 ALLEGRO_EDITOR     DATABASE      Unable to delete layer on design6 g. ?/ {. w5 R' d0 S% ^5 s
2032725 ALLEGRO_EDITOR     DATABASE      Dehighlight removes color assignment from color dialog
% W4 J: S  V( G5 n4 E! L2029542 ALLEGRO_EDITOR     DFA           Interactive Placement with Manufacturing Package to Package spacing
& u& c1 c8 |/ S( Z2 G! D- P, T2020548 ALLEGRO_EDITOR     DFM           Cadence DFM Customer site cannot Submit Request
' `# _( V0 o) j4 M9 `5 y5 l' X& o2020566 ALLEGRO_EDITOR     DFM           Error when sending Design True DFM Rules Request" y$ Q; O" [1 ^
2030179 ALLEGRO_EDITOR     DFM           Allegro PCB Editor .brd file will not save after routing using Automatic Router" l1 R! a- T1 p
2052907 ALLEGRO_EDITOR     DFM           The Submit Request button for DesignTrue DFM Rules Request does not work
: H& p$ O$ z0 J: f0 z1928915 ALLEGRO_EDITOR     EDIT_ETCH     PCB Editor constraint status bar does not match Constraint Manager data when z-axis delay is turned on.  X4 L7 Y: v; @0 w
1932165 ALLEGRO_EDITOR     EDIT_ETCH     Arc slide behavior with clines at odd angles: notches on slides; U( h0 `! @$ p/ e2 i5 g
1943901 ALLEGRO_EDITOR     EDIT_ETCH     arc segment incorrect on slide.) |- P9 g: ~& Z/ \- q
2031055 ALLEGRO_EDITOR     EDIT_ETCH     On drawing cline the width on a Layer is larger than defined constraint
6 q* u' f2 J3 P& C6 N, Y7 j: s1877891 ALLEGRO_EDITOR     GRAPHICS      Allegro PCB Editor crashes when started from EDM for projects without a board file or empty master.tag file1 T! m1 ?) }7 r5 q* Y- R
2040689 ALLEGRO_EDITOR     NC            The decimal digits of a rotated oval padstack do not match the Drill Chart.
0 I1 v% S: \7 F' V2028105 ALLEGRO_EDITOR     PLACEMENT     Delay in moving a large count pin symbol  P# z9 n: |+ c2 V) D- r/ q
2019027 ALLEGRO_EDITOR     REPORTS       Information shown in the Report Viewer is not correct.1 F4 Z, k8 z5 c; q% h: F: p$ I
2022461 ALLEGRO_EDITOR     SHAPE         Abnormal termination of  thieving function in Allegro PCB Editor
) w8 v! r0 E% P; S; V( n2032048 ALLEGRO_EDITOR     SHAPE         shape void difference from hotfix 026 to 048: need square corners for full round
* B4 c6 r$ I; `/ k4 R0 K7 {+ b8 {2040138 ALLEGRO_EDITOR     SHAPE         shape_rki_autoclip affects the overlapping shape boundary, L9 \& J( r) ]
2040259 ALLEGRO_EDITOR     SHAPE         Same net shape and cline adds shape void around cline
/ y# k3 s  s1 o/ n/ ~0 @3 Z/ h0 {" L2031468 ALLEGRO_EDITOR     TECHFILE      Cross section import (.tcfx) not working correctly.
- b0 i! s+ M! N2006425 ALLEGRO_EDITOR     UI_FORMS      Option to disable 'Create a New Design' window in OrCAD PCB Designer0 R3 R3 ~% g1 X3 _. x3 f. X
2007451 ALLEGRO_EDITOR     UI_FORMS      Option to suppress 'Create a New Design" window for File > Open in OrCAD PCB Editor from hotfix 048
  @" E3 h9 r1 N7 M, w' w2009314 ALLEGRO_EDITOR     UI_FORMS      Existing scripts that open OrCAD PCB Editor not working in hotfix 048
* w! D! o6 A- Y  V2021476 ALLEGRO_EDITOR     UI_FORMS      PCB Editor is slow when using the command 'add connect'
4 I" J5 m# t2 @& b2039462 ALLEGRO_EDITOR     UI_FORMS      Hovering over Default symbol height in Design Parameter Editor does not display a description9 T+ N0 s% ]& b* }
1808054 ALLEGRO_EDITOR     UI_GENERAL    Illegal value in axlFormSetField crashes PCB Editor
3 _9 Y8 j% D& o0 w1822679 ALLEGRO_EDITOR     UI_GENERAL    'Symbol pin #' field is truncated on rotating components in the Placement Edit mode) U- J2 A4 C% ]" Q+ Q: J
1856438 ALLEGRO_EDITOR     UI_GENERAL    Script recording messages not displayed in the PCB Editor task bar when using the script window.2 o, @+ n8 P" P2 ~. }6 h
1879078 ALLEGRO_EDITOR     UI_GENERAL    Running PCB Editor from command prompt with '-product help' should list all products and options, Z8 j0 r1 p1 [' Y: i. O" b! F" y
1944225 ALLEGRO_EDITOR     UI_GENERAL    Cannot close log file window till we close report dialog box
/ n& x" q- ?3 G1967708 ALLEGRO_EDITOR     UI_GENERAL    New Command Window Shows Last Command in UI+ x: T* H" _9 B! G( w2 H
1968380 ALLEGRO_EDITOR     UI_GENERAL    Write all open editing sessions in MRU
) Y! `! o9 K  y" G. A, G1982138 ALLEGRO_EDITOR     UI_GENERAL    axlFormListDeleteItem(fw field -1) not deleting last item of a list: F% V- G0 ~4 B
2003054 ALLEGRO_EDITOR     UI_GENERAL    Grids not shown when 'nolast_file' is set
( W) \8 d* ?! k( P2010760 ALLEGRO_EDITOR     UI_GENERAL    Pressing tabs is selecting only vias and not selecting clines in PCB Editor in hotfix 048
1 P1 B. T  X& M* L. o( r/ G5 W. |2019120 ALLEGRO_EDITOR     UI_GENERAL    Tab key is not working when there are two objects on top of each other+ X! l) S4 @( E" o! R& r
2029248 ALLEGRO_EDITOR     UI_GENERAL    Colorview load is not working when using absolute path: g8 {: f% k2 a
2030985 ALLEGRO_EDITOR     UI_GENERAL    The view of the PCB is offset after closing and opening the board./ X: W  l9 W0 t+ D
2037968 ALLEGRO_EDITOR     UI_GENERAL    Tab key will not cycle between cline elements.
  e1 t6 P* J6 R2 c8 ~: z2015766 ALLEGRO_PROD_TOOLB CORE          Advanced Testpoint Check does not work
- M' c% k* x' K4 P6 n! i2023356 ALLEGRO_PROD_TOOLB CORE          Edit new session does not work in quick symbol editor tool box9 F2 s( H4 Y4 X6 g
2017162 CAPTURE            CONSTRAINT_MG Cannot apply ECSets in Constraint Manager-enabled Capture, r0 r) c7 H* S4 c( m
2026777 CAPTURE            CONSTRAINT_MG Cannot apply electrical CSet (ECSet) in Constraint Manager-enabled Design Entry CIS' e$ B) ?# L- |4 y, m# B7 p5 }+ g7 t
2027545 CAPTURE            CONSTRAINT_MG Getting error (ORCAP-40320) while creating ECSet
9 F6 n( y' s9 k: Y* U/ h( p2012967 CAPTURE            OTHER         Capture license is loaded slowly in hotfix 048
5 R1 k$ J8 {! V# a) A2010093 CONCEPT_HDL        ARCHIVER      Archive .zip file keeps the whole folder hierarchy and not only the project hierarchy& R, X7 e2 x) q- Y6 t7 A8 l8 z
2040431 CONCEPT_HDL        EDIF300       EDIF300, Schematic Writer, crashes in release 17.2-2016
. ~/ q' T/ J/ C. q2034077 SIP_LAYOUT         DFA           DRC is not catching all Shape minimum width violations3 [. d! ^, z% \4 a% q5 k( _
2034094 SIP_LAYOUT         DIE_ABSTRACT_ [VSDP-RDL Exchange] some traces are lost in SiP Layout
8 h0 m7 e9 Z1 H5 ]! L" D/ @2037462 SIP_LAYOUT         DIE_ABSTRACT_ Cline Segments are lost on saving and re-opening the design in next session, _! w* M, P& u) T7 J
2025321 SIP_LAYOUT         IMPORT_DATA   compose symbol from geometry defaults need to change due to performance
# Z2 Q# ^* l' n3 g4 v' V% b2017759 SIP_LAYOUT         PLACEMENT     Placing a die creates extra place bound and puts pin numbers in the wrong place, causing future netlist import failure0 N+ o3 z9 d3 n* n3 D
2021057 SIP_LAYOUT         SHAPE         Polybool assert error when adding dynamic shape prevents shape voiding.
6 [9 N' g$ `1 Z2012381 SIP_LAYOUT         SKILL         Ability to check if the Dynamic Unused Pads Suppression box is selected using SKILL: w+ F3 T0 ?* k3 [
1990299 SIP_LAYOUT         UI_GENERAL    Pressing 'Esc' cancels DRC checking when there is no focus on the Allegro PCB Editor canvas
$ n( b) S. N9 d9 L. D1997317 SIP_LAYOUT         WLP           Advanced WLP, Metal Density Scan does not correctly calculate scan region count in Y direction1 h/ M  I$ o8 S/ y
2029524 SPECCTRA           ROUTE         SPECCTRA stops responding when executing the quit command
9 t$ q" Z9 R6 P1 ?! n1670888 SYSTEM_CAPTURE     CANVAS_EDIT   Rotation error when connected to a power symbol
4 |6 ?7 U& ~5 p1 H$ r4 ^# O! }1880809 SYSTEM_CAPTURE     CANVAS_EDIT   Can modify only one RefDes from canvas for duplicate RefDes; can modify both from the Properties window
% K4 j( ]1 d+ i7 v1979063 SYSTEM_CAPTURE     CANVAS_EDIT   System Capture : File > Close is grayed out' C1 Z) r( D4 v. S5 a% q! _/ I+ f
2034498 SYSTEM_CAPTURE     CAPTURE_IMPOR Cannot find parts via Find & Replace after importing Capture design2 J6 }3 P; x  q3 s: m: y2 @$ S
1984561 SYSTEM_CAPTURE     CROSSPROBE    System Capture: Cross-probing from layout does not work when zoomed into a specific area on canvas
$ o& K* _0 B7 i; j7 i7 O% O) v1863460 SYSTEM_CAPTURE     DARK_THEME    thumbnail preview of pages is in light them but dragging the page the previes is dark0 W: c, l! u% V( ]8 S- @. B- e1 {1 t
2025876 SYSTEM_CAPTURE     EDIT_OPERATIO Route failures when dragging a circuit
3 B  k7 c, @( t* k+ R2005904 SYSTEM_CAPTURE     FORMAT_OBJECT Pin name text is smaller in System Capture than in DE-HDL by about 25%2 |3 r/ T4 J2 h: }. h8 j" }) C
2036782 SYSTEM_CAPTURE     IMPORT_BLOCK  Unable to import the block from project.; X) ^( Y/ g5 ]6 Z
2025949 SYSTEM_CAPTURE     IMPORT_DEHDL_ Title block and thick wires/lines of border in DE-HDL do not  translate in System Capture7 u6 j3 J  x* v! G# r* Z3 ]* d
2025950 SYSTEM_CAPTURE     IMPORT_DEHDL_ Broken connectivity on imported ground symbols
" h5 H1 T/ J+ K- U$ `) k, x2040923 SYSTEM_CAPTURE     MISCELLANEOUS System Capture - Multiple Symbol Replace, disconnects and changes orientation6 j! k. @* x5 ^0 F
2017526 SYSTEM_CAPTURE     NAVLINKS      Page information missing in NAVLINKS
, s' O1 k# x: x) m2015346 SYSTEM_CAPTURE     PAGE_MANAGEME Rename page fails in some cases
  k) V1 S# L2 n% m3 ~2038811 SYSTEM_CAPTURE     PRINT         Black & White PDF showing colors
: r6 {+ ^3 ?$ }2 _- z  ^8 s; H2048493 SYSTEM_CAPTURE     SYMBOL_GEN    Symbol Editor, Modify outline adds an 'X' in symbol incorrectly
& K5 ^' n3 I1 j2031995 SYSTEM_CAPTURE     VARIANT_MANAG Variant Editor does not load the design and restarts the machine after sometime.8 m  @( m* `9 ]3 u+ W4 u+ V3 r1 H
2032005 SYSTEM_CAPTURE     VARIANT_MANAG Custom variables not saved for variants6 ]+ e9 G0 P7 ?
1968431 SYSTEM_CAPTURE     WORKSPACE     Unable to reorder the pages (tabs) when opened in the workspace6 e' j6 I0 u* g% A' ?
2040995 XTRACTIM           GUI           Running XIM from APD enables "skip DC R simulation" by mistake
1 _; b  o+ W( H1 c& J3 d! s3 @+ P$ E4 G8 k, Q

. Q9 j/ L2 w. Z# m: l8 `5 p. H& qFixed CCRs: SPB 17.2 HF051' v0 Z4 F, r7 B6 U; g( \
01-30-2019
( a7 x( E7 ~) ^# I========================================================================================================================================================0 Q; [8 ~: u( R4 G
CCRID   Product            ProductLevel2 Title
* E- b2 O( _' D- n: U========================================================================================================================================================
+ {! c% v, l3 @# u/ C: z  m* V2015843 ADW                LIBDISTRIBUTI Error for library distribution (lib_dist_client) regarding string index out-of-range5 k- j6 K- n% x  n4 k9 t# r8 v$ z
1869914 ADW                PART_BROWSER  Adding components to System Capture schematic canvas takes long time in Linux clusters
8 O+ S  n* l9 C: R# c$ `2 Y2010458 ADW                PART_BROWSER  RefDes values not appearing on parts
) B0 V/ s4 C4 B5 L5 p( b# x4 k2022630 ADW                PART_MANAGER  Unable to successfully import a DE-HDL Design into System Capture6 U/ d6 v& `: ~+ p8 h5 D9 U
2005033 ALLEGRO_EDITOR     3D_CANVAS     3D Flex issues: Error message when opening design with bends in 3D viewer
7 D  F/ S+ {& a7 P. N- U0 s" q/ C2023496 ALLEGRO_EDITOR     3D_CANVAS     Error for designs with bend in 3D Viewer+ g& I# a2 q: |7 i! B2 I% s, J
2033459 ALLEGRO_EDITOR     3D_CANVAS     3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation( w* m/ `4 Y' D. i
1996431 ALLEGRO_EDITOR     ARTWORK       Via holes for connection have incorrect coordinates in Gerber( B9 F3 V" w. c
1995656 ALLEGRO_EDITOR     DATABASE      Attaching and Detaching a text file created with SKILL writeTable() function corrupts the text file3 |" r/ }' T4 `/ \
2027122 ALLEGRO_EDITOR     DATABASE      PCB Editor crashes when creating Place Replicate module- p+ l5 G1 m6 N3 U+ T" x3 M
2023916 ALLEGRO_EDITOR     DFM           DFF Annular Ring: Thru via pad to Mask violates on via in pad instances.
1 }" S; w8 g- V$ G, p- K9 y2024523 ALLEGRO_EDITOR     DFM           PCB Editor crashes in Mask To Trace check of DFF.
& b( N% u7 n) a- g& N! P2021318 ALLEGRO_EDITOR     IN_DESIGN_ANA Integrated Analysis and Checking: Unable to run simulation with Crosstalk flow$ Z) l( O4 j, j/ i8 f, v8 u( ^8 G+ n
2014162 ALLEGRO_EDITOR     NC            Backdrill results using an OrCAD Professional license showing wrong values with hotfix 0487 n& L: b1 v9 e% ~
2010791 ALLEGRO_EDITOR     PLACEMENT     Setting dfa_pause_level to 3 and then moving and rotating part places the part with offset4 l! _( n0 {' T: c- e! v- X
2017112 ALLEGRO_EDITOR     PLACEMENT     place_boundary shown at wrong location when moved with User pick and footprints rotated
) l# `4 p5 D' ?) [3 B8 S# O  V2028048 ALLEGRO_EDITOR     PLACEMENT     Rotate option using pick is rotating the outlines in different axis in view0 Q& n% O, b0 x) a7 O; n. M1 Z
2028314 ALLEGRO_EDITOR     PLACEMENT     Crash on moving components in Allegro PCB Editor2 b0 u0 }) ~( p  F0 j$ a
2029235 ALLEGRO_EDITOR     PLACEMENT     PCB Editor crashes when moving more than one component and hovering on IC
' K" T& j/ G0 i* s2022644 ALLEGRO_EDITOR     SHAPE         dv_fixfullcontact obsolete in release 17.2-2016
% _4 W8 A: [+ ?2 F9 K% V/ C. C2023322 ALLEGRO_EDITOR     SHAPE         Gloss does not add teardrops on all clines.3 X" R4 i: M* H# d( N
2024235 ALLEGRO_EDITOR     SHAPE         Copper Pour disappears when area includes parts3 y$ Y9 y$ H$ V* ~
2024531 ALLEGRO_EDITOR     SHAPE         rki_autoclip is not working at a special XY location( g2 M5 Z1 G) k7 Y0 A
2024599 ALLEGRO_EDITOR     SHAPE         Cannot create round corner for shape8 @0 J2 a3 B. n7 ]6 c  \
2024707 ALLEGRO_EDITOR     SHAPE         In-line void control does not work when there is no_shape_connect property attached
$ `' v# @% x; u: V! A& U2026849 ALLEGRO_EDITOR     SHAPE         Cannot assign region name using the 'next' operation
* z* m& l+ `4 z) F0 u/ Y. U2030156 ALLEGRO_EDITOR     SHAPE         Shape Area report for cross-hatched shape includes hatching and boundary+ \5 v  R2 d1 ]
1852981 ALLEGRO_EDITOR     SKILL         Error message while creating Copper Mask layer without a name using SKILL not clear
, \/ Q+ v8 g& C2 |1 k5 z1968054 ALLEGRO_EDITOR     SKILL         Document of axlClearObjectCustomColor should indicate that it can clear color for DBID of Net! u) H; U+ f( a1 L( K0 \
2026429 ALLEGRO_EDITOR     UI_FORMS      PCB Footprint wizard: horizontal and vertical lead pitch level reversed in the image7 \+ E1 ]) O+ X9 ^5 n
1768032 ALLEGRO_EDITOR     UI_GENERAL    Numeric keypad does not work for file selection shortcut( V# F1 Z% Q, C/ Y. b9 J* z
1797376 ALLEGRO_EDITOR     UI_GENERAL    Release 17.2-2016: Padstack Designer saves padstack to the working directory when script is used
; j6 ^; A( K; P' T" h- S2 A8 ?9 j$ K1798524 ALLEGRO_EDITOR     UI_GENERAL    Unable to save a padstack using script% C* h+ _0 a* n6 F6 d, |0 ~) T: l3 n
1823031 ALLEGRO_EDITOR     UI_GENERAL    Help not working for OrCAD Productivity Toolbox/ ?6 F' Y4 s# Q3 a6 b; T* u
1849921 ALLEGRO_EDITOR     UI_GENERAL    Analyze menu missing in OrCAD PCB SI
. `' F2 F" ~0 b1951740 ALLEGRO_EDITOR     UI_GENERAL    Trigger for 'open' does not work when opening a .dra file& j# t1 l( [) l; }( ?
1952163 ALLEGRO_EDITOR     UI_GENERAL    Analyze menu missing in OrCAD PCB SI
& k2 U0 u# S/ h9 ?' y1982966 ALLEGRO_EDITOR     UI_GENERAL    SKILL command to access the Option window fields while in Interactive commands.1 f- g) k* M+ l5 s( h# x1 {
1983567 ALLEGRO_EDITOR     UI_GENERAL    Alias with Ctrl not working with 'command window history' variable enabled
( G3 M9 L/ X  z' }# d+ ?, K1989507 ALLEGRO_EDITOR     UI_GENERAL    Third-party tool causes PCB Editor to stop responding to command1 _6 w4 ?+ M2 G5 z" \
2003511 ALLEGRO_EDITOR     UI_GENERAL    Aliases using control (tilde) characters stopped working after upgrading to hotfix 048
% R9 B2 ^6 f7 G+ a! y8 P0 s3 g2010418 ALLEGRO_EDITOR     UI_GENERAL    New command window breaks funckeys& Q$ R1 N: _( E! t/ ]) @
2018201 ALLEGRO_EDITOR     UI_GENERAL    SKILL axlDBControl ('activeLayer /') updates active class/subclass but ministatus form not updated
' y. d& b! E1 @, v4 c0 w% U2023468 ALLEGRO_EDITOR     UI_GENERAL    axlZoomInOut does not zoom out, always zooms in regardless of zoom factor (positive or negative)
3 w* I9 q- u# u1 t% M+ K" a; g2026428 ALLEGRO_EDITOR     UI_GENERAL    PCB Editor takes several minutes when saving a design
7 X1 y9 B5 v% R8 D2032697 ALLEGRO_EDITOR     UI_GENERAL    Funckeys with Ctrl not working with 'command window history' variable enabled
6 y5 j) e# W* ~# A: q2032717 ALLEGRO_EDITOR     UI_GENERAL    Funckey combinations, such as Ctrl + M, not working9 U6 n: Z4 u$ [2 D
2014211 ALLEGRO_VIEWER     OTHER         Arrow keys are not panning in Allegro Physical Viewer
( I' u0 Q: T6 I5 e& A2 T2039081 CAPTURE            NETLISTS      Netlist not created: netlist fails for numeric pin names with backslash '\'
) c) P% ?, R& ]3 F, ~! x( @8 z1993057 CONCEPT_HDL        CONSTRAINT_MG Constraints disappear in hierarchical design (Electrical->Net->Routing->Relative Propagation Delay)  C9 L( ]4 w; I* r7 h6 Z. R
2004641 CONCEPT_HDL        CONSTRAINT_MG 'Save Hierarchy' (hier_write) deletes bus object in Constraint Manager
- h) ]7 w& z1 G1 @2020901 CONCEPT_HDL        CONSTRAINT_MG Incorrect match Groups created in CM (TDO design)
% U+ j6 L: D$ q8 L2 d" T* ^$ k2014979 CONCEPT_HDL        CORE          The active schematic page randomly changes while editing text
- T0 x$ `' U4 `$ J9 m  \+ k+ v, w3 \) t2027905 CONSTRAINT_MGR     DATABASE      Pin Property changes in CM during uprev to release 17.2-2016$ c3 @$ X: U$ b
1762263 ORBITIO            INTERFACES    Add set allegro_orbit_import variable to user preference: |. R' E2 {  d$ J
2005860 PSPICE             LIBRARIES     Error when simulating design with TL494 part in release 17.2-2016; }( J  G2 C+ y; x8 u3 b+ d
1980072 PSPICE             SIMULATOR     Noise in the waveform when using DELAYT and DELAYT1 with capacitor
& K8 L1 m$ N3 A: d3 B1977615 RELEASE            INTEGRATION   Cannot import third-party schematics into OrCAD Capture in release 16.6
& ]0 V! Z$ w8 s) d2027009 RF_PCB             SETUP         'RF-PCB' - 'Setup' changes not saved on Apply
2 u8 u: e: ?) l5 U2002040 SIP_LAYOUT         MANUFACTURING IPC 356 'ignore die layers' does not work: netlists to die
$ h1 W" h5 z; D0 T5 |, A* H% Z4 w2024703 SIP_LAYOUT         WLP           Cannot Add Pin Text: Error on 'Manufacturing' - 'Documentation' - 'Display Pin Text'
8 K4 n7 h  H6 t, v) z7 A. }; G2010045 SYSTEM_CAPTURE     CANVAS_EDIT   Cannot snap back vertical CAP until moved up and down horizontally& S# v: c: Z: K$ s( b8 h6 i7 g
2010443 SYSTEM_CAPTURE     CANVAS_EDIT   Cannot select the CAP part' F1 u( u2 v  u0 M
2012843 SYSTEM_CAPTURE     PACKAGER      Cannot short two grounds in the schematic
  I( ^2 T4 ~  K* S2015574 SYSTEM_CAPTURE     PACKAGER      System Capture is treating quotes in PTF files differently from DE-HDL
0 x$ u5 _/ b: z9 B' S0 r1 G2022653 SYSTEM_CAPTURE     VARIANT_MANAG Variant Editor - Allow Alternates where ALT_SYMBOL is a valid match for JEDEC_TYPE
" r7 }% m3 G- P1 r6 u8 q% t2024742 TDA                SHAREPOINT    Accessing projects is taking time
' i# W2 H3 t. t" F2010531 XTRACTIM           OTHER         Allegro crash on repaint of command window$ O: h0 D& l' r; c, |+ k" H$ z- C0 u
2022351 XTRACTIM           OTHER         XtractIM is crashing the latest HF S049
/ f+ z, V* K" _5 A( E/ X
+ l) C5 W+ {$ p2 ^2 \9 u9 x! o, M
3 E5 r+ m# Q; [3 p# f/ cFixed CCRs: SPB 17.2 HF050
, ^# P2 w) ]8 d2 e8 z1 W12-23-2018' c  v7 m9 d; p( b% D1 z4 m
========================================================================================================================================================" F' y4 C6 X( ?) \8 h" Q8 X
CCRID   Product            ProductLevel2 Title
* }8 c; u3 W1 S: l; c4 g  N% o========================================================================================================================================================
( W# H! ~$ A4 r* U* j( \; L* h2012119 ADW                ADWSERVER     Cannot connect Component Browser to server
9 T+ [# x; c2 a3 j1998856 ADW                ADW_UPREV     adw_uprev fails and a typo in rule name
& V; V& ^$ a. |, o+ Q. }1673333 ADW                CONF          Configuration Manager stops working and gives Java Timer-1 Error1 r4 E- h/ G1 {7 J, j( [$ f, K
1900342 ADW                DBEDITOR      'Link To' on a schematic classification attribute does not work with linked attributes containing parenthesis
# a0 G6 g+ Y& Z0 a( }% ?+ T1997516 ADW                DBEDITOR      DBEditor stops responding on changing attributes& G) {% S; q5 T
1986292 ADW                LIBDISTRIBUTI Some parts are not updated in the part table in all_noauto and ini_noauto (restricted_sites).: W1 _  i$ ^2 t
2010460 ADW                PART_BROWSER  PKG-1002 error when opening a DE-HDL design. o/ F' H( E9 c1 [8 D4 Y7 a8 j: b' v
2013430 ADW                PART_BROWSER  Add component is inactive if WB_SHARED_RESOURCES is not pointing to the installation directory% q2 d# S8 S' D* X; ~
2022806 ADW                PART_BROWSER  PKG-10005: Cannot package the following primitive instance in any section of the physical part
7 F0 ?& C* W$ e  ~! B2006528 ADW                PART_MANAGER  Part Manager does not update parts when Key PTF property value changes2 p  F+ `# T! P$ H( I0 M% u; g
1980397 ALLEGRO_EDITOR     DATABASE      Mechanical pins with route keepouts (RKO) not updated/ X& E! g- P  ^7 P( x
1988171 ALLEGRO_EDITOR     DATABASE      Backdrill clearance Keepout is not applied consistently
( N  Z: F$ D; ~1994280 ALLEGRO_EDITOR     DFM           PCB Editor crashes during Unplace component
( Z) i) s$ \5 T0 k- u2012742 ALLEGRO_EDITOR     DFM           DFT for testpoint to outline not showing DRC
4 O) s3 B/ n$ Y/ P* D- Y  i: d$ ~2002680 ALLEGRO_EDITOR     EDIT_ETCH     PCB Editor crashes on choosing Add Connect for two selected nets
, F1 I9 t9 w8 L% }- v2004597 ALLEGRO_EDITOR     EDIT_ETCH     Illegal BMS Identifier error when copying multiple via structures) L. m% U' n7 q) I6 q: I7 E- }) b
2004929 ALLEGRO_EDITOR     EDIT_ETCH     Net with physical pin pair constraints is using incorrect line width when routed
; D+ _$ W& N/ N0 A- f- M' [2 p2 h2008314 ALLEGRO_EDITOR     EDIT_ETCH     Adding nets in tabbed routing crashes PCB Editor; F6 D3 i* P: P% F& G
2018710 ALLEGRO_EDITOR     GRAPHICS      Using the mouse to zoom by scrolling stops working randomly$ Q- v( q; @! j
2018841 ALLEGRO_EDITOR     GRAPHICS      Canvas does not regain mouse focus after working in the Options pane in hotfix 049( O9 O3 o+ O1 k3 u
2019482 ALLEGRO_EDITOR     GRAPHICS      Canvas does not regain mouse focus after working with the Options pane in hotfix 049 on Windows 7
/ B- T9 O  P, t# e2019864 ALLEGRO_EDITOR     GRAPHICS      Using the mouse scroll button to scroll the canvas: focus is in the Options pane! H2 v* a9 Q9 m/ j9 V9 I
2020750 ALLEGRO_EDITOR     GRAPHICS      Zoom in/Zoom out scroll does not work
& U: ?( X' j$ b9 i* }5 j: P2020847 ALLEGRO_EDITOR     GRAPHICS      Scroll up/down key focus remains in command screen even when canvas is selected$ Q6 z- a, @" R! z5 y3 w; v: Z/ A
1908812 ALLEGRO_EDITOR     INTERACTIV    Tools > Design Compare command does not work on Windows
( ]3 f/ X. u6 P% }1995846 ALLEGRO_EDITOR     INTERACTIV    When there is an embedded component, the result of Metal Usage report is incorrect.# u. S- L9 V" B7 I2 p
2011449 ALLEGRO_EDITOR     INTERACTIV    Command not found error (_impvision) for Impedance and Return Path DRC visions
/ ^# b2 R" A2 E3 M/ y- O! _" Q1982867 ALLEGRO_EDITOR     INTERFACES    DBDoctor displays error for objects outside extent that cannot be fixed because the extents cannot be increased' `7 f* C" F. ], G& ]# F2 m
1983177 ALLEGRO_EDITOR     INTERFACES    PCB Editor crashes when reading IDX file
4 q; X3 F2 h2 k. g$ H6 B1985623 ALLEGRO_EDITOR     INTERFACES    STEP model not exported from PCB Editor
/ ]5 b0 r! Z* C& ~$ p" z  o/ t1994855 ALLEGRO_EDITOR     MANUFACT      Drill legend with counter-bore: legend size not uniform when database set to inches1 E) W& X1 q+ `  ^. N; b$ v
2001355 ALLEGRO_EDITOR     NC            PCB Editor crashes with NC route parameter5 b: I  x! `: c) F  }  Z& A
1753414 ALLEGRO_EDITOR     OTHER         Ability to add Rigid Flex class in a format symbol
, y) U* n9 w6 r2 q2004786 ALLEGRO_EDITOR     OTHER         Legacy menu option missing in OrCAD Professional! Z0 D7 q- E" g; A
1949695 ALLEGRO_EDITOR     PADS_IN       Third-party to PCB Editor translation does not make a clean conversion, X& o! N# Y7 d- b
1949658 ALLEGRO_EDITOR     PLACEMENT     SKILL module creation issue: subsequent runs rotate module incorrectly
5 w4 V0 Y0 ?8 c- X" ~2001496 ALLEGRO_EDITOR     PLACEMENT     Constraint Region not replicated as part of the Place replicate apply command
& g' H: X& E7 E$ K4 D2002989 ALLEGRO_EDITOR     PLACEMENT     Default rotation point is set to 'User Pick', h% ?9 a1 \7 s. j& x1 C& Q1 x
2007301 ALLEGRO_EDITOR     PLACEMENT     DFA boundary is shifted when moving components with User Pick' D3 C) J% Q' ^, f. }3 Y+ a( @& z
2007312 ALLEGRO_EDITOR     PLACEMENT     DFA boundary is shifted when moving components with User Pick6 g- x" z8 ^8 S! t
2008098 ALLEGRO_EDITOR     PLACEMENT     DFA boundary shows a shift if anchor point is set to 'User pick'
% j0 P" H$ z; V! M" m2 C2009085 ALLEGRO_EDITOR     PLACEMENT     DFA boundary is shifted when moving components with User Pick
; ]; J" d& D; |( ?  s& j% ?. o' U2009090 ALLEGRO_EDITOR     PLACEMENT     DFA boundary is being offset when moving components with User Pick
) H+ `( |; u8 d4 f' ~/ u' K% H2009580 ALLEGRO_EDITOR     PLACEMENT     Component outline offsets during move process
; B; a$ ?4 f5 x* P5 T  m2010726 ALLEGRO_EDITOR     PLACEMENT     Two images appear when moving component in release 17.2-2016, hotfix 048: M) S: t; q  O1 M; G  a7 P2 Y$ C
2010819 ALLEGRO_EDITOR     PLACEMENT     A separate outline appears when moving components using User Pick
! P- }: R& y7 }3 H9 @& F  w7 {2011454 ALLEGRO_EDITOR     PLACEMENT     DFA boundary is not centered correctly on moving components! w* J( H. `2 E  e
2011497 ALLEGRO_EDITOR     PLACEMENT     DFA boundary shifted from the part when moved8 E# b+ N- \: z" ^$ s0 Z2 J
2014250 ALLEGRO_EDITOR     PLACEMENT     Moving a symbol using the 'User Pick' causing an offset image of the symbol outline getting attached to cursor# r4 Y$ w2 }1 v5 Q1 R
2015676 ALLEGRO_EDITOR     PLACEMENT     Strange end-to-end DFA checking: offset of DFA from component when in user pick
: p+ S6 B8 A* D' H& |" V2016421 ALLEGRO_EDITOR     PLACEMENT     Fail to place symbols because definition is incompatible for attribute 'PW_GENERATED'
8 P0 w! R. N, r0 \3 Q7 r2016452 ALLEGRO_EDITOR     PLACEMENT     Some symbols cannot be placed due to property definition differences4 p9 @% _  r: h- w
2016527 ALLEGRO_EDITOR     PLACEMENT     PCB Editor crashes on moving all components on board# W& A# o/ A# L& g4 v# }) j
2017364 ALLEGRO_EDITOR     PLACEMENT     Strange behavior when moving component: DFA or place bound area is centered around the User Pick position) x8 _( {' ~9 _$ G. R, p! u2 ?
2018859 ALLEGRO_EDITOR     PLACEMENT     Moving parts by 'User Pick' or 'Sym Pin #' shows two component placement boundary outlines
6 x' `& D: @" W2019364 ALLEGRO_EDITOR     PLACEMENT     PCB Editor stops responding when moving components
, d% d0 r4 `+ L- O' C2019478 ALLEGRO_EDITOR     PLACEMENT     PCB Editor crashes when moving more than one component across the design
; S9 O+ z2 s3 q2019624 ALLEGRO_EDITOR     PLACEMENT     DFA Boundary is offset from definition when moving symbols with user pick: U% {6 m: i: d% u. a
2021625 ALLEGRO_EDITOR     PLACEMENT     Graphical Issue with Edit - Move and User Pick: additional outline image shown
- v5 g. x! q7 }/ v3 B0 c& O2022203 ALLEGRO_EDITOR     PLACEMENT     Place bound outline is shown at the center of the pick when moving a part by User Pick
% V- s! R: K% t2024655 ALLEGRO_EDITOR     PLACEMENT     Moving multiple components causes PCB Editor to crash
/ I9 Y7 p: I3 S3 w4 y2025895 ALLEGRO_EDITOR     PLACEMENT     PCB Editor stops responding when multiple symbols are moved and on getting too close to another symbol3 P8 h. ]0 }( _# j+ X
2004497 ALLEGRO_EDITOR     SHAPE         Automatically deleting antenna shape is not deleting thermal reliefs associated with those shapes
3 N0 C4 o) h/ d+ C; H, ?0 w2007832 ALLEGRO_EDITOR     SHAPE         Cannot void shape properly after rotating symbol
; A! j% }. H; [. @2009601 ALLEGRO_EDITOR     SHAPE         Error for shape created using third-party SKILL utility6 t5 @9 c; y( u
2010924 ALLEGRO_EDITOR     SHAPE         Dynamic shape does not void in route keepout areas; D* H6 D2 g! X: K( y3 L: O3 Y
2011176 ALLEGRO_EDITOR     SHAPE         Nothing happens on choosing 'Shape- - Change Shape Type' in Allegro Sigrity SI0 B" @1 }1 @& S$ s
2015446 ALLEGRO_EDITOR     SHAPE         Thermal relief connection created for static shape covering pin when inside a void in a dynamic shape.
0 `9 ]6 K0 D2 ?( @( E( P2017273 ALLEGRO_EDITOR     SHAPE         Same net spacing does not void properly for shape to hole.
) q9 v4 N! v- b! N. V. O6 N2012878 ALLEGRO_EDITOR     UI_FORMS      Custom toolbars cannot be loaded as size differs for customState and customExteded in registry
; k- X, T# Z2 K4 h) U6 a2018177 ALLEGRO_EDITOR     UI_FORMS      Custom toolbars cannot be loaded as size differs for customState and customExteded in registry
+ \3 k- _  x$ v2019437 ALLEGRO_EDITOR     UI_FORMS      Custom toolbars cannot be loaded as size differs for customState and customExteded in registry
8 }& m6 R* m" f* s( D3 t, I2020491 ALLEGRO_EDITOR     UI_FORMS      Cannot load custom toolbars because the customState and customExtended Windows Registry entries are incorrect2 d4 y1 E( D; M2 g9 ?
1897843 ALLEGRO_EDITOR     UI_GENERAL    Function Keys, such as F3, F6, and F7, are not working if tool is idle for some time: w9 B, I0 R- D6 u; U
2000445 ALLEGRO_EDITOR     UI_GENERAL    Funckeys not working in hotfix 048 with the new Command Pane as default
6 _% z6 [8 A( C4 m' {/ \. ^2001847 ALLEGRO_EDITOR     UI_GENERAL    Ctrl related funckeys not working in hotfix 048# O! a! i' X$ c) B4 l
2008112 ALLEGRO_EDITOR     UI_GENERAL    Funckeys using Ctrl and Shift do not work in hotfix 048 (QIR 7)
7 A3 q. ]7 X, i2010370 ALLEGRO_EDITOR     UI_GENERAL    Shift + arrow key does not move component in release 17.2-2016, hotfix 048  s: |$ p+ X1 i
2015418 ALLEGRO_EDITOR     UI_GENERAL    Funckey not working* [, W* Z/ f! y9 Z0 M( [
2015443 ALLEGRO_EDITOR     UI_GENERAL    Text does not regain focus even on clicking after using a drop-down menu- B) C/ G* ?- J% q8 d9 w% k% J
2016899 ALLEGRO_EDITOR     UI_GENERAL    Dynamic zoom and funckeys are disabled after clicking a combo box in the Options pane  X" K7 H9 V. v. `
2019753 ALLEGRO_EDITOR     UI_GENERAL    Infinite Cursor disappears regularly in hotfix 049 when infinite_cursor_bug_nt is set
6 N% V& d6 J0 }' q% K, ~6 H2019990 ALLEGRO_EDITOR     UI_GENERAL    Mouse over does not highlight pin, need to click
0 Q0 p$ A' V# U9 o8 j( l8 x; D2020162 ALLEGRO_EDITOR     UI_GENERAL    Funckeys not working in hotfix 049: pressing F4 not running Show Element1 ]. R7 g3 E+ g/ V+ k5 m
2020168 ALLEGRO_EDITOR     UI_GENERAL    Data tips not shown on mouse hover7 ~$ `; Y# k1 Y( P& N9 e
2020840 ALLEGRO_EDITOR     UI_GENERAL    Page-up/Page-down (remapped to zoom-in/zoom-out) stop working until mouse scroll button is pressed
2 K5 u! [/ h2 C) ?, q0 \/ H9 s& r2021416 ALLEGRO_EDITOR     UI_GENERAL    New user interface does not shift input focus and zoom in/out does no longer work in layout window" H/ K8 |& }; j+ t3 ~# \7 T! t
2022185 ALLEGRO_EDITOR     UI_GENERAL    Ctrl related funckeys are not working0 l9 M5 C+ V: b) ^# Q; g
2023402 ALLEGRO_EDITOR     UI_GENERAL    During Add text, focus does not move from the subclass dropdown to the canvas.$ v$ ]( a/ ^2 H% E' L
2025806 ALLEGRO_EDITOR     UI_GENERAL    Function keys and shortcuts not detected7 @9 [* |9 a+ e& A9 H
2027581 ALLEGRO_EDITOR     UI_GENERAL    Funckey problem: focus lost from canvas on using another window+ k$ H; w1 q: a% Q
2009382 ALLEGRO_EDITOR     ZONES         When deleting zone by Zones - Manage, the shape in zone is out-of-date
: n9 |: ?0 v0 Q# [4 a7 l1977211 APD                DXF_IF        APD: die pads shift after export DXF
# ]/ ]) p" R9 o6 S% h2018483 CAPTURE            NETLISTS      Error when extracting netlist from schematic (ORNET-1193)
  }# z( h$ \; I. T& `2022764 CAPTURE            NETLISTS      Schematic will not generate pstchip.dat file
, _0 E8 s% ?+ c" p1921557 CAPTURE            NEW_SYM_EDITO Zoom to region option grayed out3 D/ O8 b1 l0 V3 \2 T, X
1945203 CAPTURE            NEW_SYM_EDITO Symbol Editor: No Zoom to Region and cannot edit Pin Type and User Pin Properties for multiple pins2 E: @7 L0 q. d+ `% w
1950178 CAPTURE            NEW_SYM_EDITO Ability to remove convert view of a component4 ^1 C! q+ l, ~0 V- O* O6 B
1966792 CAPTURE            NEW_SYM_EDITO JavaScript error on trying to edit pin name for GP0  X0 s2 M9 d$ F; m% ^" e
1969099 CAPTURE            NEW_SYM_EDITO Cannot add convert view after creating a part
0 w. m4 T$ G! `0 ~3 E# \1969834 CAPTURE            NEW_SYM_EDITO Shapes not mirrored around center if more than one shape selected in Symbol Editor
0 I$ B% z9 B9 X9 b* `/ u* R1970984 CAPTURE            NEW_SYM_EDITO New part is getting Numeric Numbering automatically0 r6 \% Z5 k3 W+ Q9 b
1972607 CAPTURE            NEW_SYM_EDITO New Symbol Editor: name cannot be edited unless value is entered for a new property& ~+ f0 V3 P2 o- N) u2 G5 ~
1972635 CAPTURE            NEW_SYM_EDITO New Symbol Editor: wrong listing of Symbol Properties in right pane1 J# L$ C+ q; h' g7 \# D9 a7 |
1974296 CAPTURE            NEW_SYM_EDITO Design Template font settings are not being honored for new library/part creation/ E' R. z3 c  G1 A. ^
1982783 CAPTURE            NEW_SYM_EDITO Part Editor is blurry when zoomed out.' q6 ]1 w$ r% M( g
1993361 CAPTURE            NEW_SYM_EDITO Cannot change part numbering, set to Numeric by default3 Y9 A: Z. \$ k( X( i. ^7 h* V
2003749 CAPTURE            NEW_SYM_EDITO Cannot save edits to hierarchical blocks in new Symbol Editor in hotfix 048
& ^4 \2 X" z$ |% n9 p2004395 CAPTURE            NEW_SYM_EDITO 'Pin ignore' modifications not saved in new Symbol Editor 'Edit Pins' after hotfix 0481 B. D; c' `$ x& E0 b
2007747 CAPTURE            NEW_SYM_EDITO Cannot add Convert View after creating a part! @6 f  h' c! b
2011321 CAPTURE            NEW_SYM_EDITO 'Place - Picture' is not working for blocks in hotfix 048
# i) b3 z4 V+ c  q5 b2 y2013146 CAPTURE            NEW_SYM_EDITO 'Part Edit' not updating changes in hierarchical block
5 }9 ]2 H6 I4 b  Z2002904 CAPTURE            OTHER         Unable to check out Capture license in release 17.2-2016, HotFix 048" V4 D" z+ S5 Z- T) P
2002922 CAPTURE            OTHER         Unable to check out Capture license in release 17.2-2016, HotFix 048- c( g% l+ q5 F. i0 _
1988812 CAPTURE            PART_EDITOR   Parts created or edited with hotfix 038 Part editor do not use default font size
/ _( X' U' A$ c  c2008912 CAPTURE            SCHEMATIC_EDI Design Compare shows 'NaN' in the graphical output6 o0 g) U# [" O6 y+ S3 D2 d
1985701 CONCEPT_HDL        CHECKPLUS     Library symbols are missing from the examples folder
& {! a7 D' @. Q1933789 CONCEPT_HDL        CORE          honor_sch_custom_texts
  e% _7 k- M: t4 W1933892 CONCEPT_HDL        CORE          HONOR_SCH_CUSTOM_TEXTS% w0 f0 S/ [8 N& ^2 N9 v
2001737 CONCEPT_HDL        PDF           DE-HDL crashes on choosing File - Publish PDF$ P4 c9 x; F6 z. K% H2 M
2010508 CONSTRAINT_MGR     CONCEPT_HDL   Schematic data corrupted on reading the data from CM database using the CM SKILL APIs
( w, k9 h* k1 e) M0 L$ D1997461 PSPICE             AA_FLOW       'Edit PSpice Model' from 'Assign Tolerance' window does not work: s% e* g, _2 B9 ~, j& G& c2 W
2005948 SIP_LAYOUT         DIE_EDITOR    CTE expansion tool shifts pins off the die
. G* i, E; h, Z( v# I; M1893045 SIP_LAYOUT         INTERACTIVE   Refreshing bond finger labels causes all the labels to shift location4 k6 P5 |- z5 b) Q  ~" s0 C" U
2006926 SIP_LAYOUT         ORBITIO_IF    Bundle translation from OrbitIO is incorrect* H& u+ g! n8 U- T9 v3 i
2006659 SIP_LAYOUT         SHAPE         Cannot form fillets inside a shape in hotfix 048# o# G1 s  C* {* s5 @  W4 G
1969192 SYSTEM_CAPTURE     CANVAS_EDIT   Pin Numbers of Discrete Symbols visible0 C$ b& o' e9 r; |5 y
1982368 SYSTEM_CAPTURE     CANVAS_EDIT   System Capture switches to Auto Pan, even if the option is disabled, in the Notes mode
+ c  _5 W  s  E7 [8 `. K6 I1995012 SYSTEM_CAPTURE     CANVAS_EDIT   Connect lines do not move with components. M  C/ }0 y4 q& t' ?$ }$ D5 ^
1907992 SYSTEM_CAPTURE     CONNECTIVITY_ Draw stubs is not respecting stub length setting.3 |9 K, i( a* ?
1960100 SYSTEM_CAPTURE     CONNECTIVITY_ Moving components after routing failure:  connect lines do not move resulting in disconnected route) g1 [0 a6 p, f" o$ ?) c. V
1988284 SYSTEM_CAPTURE     CONSTRAINT_MA Log files and topology files are being stored at the top-level design (CPM) folder level
+ T; G. U6 H+ f1996039 SYSTEM_CAPTURE     COPY_PASTE    Cut and Paste change the pin numbers for connector after saving design.
; V( D. D. \, K- S7 `. L1951700 SYSTEM_CAPTURE     EXPORT_PCB    System Capture: Export Physical - Change Directory UI entry block not displaying properly& V8 V( k# K( H' D; X+ F
1970761 SYSTEM_CAPTURE     EXPORT_PCB    Cannot import System Capture netlist if PCB Editor is launched with -proj argument3 z8 r4 b& d/ s+ r, t% R3 U. P
1997533 SYSTEM_CAPTURE     IMPORT_PCB    Pins do not swap in System Capture on backannotation
( ~% M( K* L5 j1 I  i0 e1910962 SYSTEM_CAPTURE     MISCELLANEOUS Dragging GND symbol placed on a pin sometimes disconnects the GND symbol
/ l: _. u/ G9 x. B( X( e& w1962037 SYSTEM_CAPTURE     TABLE_OF_CONT Table of content link number not same as page number in the title block$ i3 v9 r* d- G: v! U
1986317 TDA                SHAREPOINT    Cannot enable Design Management and SSO session expires$ a, r: l0 I. F/ h+ I/ l

0 s; D# G& ^$ T$ f
( y+ E/ o* Q. \$ P! XFixed CCRs: SPB 17.2 HF049# d3 X, ~5 I+ o. s" s
11-16-2018* f, \' I8 k4 G# S) Q
========================================================================================================================================================; c$ o# p  A0 x7 c& P5 \& ?
CCRID   Product            ProductLevel2 Title
8 k: P# R$ i, Q, s; o9 l========================================================================================================================================================
6 y" B1 u0 \( r$ x2002642 ADW                ADWSERVER     Exception in adwserver.out with LDAP enabled6 x" I8 S9 R! Z
2007046 ADW                ADWSERVER     Component Browser is not connecting to server in hotfix 0488 u: _0 y3 P- b7 h2 @
1997678 ADW                DBEDITOR      Model not deleted due to missing cell model relation8 A! r. [7 ~. p; `
1985059 ADW                FLOW_MGR      Flow Manager issues warning about project path that contains a period, removes from catalog file
% A3 v: {4 |# F0 q1991515 ADW                FLOW_MGR      Flow Specific Tools: Launch error after upgrading to Hotfix 044 and extending code; |8 z* k7 f" ]+ q: d
1972762 ADW                PART_BROWSER  The Schematic Models icon does not match the definition in EDM Component Browser
4 ?" ~4 s+ p( T$ G; f: ^6 ]' X; h! y1830062 ALLEGRO_EDITOR     DATABASE      Uprevving release 14.0 design with stand-alone DBDoctor in release 17.2-2016 crashes; works in release 16.6
) L8 ?7 Y/ g: H) E% ]' E1980161 ALLEGRO_EDITOR     DATABASE      NODRC_ETCH_OUTSIDE_KEEPIN assigned to text in library part is not passed to PCB Editor
8 U5 D7 J; O+ C% ?2003757 ALLEGRO_EDITOR     DATABASE      Open circuit not detected by PCB Editor: reports unconnected pin as connected
) p5 i1 h, B& q3 [" b) v2009748 ALLEGRO_EDITOR     DFM           PCB Editor crashes on Update DRC
+ [8 C. m, f' K1796895 ALLEGRO_EDITOR     DRC_CONSTR    Increase precision of Inter Layer Spacing check! N. e! y' y) r* @( @  _' b
1997487 ALLEGRO_EDITOR     DRC_CONSTR    Cannot add teardrops to some pins: d& }8 T6 k# D
1857024 ALLEGRO_EDITOR     EDIT_ETCH     PCB Editor crashes on using funckey 'y FORM mini padstack_list -+'
% n  |8 d! m0 u0 N5 z2 {/ u. C4 a3 `1979750 ALLEGRO_EDITOR     INTERFACES    axlStepSet not working for component definitions
3 \' E% i5 f  E& X; W8 _$ s1988168 ALLEGRO_EDITOR     MANUFACT      Graphical Compare in productivity toolbox terminates with errors/ @2 n8 G: I; \5 q  C
1982233 ALLEGRO_EDITOR     SCHEM_FTB     Netlist files cannot be imported into board as the process is not finishing" A' z3 Q" N) X  P$ B+ v7 d% J
2000367 ALLEGRO_EDITOR     SCHEM_FTB     Cross-probing between OrCAD Capture and PCB Editor does not work in HotFix 048
* F( x9 q9 ^. n( B# u( D2000397 ALLEGRO_EDITOR     SCHEM_FTB     Cross-probing not working with hotfix 048
  s! }0 j1 J# H2000552 ALLEGRO_EDITOR     SCHEM_FTB     Cross-probing is not working if we are importing Netlist from PCB Editor
6 O- B+ r; _1 o/ F2001165 ALLEGRO_EDITOR     SCHEM_FTB     Cross-probing between Capture - Allegro PCB Editor fails after hotfix 048
# j$ M; t: {' k) P" R; g2002635 ALLEGRO_EDITOR     SCHEM_FTB     Cross-probing issue because of Unique MPS Session in HotFix 048 (QIR7)
9 `4 U! k* s1 E  o) ~0 T4 S; _- {2004252 ALLEGRO_EDITOR     SCHEM_FTB     Cannot do cross-probing between Capture and PCB Editor8 P* R& D) v1 P
2004305 ALLEGRO_EDITOR     SCHEM_FTB     Inter-tool communication is not working properly in PCB Editor release 17.2-2016, hotfix 048/ k0 O" T1 [4 c' h" S
1978660 ALLEGRO_EDITOR     SHAPE         Static shape on dynamic shape issue: thermals not removed when component is moved
' e) `* d1 ]2 Q! q- {1985035 ALLEGRO_EDITOR     SHAPE         Thermal reliefs not removed on moving parts8 Z4 F$ f1 C0 |+ W7 h: ^  ^
1960966 ALLEGRO_EDITOR     SKILL         Stackup import is not working in release 17.2-2016 via automation% p! @4 s  T9 t1 P2 M) m
2003651 ALLEGRO_EDITOR     UI_FORMS      Error on starting and loading footprints in hotfix 048: message about customExtended and customState7 C6 g1 K; a( P; ^& E& R
2003810 ALLEGRO_EDITOR     UI_FORMS      OrCAD layout editor font size is too small for almost all UI( g, Z2 v2 C* h( l; M8 ~
2003832 ALLEGRO_EDITOR     UI_FORMS      Error on loading footprint in hotfix 048: custom toolbar cannot be loaded due to registry problem
4 u( y' G8 J4 T( Z2004769 ALLEGRO_EDITOR     UI_FORMS      Custom toolbars cannot be loaded as the size of customState and customExtended differs in registry- M) A+ H+ D4 e% A: ~2 s
2007669 ALLEGRO_EDITOR     UI_FORMS      Broken scalability between OrCAD PCB Editor and Allegro PCB Editor4 ]) p2 P3 ?- B/ F" K# i1 S
1987164 ALLEGRO_EDITOR     UI_GENERAL    PCB Editor stops responding when multiple sessions are accessing third-party tool% @3 }) r# G  N- j/ l0 Z
1983512 ALLEGRO_PROD_TOOLB CORE          Allegro Productivity toolbox: Advanced Testpoint Check is not working9 S5 P/ l, _* c
1996008 APD                3D_CANVAS     New 3D Canvas does not work in APD
5 J/ R  V2 m1 a$ f2 i; u" P# b1993698 APD                SHAPE         APD stops responding and database is corrupted on moving, deleting, or updating a symbol
/ V; K  Q* m4 ~# Y1999446 CAPTURE            OTHER         Update symbol database in Trial3 r/ X" f- {8 [" K
1962222 CONCEPT_HDL        CORE          Nested hierarchy block RefDes transfer issue: suffix added to RefDes+ N0 }2 ^) U2 j; Q2 X+ N0 Z
1964260 CONCEPT_HDL        CORE          RefDes not updated in a hierarchy block on repackaging release 16.6 design' P" w. C, H2 E# X2 n' i
1972243 CONCEPT_HDL        CORE          Version filter does not work correctly
1 H) W# b4 O) Y1993448 CONSTRAINT_MGR     DATABASE      CSet is duplicated with same name when modified in SigXplorer
0 H3 P2 p/ ^" h4 y( T1976148 CONSTRAINT_MGR     INTERACTIV    DRC worksheet in Allegro PCB Editor: 'Go to Source' flickers worksheet and does not switch
- ?# B- s: ?5 r/ n7 b! R1948372 CONSTRAINT_MGR     UI_FORMS      cmDiffUtility fails to compare and gives the message 'Failed to read the configuration file') i1 P- {2 |: A9 A
1961750 EAGLE_TRANSLATOR   PCB_EDITOR    Voids and some shapes of third-party board not translated correctly+ w, _( ?, q3 B* X- n1 j" s( c
1984569 FSP                DECAP         When a pin function is in an interface or custom connector is changed, decaps defined for the part is deleted
, g2 S  r% @" x, `1984588 FSP                DECAP         FSP crashes when changing pin functions or bank settings for a connector
9 D1 a% j/ x/ k" g8 G0 W/ K' ]1984590 FSP                DECAP         FSP design fails to load if pins are defined with a pin function that is later changed in custom_connector.crf5 i9 q' r% n  }3 j, ]7 H+ e; _3 H
1985555 PCB_LIBRARIAN      IMPORT_EXPORT JavaScript exceptions on opening libraries converted using con2cap
* x0 _7 ~4 y$ s* `1961944 PCB_LIBRARIAN      SYMBOL_EDITOR Hide symbol outline in new Symbol Editor
. M0 ?- h' y7 u* L" O6 t6 v7 `1967532 PCB_LIBRARIAN      VERIFICATION  libimport fails with ERROR(SPDWPAR-102): Metadata has the ErrorStatus value set.
# t5 D* r& a6 i! u" i( G1976965 PSPICE             SIMULATOR     PSpice 'Tools - Generate Report' not working in release 17.2-20164 l3 @4 D* c7 z  {2 F" V0 X
1982260 RF_PCB             FE_IFF_IMPORT Unable to successfully pull in .IFF file created in ADS.
% L* Y5 ^6 E% {1981585 RF_PCB             LIBRARY       Cannot load RF symbol via2 into PCB Editor
8 j' `9 ^- W+ z3 _; N, ~% r1976845 SIG_EXPLORER       OTHER         CPW trace models do not solve in SigXplorer after changing some trace parameters( o! H9 b. i1 k7 E' c
1986466 SIG_INTEGRITY      OTHER         Delay in Relative Propagation Delay worksheet is displayed as a negative value- h7 G5 c3 ~" K, P* o
1980264 SIP_LAYOUT         INTERACTIVE   SiP Layout crashes on running 'Manufacture - Documentation - Display Pin Text'3 u# U  p/ q7 w& ^0 E  m0 c
1983381 SIP_LAYOUT         REPORTS       Incomplete Design Summary Report
8 u2 Y/ p9 H6 ?/ K0 O3 c, k; \2005709 SIP_LAYOUT         SHAPE         Dynamic shape voiding around same net cline segment: no property attached6 A) s; ?/ t  i$ B( {* R( F9 j. {# _
2008064 SIP_LAYOUT         SHAPE         Hotfix 048 (QIR 7): Shape creates void for same net cline, it should be shorted1 p+ U6 ~/ Y. H( B( E; E! ]! \
1980967 SYSTEM_CAPTURE     CANVAS_EDIT   System Capture does not reflect part symbol changes7 e5 {4 y& x# m
1988928 SYSTEM_CAPTURE     CANVAS_EDIT   Changing version 2 of the resistor part makes the PART_NUMBER property visible
2 ~8 t" E2 _: W% D1990215 SYSTEM_CAPTURE     CANVAS_EDIT   Draw Multiple Bits: Bits do not follow mouse smoothly
/ J& w' }& L# {  k1972658 SYSTEM_CAPTURE     EXPORT_PCB    Modified injected properties do not get updated in the pstchip.dat file after running Part Manager and Export Physical$ M) w& ?# k+ p/ k1 I
1989421 SYSTEM_CAPTURE     EXPORT_PCB    Part Manager does not update the PTF values
( K: A5 ]# ~, }% Z, Y$ V! o& s1992407 SYSTEM_CAPTURE     PART_MANAGER  Part Manager removes part properties and main window and details window updates are inconsistent1 E7 B+ v7 v& Q' ]% @  I

& b: R" \& [5 P2 Z( q
2 ?# E5 n0 q+ V' P7 \. J( C  aFixed CCRs: SPB 17.2 HF048
. h- y# d/ `  \) R/ n6 M( ?10-13-2018
/ |4 l" ^3 Q9 e. ~- A% \% c========================================================================================================================================================9 ^  _9 C0 l. s, t
CCRID   Product            ProductLevel2 Title- {( E& G0 _# P% F, a4 n
========================================================================================================================================================
% C3 ]1 E/ q/ [: t2 C8 C  G& R1913039 ADW                ADWSERVER     EDM Library Server exits with error message on starting library server service& z% A& e% o$ G2 K; h
1709155 ADW                COMPONENT_BRO Search query does not search for all the parts in the library
4 d1 n& [' S; c3 Z3 _6 X; ?$ E- |1827231 ADW                COMPONENT_BRO Clicking the 'a' key in Part Manager launched from DE-HDL crashes DE-HDL
( W1 [7 p# X, A1903818 ADW                COMPONENT_BRO Parts that have comment_body do not display version
1 d, K; a9 e  O1917961 ADW                COMPONENT_BRO Component Browser PPL column values are truncated when selecting the top '*' filter5 i" ~; z) j# Q# R% k2 s$ X% h) Q
1938172 ADW                COMPONENT_BRO Symbol version with COMMENT_BODY set to TRUE cannot be instantiated
( x6 W0 \/ U+ H* ^0 U1914103 ADW                CONF          conf creates incorrect path in fetch_dump.ini when MLR is enabled.$ Q& s7 `7 L. K! z. A
1911422 ADW                DBADMIN       RuleP101 - PACK_TYPE check against schematic model not working% U0 C  Z6 h. u, J* G
1926691 ADW                DBEDITOR      Adding a new classification and immediately trying to delete it results in errors
+ S$ `* F4 F7 |! T4 V2 f$ _1926694 ADW                DBEDITOR      Renaming a classification and then renaming it back to the original results in error2 A2 j7 k3 Q7 b5 W* F  v$ b+ l
1934870 ADW                DBEDITOR      Adding a new classification and immediately trying to delete it results in errors: y: ?; u6 x' u! U9 |  W
1872387 ADW                DSN_MIGRATION Design Migration does not cache all used parts into flatlib/part_table.ptf; O3 ]$ ^; b- r- }' v
1254292 ADW                FLOW_MGR      Flow Manager Open Last Project should open last project closed
& X  L4 ^1 u# r5 g1281817 ADW                FLOW_MGR      '-proj' switch in 'pcbdw_fm' does not work; launches Flow Manager without loading any project6 ~; l+ i8 d/ D' L# h) M! a, F
1727286 ADW                FLOW_MGR      Product options for PCB SI and Power Integrity are incorrect in the flow and tool launchers
' Y2 ]% j6 y( A6 f1875498 ADW                FLOW_MGR      EDM fails to open or becomes unresponsive.
/ x+ W) |+ O" c0 f1879386 ADW                FLOW_MGR      Unable to access COS with the default Firefox version in the 17.2 installation, ~& D& S9 G0 E' j
1922541 ADW                FLOW_MGR      Warning message for unavailability of Java version appears on opening a project on Linux
" |; Z: c' Y3 s2 z8 g1945451 ADW                FLOW_MGR      Checklist does not work with two-byte characters
6 C0 g3 {/ d& m: r% Z1956213 ADW                FLOW_MGR      Not able to invoke Flow Manager on the remote system
8 J' C) B# L8 W1892285 ADW                LIBDISTRIBUTI Symbol not consistently available in 16.6 ADW Library
4 z# z% g# ]- f* H1961731 ADW                LIBIMPORT     libimport fails to create tar for two Capture models
+ |! O8 V& K$ E( e/ @6 D1836620 ADW                LRM           Library Revision Manager crashes on clicking Help
( M1 l' ?; t* |1961845 ADW                PART_BROWSER  Error regarding environment variable2 P, q; h% ~8 R- O( K4 m
1890782 ADW                TDA           Launching TDO dashboard connected to PLM returns a license error
& ^+ _1 H" c" f: M% T. e1 }1980914 ADW                TDA           Cannot start Design Entry HDL and Component Browser in a TDO design7 a+ s# B2 s  X
1833750 ALLEGRO_EDITOR     3D_CANVAS     Soldermask Text is not shown in 3D Canvas! A' C) ~. c* ?) t# \
1891230 ALLEGRO_EDITOR     3D_CANVAS     3D Canvas Viewer not bending PCB with proper radius) @- Q6 Q* h$ x! ^3 V
1913338 ALLEGRO_EDITOR     3D_CANVAS     STEP models missing from exported .stp file
) H" y; J/ J- M3 b( U3 f1927507 ALLEGRO_EDITOR     3D_CANVAS     Get Error: All bend operations are disabled due to licensing and/or DLL installation issues on invoking 3D Canvas% `! A; Q3 X$ w* M
1931508 ALLEGRO_EDITOR     3D_CANVAS     Place Bound Bottom is displayed on Top, when dra is opened in 3D Canvas
8 f; k$ p9 c7 q# G4 \/ |1943060 ALLEGRO_EDITOR     3D_CANVAS     Placebound bottom is not showing correctly.
, r  g, ?; t8 c  Z1950099 ALLEGRO_EDITOR     3D_CANVAS     Place Bound Bottom is displayed on Top, when dra is opened in 3D Canvas4 A! }3 F$ H6 p. ?* ]/ m4 T$ R' {
1988307 ALLEGRO_EDITOR     3D_CANVAS     3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation
' C. `  @4 z- x  O+ [1923585 ALLEGRO_EDITOR     ARTWORK       Additional unwanted subclasses appear in film control when a new film definition is added
: c) N' j; C4 ]) S9 n  m# `5 N+ i1944079 ALLEGRO_EDITOR     COLOR         Export of Board Parameters (Net Colors) does not contain entries for nets with spaces
, Z$ J2 w. }+ u1856320 ALLEGRO_EDITOR     DATABASE      Donut pad fails to connect with cross-hatched shape in full contact thermal mode, despite hatch overlap of donut.
# p2 ~  i# _7 x. B& P" z. p; K) I* A1912313 ALLEGRO_EDITOR     DATABASE      Database corrupted during background process
& q2 W# h! z% \1913344 ALLEGRO_EDITOR     DATABASE      When changing accuracy of design, the thermal relief for donut pad's outer pad connects to inner pad
- A- G: u; d( d3 c. h+ i4 F: ~1914470 ALLEGRO_EDITOR     DATABASE      Release 17.2-2016: export libraries command does not inherit posi/nega information
2 K$ R8 c- V4 A1 l( X7 b$ h. z: v1932086 ALLEGRO_EDITOR     DATABASE      Unable to resolve DBDoctor error/ }# p9 }, Q' I' g
1963932 ALLEGRO_EDITOR     DATABASE      DB Doctor is not recognizing placed parts and showing them as unplaced.8 f& P* I& ?' V9 H+ u! M% G7 `
1987735 ALLEGRO_EDITOR     DATABASE      Interior sub-lamination backdrill holes are displayed with Top Soldermask pads where backdrill does not exist
- g6 o' r  G( A6 _1977622 ALLEGRO_EDITOR     DFM           Not able to add value '5' or multiples of 5 in in DFF constraints for maximum stacked via count
' |- B, i- i6 V9 x3 U' [! C- u6 r1892809 ALLEGRO_EDITOR     DRC_CONSTR    NODRC_ETCH_OUTSIDE_KEEPIN property is not working on TEXT
- p2 f" _" ?6 f0 A. j6 n4 U* M; y1894765 ALLEGRO_EDITOR     DRC_CONSTR    DRC for no_drc_component_board_overlap is not created if the place bound is outside Place Keepin1 S( J9 a' P. o% h: w: }
1896627 ALLEGRO_EDITOR     DRC_CONSTR    Moving components takes long time while doing placement( n) v* ]7 _& o, @5 {1 [
1914591 ALLEGRO_EDITOR     DRC_CONSTR    Spacing constraints for Mechanical to Hole shows resolved constraints different from the actual air-gap/space
3 \8 t/ G3 M, X" N% e3 t1956468 ALLEGRO_EDITOR     DRC_CONSTR    DRC getting generated while moving the uvia and getting removed after updating DRC.- X  h7 Z; @0 F6 `! g; W
1884149 ALLEGRO_EDITOR     EDIT_ETCH     Arced Routing of differential pair creates unexpected arc radii* }* Z4 C& a8 |2 [
1891985 ALLEGRO_EDITOR     EDIT_ETCH     Etch edit does not follow the constraints
  ~, _, z2 K6 M4 q# G1860056 ALLEGRO_EDITOR     GRAPHICS      PCB Editor crashes on right-click after choosing the Move command" ?* P$ t2 P( B, X
1860723 ALLEGRO_EDITOR     GRAPHICS      APD crashes on right-click when using the Move command
# i  o, z4 E3 ~+ h1870058 ALLEGRO_EDITOR     GRAPHICS      PCB Editor crashes when using Place Manual -H command
( L! m0 ?* X# F; s1930282 ALLEGRO_EDITOR     GRAPHICS      PCB Editor crashes on executing axlVisibleDesign(nil) from allegro.ilinit$ a  G! T- e8 s, T0 w
1882813 ALLEGRO_EDITOR     INTERACTIV    Unable to set the end point with 'snap pick to' when adding an arc( q+ ]3 \3 a( g9 _& }8 j
1884725 ALLEGRO_EDITOR     INTERACTIV    Edit and Move vertex operation not working as desired  F% W5 B3 K3 q# T
1902359 ALLEGRO_EDITOR     INTERACTIV    Connector boundary remains ON for a layer if visibility toggles in Shape Edit application mode
  o6 V! L0 w) T* a( A1909004 ALLEGRO_EDITOR     INTERACTIV    Parameter description showing wrong for Padless Holes under Design Parameter Editor3 L* M7 w% k5 v# u$ {9 L
1912055 ALLEGRO_EDITOR     INTERACTIV    PCB Editor crashes on Delete By Query - AutoSilkscreen - Find By Query2 v( N# X' P4 d# `  N7 u7 j2 k
1924503 ALLEGRO_EDITOR     INTERACTIV    Editing shape causes PCB Editor to crash5 K' O; R* d% Q' e& m0 D
1929614 ALLEGRO_EDITOR     INTERACTIV    Unable to Place Via Array when Staggered ring is selected in Global Ring Parameters.* [% G$ ~% _3 U( G4 H1 b2 U" a( g
1938523 ALLEGRO_EDITOR     INTERACTIV    Change Shape Type message is same for dynamic and static shapes
" ]- J2 t6 ~9 i8 G( \1940827 ALLEGRO_EDITOR     INTERACTIV    Irrelevant/incorrect warning message when doing Edit- Change on Clines2 n9 r  [7 ~$ i+ ~7 j: n$ c2 A' N& f
1872653 ALLEGRO_EDITOR     INTERFACES    DXF export shows embedded layers in the layer configuration file3 ~  y& @1 E" D+ W4 I- J
1873971 ALLEGRO_EDITOR     INTERFACES    IDX proposal comments are not shown when importing the IDX file into Allegro
! S; @) P2 ^" w( r; s5 ~1892172 ALLEGRO_EDITOR     INTERFACES    STEP Package Mapping form needs to be larger5 s9 J/ D! p" ^- n+ W. R
1893311 ALLEGRO_EDITOR     INTERFACES    A line became two lines after import dxf
+ \6 s+ V" {/ T: e! H5 i) ~& z- @3 O6 X1937816 ALLEGRO_EDITOR     INTERFACES    Unit as % in Property Definition not supported by SubDrawing& m$ H5 h; C4 s) y
1973084 ALLEGRO_EDITOR     INTERFACES    Physical library not placed if design and IDF database not matched while running
6 o) r4 w/ z2 H1987526 ALLEGRO_EDITOR     INTERFACES    IDX import Fails to recognize SURFACE FINISHES Class
% X1 C7 [+ N# s1872856 ALLEGRO_EDITOR     IN_DESIGN_ANA Message displayed when creating directed groups needs to be improved
, c$ U4 U: T3 j6 J; X( s1900832 ALLEGRO_EDITOR     IN_DESIGN_ANA RTP: Return Path DRC does not check circle void correctly
% i- P, Y* F; v  b$ w! B1935641 ALLEGRO_EDITOR     IN_DESIGN_ANA Return path DRC crashes PCB Editor
9 E, u5 V& |: K( b- }1649465 ALLEGRO_EDITOR     MANUFACT      Manufacturing options are not visible in OrCAD PCB Designer legacy menu2 k- v% a+ T) ~+ ?
1873417 ALLEGRO_EDITOR     MANUFACT      Autosilk fails to add line information. Only part of the line is getting copied to the autosilk layer.6 V) U7 u& p( B
1911596 ALLEGRO_EDITOR     MANUFACT      Documentation Editor drill chart shows two different rows for the same slot.
& A) `& J# i$ S  n" n- U# b1937721 ALLEGRO_EDITOR     MANUFACT      Drill figure character scaled up in GERBER
' O3 M6 I  o! a, @! d. W1957768 ALLEGRO_EDITOR     MANUFACT      Import IPC2581 on cross-section does not import line width and impedance
6 k; B- ?* m: k3 k% z1969363 ALLEGRO_EDITOR     MANUFACT      Pressfit connector backdrill depth is considering MNC Layer
* E0 |2 G7 k  l) G1891102 ALLEGRO_EDITOR     MULTI_USER    Rejected by server error messages when using Symphony Team Design/ l. o+ d6 u$ G0 O
1928082 ALLEGRO_EDITOR     MULTI_USER    Unknown SubClass BOUNDARY/MULTI_USER_LOCK automatically added when defining Artwork Output.) @1 U8 z& U. J& W
1976705 ALLEGRO_EDITOR     MULTI_USER    Symphony client disconnects from server without any notification - despite ping mechanism6 ~' ~: b( X* M; n, G
1972554 ALLEGRO_EDITOR     NC            Mill symbol moved from Nclegend-slots-1-2 to Nclegend-1-2 subclass if nc_param.txt not present
$ f; j; a' @# z2 e' j& Z7 R1914412 ALLEGRO_EDITOR     OTHER         Autosilk lines do not clear padstacks that are not rectangular! G0 f/ z& u- u
1921933 ALLEGRO_EDITOR     PAD_EDITOR    column clearance cannot reset to 0 in padstack editor$ I1 d; h+ Z' U; a
1922234 ALLEGRO_EDITOR     PAD_EDITOR    DBDoctor reports 'illegal value for pad' and does not fix when zero corner radius for Rounded Rectangle is defined
2 @- L0 H' B1 y. u- Z) u1932183 ALLEGRO_EDITOR     PAD_EDITOR    Drill Symbol information not exported in Padstack XML if Drill Figure in none9 j" e, F  z4 b. m
1934880 ALLEGRO_EDITOR     PAD_EDITOR    Shapes with offsets not displaying properly in Padstack Editor views
4 b+ h9 C# P0 `# n5 m1813270 ALLEGRO_EDITOR     PLACEMENT     When a place replicate module is updated, the vias used in thermal pad are removed
, A2 u2 R' Q$ L1840275 ALLEGRO_EDITOR     PLACEMENT     Placing component with the Mirror option causing display problems6 P# ^0 y$ R. F  H6 P- z
1854099 ALLEGRO_EDITOR     PLACEMENT     Align components to zero spacing causing mirrored components to overlap
, L" f& H4 N% B( j1854696 ALLEGRO_EDITOR     PLACEMENT     Pins shown incorrectly when the Alt Symbol and Mirror commands used consecutively
$ _% a! }! O# H1862863 ALLEGRO_EDITOR     PLACEMENT     Too many messages in the command window when symbol does not support mirroring7 K" ~1 G/ _0 U" F; V4 F, q
1909857 ALLEGRO_EDITOR     PLACEMENT     Using Mirror with Alt Symbol placement displays incorrect graphics8 F9 l0 e0 Y6 [2 `& d( d9 |! A0 ?
1917128 ALLEGRO_EDITOR     PLACEMENT     Place - Autoplace - Room when all the components of the room are placed on board causing crash$ n- U7 H5 H1 I: S6 E
1925144 ALLEGRO_EDITOR     PLACEMENT     PCB Editor stops responding on using the Autoplace - Room command8 q9 A1 M" n0 G% B
1961509 ALLEGRO_EDITOR     PLACEMENT     PCB Editor crashes on choosing Place - Autoplace -Room
2 V1 k% N7 v9 n* ~9 C9 U1930669 ALLEGRO_EDITOR     REPORTS       Net 'VSS' not included in the Etch Length By Pin Pair Report
! [( B# Y! K! A, w0 N1982934 ALLEGRO_EDITOR     SCRIPTS       PCB Editor stops responding if Generate button is used to create script from journal file
3 G! z9 ]+ I; q7 S! S1337346 ALLEGRO_EDITOR     SHAPE         Shape Check is generating problem point errors that seem unnecessary8 Y" r/ y7 X% G. \% H7 E: Z; p/ p
1396692 ALLEGRO_EDITOR     SHAPE         Zcopy with expansion not following board outline
8 k/ |3 Q3 p9 U4 `2 a  m9 j& _1902001 ALLEGRO_EDITOR     SHAPE         Shape behaving differently across hotfixes
4 K4 o- K' W7 a$ K1 L/ ?1921287 ALLEGRO_EDITOR     SHAPE         3D canvas is showing some stray objects
, Z/ ]" D( t, b1936482 ALLEGRO_EDITOR     SHAPE         Option for Fillet to not obey NO_SHAPE_CONNECT Property6 R7 q; l. |( l# e5 g; W
1943899 ALLEGRO_EDITOR     SHAPE         Only one Shape to Route Keep In DRC in release 17.2-2016 compared to two in release 16.6
1 q6 z) p  N- C. }! ^1944041 ALLEGRO_EDITOR     SHAPE         shape_rki_autoclip makes shape voiding incorrect/ f4 `) k% \& n/ m0 }
1947675 ALLEGRO_EDITOR     SHAPE         Shape void error when dv_squarecorners is enabled
* i8 D, \" N) o1949250 ALLEGRO_EDITOR     SHAPE         Shapes are filled even after raising and lowering priority
/ n. v, |& ~- i4 F% i" l1984526 ALLEGRO_EDITOR     SHAPE         Same net shape voided is inconsistent with respect to vias
$ U/ y8 a2 V- R' Q' ~1 y. h1984955 ALLEGRO_EDITOR     SHAPE         Dynamic shape creating same net spacing drcs.
7 E5 c* P2 C0 y1 f8 v, S3 ?' h9 m1839147 ALLEGRO_EDITOR     SKILL         axlDBGetLength() reports that the segments of a filled rectangle shape are invalid database ID arguments
: s7 x2 A( t4 P0 z6 U3 E1882776 ALLEGRO_EDITOR     SKILL         SKILL documentation for axlIsBetween() is wrong
* S% s9 R2 Z7 o& V1882882 ALLEGRO_EDITOR     SKILL         Example for axlMathConstants needs correction in Allegro SKILL Reference
' q2 D. W( V0 q- k( W8 i" h1902712 ALLEGRO_EDITOR     SKILL         axlAltSymbolReplace moves symbol to the top of design while replacing* }) a% |3 a: H! l0 p
1906329 ALLEGRO_EDITOR     SYMBOL        Mechanical Pin to Conductor property set on a pin in a symbol does not pass to the board1 N" a: [, d( \0 x
1911343 ALLEGRO_EDITOR     UI_FORMS      Global Visibility not turning all layers off* m2 T' W2 k& g# B; j" `
1985584 ALLEGRO_EDITOR     UI_FORMS      Import logic changes the Current Working Directory5 e# v+ a% b9 n; `$ d
1987829 ALLEGRO_EDITOR     UI_FORMS      Import logic changes the current working directory, G/ e2 I0 l) a" g# J' I2 K( F
1992722 ALLEGRO_EDITOR     UI_FORMS      After netlist import process, the board file is changing its current path
8 P5 H% q; P! h& R8 g! ]6 B1697506 ALLEGRO_EDITOR     UI_GENERAL    Stroke Editor working in OrCAD PCB Editor of release 16.6 does not work in release 17.2-2016
+ u  {. ^9 D/ a1 |1702631 ALLEGRO_EDITOR     UI_GENERAL    Etch Length by Net report does not list correct net name for nets in a bus% j3 K7 O) j$ Z7 W
1703105 ALLEGRO_EDITOR     UI_GENERAL    Bus net names are incorrect in reports when using the allegro_html_qt variable
( x- V9 F- T# M/ D1770786 ALLEGRO_EDITOR     UI_GENERAL    Stroke Editor working in OrCAD PCB Editor of release 16.6 does not work in release 17.2-20166 H% p4 h  Q4 D, |& x; D
1784938 ALLEGRO_EDITOR     UI_GENERAL    Etch Length by Net report does not show net names with angle brackets in release 17.2-2016
4 P: H/ y; H. @2 I! u0 C& F1822557 ALLEGRO_EDITOR     UI_GENERAL    axlUIWCloseAll is not closing text window in release 17.2-2016& X; i5 A  B% h/ N5 x) b" j9 {4 L
1836400 ALLEGRO_EDITOR     UI_GENERAL    Net names are truncated in HTML reports  d+ Y- B0 z1 ?2 h9 P9 m
1869879 ALLEGRO_EDITOR     UI_GENERAL    Links not working in the Net loop report
. k* A4 e: a2 G; X1895878 ALLEGRO_EDITOR     UI_GENERAL    axlUIWClose()/axlUIWCloseAll() functions do not work when allegro_html_qt setting is enabled.
- j, Y( V7 [$ V1912282 ALLEGRO_EDITOR     UI_GENERAL    PCB Editor exits with error message on editing objects
# X( C( e) T& A1913962 ALLEGRO_EDITOR     UI_GENERAL    PCB Editor toolbars change on choosing View - UI Settings - Save Settings and then restarting
9 w6 I3 @" ?3 @! M8 t3 c1933172 APD                UI_GENERAL    Cannot paste text into the command prompt without clicking when 'enable_command_window_history'  is set
' N" Q& ^( q. b( b5 z1843712 CAPTURE            NETGROUPS     Signals shown only for first segment of NetGroup
- a9 I1 K3 Q5 v0 ^1917768 CAPTURE            NEW_SYM_EDITO Missing package pin overview in Symbol editor; P4 ?1 `! s0 ~$ \/ _9 c' y; A
1920088 CAPTURE            NEW_SYM_EDITO Package view missing in the new Symbol Editor
5 H$ ?6 B; A4 M9 K9 n- O* _2 i1922196 CAPTURE            NEW_SYM_EDITO Snap to grid issue in Symbol editor; v( F! D5 R# d
1927268 CAPTURE            NEW_SYM_EDITO View Package is grayed out in release 17.2-2016, hotfix 038 and later versions( C  F3 i5 u. X
1928012 CAPTURE            NEW_SYM_EDITO In new Symbol Editor, View - Package is grayed out
. Z4 M. W4 x" H/ D  T1930865 CAPTURE            NEW_SYM_EDITO View Package missing in hotfix 038/ Q- k# j$ r7 x2 p7 _% F
1938507 CAPTURE            NEW_SYM_EDITO Issues with new Symbol Editor: Justification and spreadsheet usability
# ^3 d, f% k; n! ^1940869 CAPTURE            NEW_SYM_EDITO Missing pins in 'Edit Pins of All Section' table view for 4k resolution but not in 2k resolution
: U. }$ _8 d, g) `1940888 CAPTURE            NEW_SYM_EDITO Copying pins from a part and pasting on different parts not working properly.
3 T) g) [( j- t  m3 w1942994 CAPTURE            NEW_SYM_EDITO Cut / Paste of object in New Part / Symbol editor always pastes on grid
. U/ ]- d8 b4 [9 p$ ~0 v* i* W1944396 CAPTURE            NEW_SYM_EDITO JavaScript error while copying from 'Edit Pins of All Sections'5 j5 a+ W0 d1 D8 C8 \- K5 K
1950224 CAPTURE            NEW_SYM_EDITO Cyrillic alphabets are not displayed properly on Schematic.+ J6 e" o- @. M5 J  v
1951369 CAPTURE            NEW_SYM_EDITO Cancel closes Symbol Editor
4 g! l, {: }) y0 y6 R1 _& ^1966785 CAPTURE            NEW_SYM_EDITO Edit Part is grayed out
% a9 x# q# T, w$ n6 B1973135 CAPTURE            NEW_SYM_EDITO Issue with new Symbol Editor: cannot copy-paste pins
* k8 B: p3 t8 _( n: [9 z* F1973344 CAPTURE            NEW_SYM_EDITO JavaScript error on opening part from design
+ m4 I( I7 q% c  s1974122 CAPTURE            NEW_SYM_EDITO Cannot copy-paste all pin list on the new Symbol Editor
& l+ W% N) s# p1983593 CAPTURE            NEW_SYM_EDITO Script error on copying and pasting to property sheet
( ^' p4 r8 E: W) l7 V1929692 CAPTURE            OPTIONS       PACK_SHORT issues with Pin Numbers that contain letters/alphabets) x) N$ }& O+ ~* f9 r
1876939 CAPTURE            OTHER         Incorrect Capture renaming error (ORCAP-1310), G0 Y9 v  Z: f, ]( z4 f$ \8 ]! Z
1916090 CAPTURE            OTHER         Incorrect error message when 'save as' fails due to long directory path/ c# s( @2 Y& u3 s3 F9 I3 F
1921927 CAPTURE            OTHER         Two functions are mapped to Shift + R in OrCAD Capture in hotfix 038! z* {) z3 r2 c) V/ J
1946453 CAPTURE            OTHER         Shift+R shortcut is assigned to two functions.
2 a% ~6 ~% i% P! A1965456 CAPTURE            OTHER         Shortcut Shift + R is not opening the Independent Sources dialog box
: i9 [6 D' H" s. s1968757 CAPTURE            OTHER         Close CIP is grayed when right-clicking on the tab in Capture.
* A1 p' ^7 O( Q. n1938437 CAPTURE            PART_EDITOR   OrCAD Capture new Symbol Editor Pin Type missing in table# F) A, v6 m# V; N; k4 ~
1906757 CAPTURE            SCHEMATICS    Intersheet reference is overlapping with the offpage connector name1 }3 [1 E( J* ^) D
1867016 CAPTURE            SCHEMATIC_EDI Part placeholders not being positioned when moved
! v0 N) u4 F$ I1932837 CAPTURE            SCHEMATIC_EDI Parameters graphics are not correctly positioned
/ {4 O8 n2 R/ N9 W4 U! ^: x1949518 CAPTURE            SCHEMATIC_EDI Getting error when comparing designs
0 ~" }% e" e) b. o/ f1967545 CAPTURE            SCHEMATIC_EDI Only section A of heterogeneous part being placed and not sections B, C, or D. u* S, L. b4 w" @- o( T
1933919 CIS                DBC_CFG_WIZAR New CIS Configuration .dbc file created in release 17.2-2016 shows release 16.3
+ f% t1 e  e, Y/ L3 R: B/ ?# s$ x1932550 CIS                RELATIONAL_DB VIEW NAME in Relational Database configuration is not working as expected.
: H8 p' }- G' G' N. g$ y5 O% z1832524 CONCEPT_HDL        CHECKPLUS     Default checkplus rules show body height of 0 (sym_2 of the attached cell). This causes the cell to fail verification.) z$ v; b, s7 v2 L
1912023 CONCEPT_HDL        CHECKPLUS     signalWidth predicate does not recognize SIG[1..0] as bus.  V4 i8 S& i; M$ B3 N# _7 I# e) B
1966120 CONCEPT_HDL        COPY_PROJECT  Copying release 17.2-2016 project results in message stating the project is of an older version2 h2 [& `) c& \* q  b1 P& c5 \
1879425 CONCEPT_HDL        CORE          Adding signals with the right-click menu is not following the defined color scheme
6 A) e/ ^  h  ^' _: y8 U* E9 X6 w+ m1890542 CONCEPT_HDL        CORE          Getting ERROR(SPCOCN-1911) when running export physical with backannotation
/ t: G6 v, w! y% D& P9 S1907684 CONCEPT_HDL        CORE          Moving symbol makes canvas unresponsive for a long time0 G" f2 V- @. L' F0 w( Y, J
1920711 CONCEPT_HDL        CORE          Pin names changes when mirroring the swapped section.
. h; o- y5 Z: n1931421 CONCEPT_HDL        CORE          On Linux, 'cpmaccess -read' returns incorrect value
" ^9 |( g; c. {% h' w, X! y0 c1931782 CONCEPT_HDL        CORE          Setting DONT_FORCE_ORIGIN_ONGRID to ON does not work for sig_name
8 y+ D% J/ ~) d+ H- M9 H. ]1932433 CONCEPT_HDL        CORE          _movetogrid causes signal disconnection. Q6 Z4 U/ H4 |, A/ Z) b# V
1946993 CONCEPT_HDL        CORE          DE-HDL Part Manager fails to update parts on schematic if new KEY properties exist in PTF but not in schematic
% n5 I) f1 u1 ~' r" g) W1947029 CONCEPT_HDL        CORE          Design Entry HDL Font Support not working for signal rename
) z4 G0 `1 a$ V1962865 CONCEPT_HDL        CORE          Schematic symbol creation with '-' as pin name not packaging( \/ |8 P( r$ X' x0 N: H+ k
1966805 CONCEPT_HDL        CORE          Issues with packaging design containing cells named with a leading underscore  B( W. v- H3 D% f2 W. j6 Q, q0 F
1967760 CONCEPT_HDL        CORE          DE-HDL crashes on moving Net Group/Port in release 17.2-2016, hotfix 0448 C" F3 J8 z0 Z5 h  F/ E; ~
1968282 CONCEPT_HDL        CORE          DE-HDL Part Manager fails to update parts on schematic when new KEY properties exist in PTF and not in schematic: }1 [( h5 Z1 _
1972815 CONCEPT_HDL        CORE          Part Manager not updating missing key attributes from the ptf file by using 'Update instances' option
/ c, K4 V" M3 E" ]( V& T( G; U1887790 CONCEPT_HDL        CREFER        CRefer links not working in selected cpm file5 l& G3 T4 I3 N6 ?' T" `" G8 p
1898535 CONCEPT_HDL        INTERFACE_DES Global Navigation window does not reflect removal of a net on page2 that is part of a netgroup on page1
, ]3 `/ L7 o. d4 L! C0 G1888048 CONCEPT_HDL        PDF           Japanese characters are not output correctly to PDF on Linux.
: M+ ~5 \5 V5 `; F1937505 CONCEPT_HDL        PDF           Missing intersection dot in schematic PDF) X5 Q' k4 `& X7 h4 ]1 s
1942486 CONSTRAINT_MGR     CONCEPT_HDL   CM crashes when you save after importing a TCF file
* t# j: A$ F* b! a6 p$ _1983743 CONSTRAINT_MGR     CONCEPT_HDL   Region Class-Class members are being duplicated in CM in the current session+ k7 w" W, }4 p7 b+ V0 L
1906573 CONSTRAINT_MGR     ECS_APPLY     Database corrupt and DBDoctor reports illegal database pointer error) ?+ J. H4 T' E/ |" P5 E/ h2 R* L
1913805 CONSTRAINT_MGR     OTHER         Setting environmental variable CM_PARTIAL_DCF in release 17.2-2016 causing crash' ^/ R, k( X$ ]& n
1914813 CONSTRAINT_MGR     OTHER         C++ Runtime error and non-recoverable crash in class-class worksheet+ ?6 ^5 J- a* [1 [( v
1920142 CONSTRAINT_MGR     OTHER         Xnet names are not consistent in the design& J$ \' p% N1 t- m
1898549 CONSTRAINT_MGR     SCHEM_FTB     Importing netlist causing crash in release 17.2-2016, hotfix 036
* I& j  B- O' @8 L' Y. i- J2 w, p1814851 CONSTRAINT_MGR     UI_FORMS      Field solver /DRC check running forever
+ T# w! |8 E& h! d; J1889862 CONSTRAINT_MGR     UI_FORMS      PCB Editor hangs while assigning net voltages in CM
1 x$ Z! U( z5 Z- u2 u( X* _, O1965470 CONSTRAINT_MGR     UI_FORMS      Constraint Manager GUI Issue in release 17.2-2016, hotfix 039: Font size small and rows/columns in shrink mode1 g1 \% P1 b2 r4 \( _9 B
1945406 ECW                ADMINISTRATIO Tree view was not refreshed soon after changing the site permission.
" F$ j0 q6 j: `% \. q. n1826848 ECW                METRICS       SPDWECW-551 and SPDWECW-553 should be warnings, not errors
7 ^. _$ \+ I  U/ D1 z, P( {1933373 ECW                PROJECT_MANAG ecwbatch does not accept password and does not ignore invalid users5 Y, P* m$ r2 t% s6 W
1921502 F2B                PACKAGERXL    Errors on running Export Physical:SPCOPK-1138 and SPCOPK-1149' Z' o! _; z. Y8 X
1929846 F2B                PACKAGERXL    PackagerXL is still creating the pstcmbc.dat file on a release 16.6 design uprevved to release 17.2-2016
8 ^) K% d. ~2 E' K9 o! G( K# K1953780 F2B                PACKAGERXL    Updated subdesign package information not updated on the top-level design in the reuse flow
. j8 i& C2 U- }0 @) @7 E; z8 m1971738 F2B                PACKAGERXL    Deleting blank space from pstxnet.dat file crashing DE-HDL. U' o; a6 x2 Z4 i4 k' c) V
1891002 INSTALLATION       DOWNLOAD_MGR  Issue with Download Manager (Change Preferences Option does not Work)* {* g1 v4 e& J1 A3 I  y
1972890 ORBITIO            OTHER         OrbitIO-APR failed to run if PCB design included
' `$ `4 Q; J# y4 ^7 X1954262 PCB_LIBRARIAN      CORE          Footprint model check in fails with verification checks failed error
; s. \1 y$ d% g& _& ]# B% s2 A1943656 PCB_LIBRARIAN      GRAPHICAL_EDI Symbol Editor is blank if .ascii file is newer than .css file9 y: j3 P' @& P3 V, e0 d" t0 A3 L
1897887 PCB_LIBRARIAN      SYMBOL_EDITOR New Symbol Editor: Inconsistent symbol results when adding vector pins in Part Developer
; V# e5 p- s" H  D+ i! v6 B. I) J, E1898003 PCB_LIBRARIAN      SYMBOL_EDITOR Issue with Page Border Symbol4 R" ^9 }" W3 p  j# v) E4 o  Y
1842007 PSPICE             LIBRARIES     Change required in swit_reg.lib
' p9 [- [; x- P7 R3 |4 p! Y1906922 PSPICE             LIBRARIES     Mismatch in mapping of IC pins in model and PSpice template for analog device AD81381 l' r4 F5 h" C7 M
1947586 PSPICE             LIBRARIES     Update the model AD8138/AD in ANLG_DEV.OLB
$ S1 i: X3 _; E6 ?) @1748470 PSPICE             MATLAB        PSpice displays an error when sending current in co-simulation
% l: z" U9 C7 ]* d# _1802455 PSPICE             MATLAB        Incorrect current direction for pins in SLPS flow4 E; J: P! v0 x
1852811 PSPICE             MATLAB        ORPSIM-2604 being reported in SLPS simulation& O# @. D4 w( H+ M( u- f/ F; p
1858716 PSPICE             MATLAB        Co-Simulation fails if 'RC' is used as reference of resistor
& F5 `' y, Z4 q1921641 PSPICE             MODELEDITOR   Model Editor in Client Server installation slow to invoke' m6 ^8 m  H4 m5 t
1922160 PSPICE             MODELING_APPS New Capture Associate Symbol GUI not reading libraries; C4 c6 M% [+ j
1843698 PSPICE             PROBE         PSpice icons appear very small on a specific computer
& `1 K% z& @. q4 a1773841 PSPICE             SIMULATOR     orSimSetup64 crashes when running the simulation for attached design* M3 o5 Y1 Q0 Y6 T
1816316 PSPICE             SIMULATOR     Simulation stuck; however, the status bar is correctly updated during Pseudo Transient Analysis1 j2 W4 F7 i0 ~0 K6 `
1887119 SCM                IMPORTS       Cannot selectively update changes in VDD; {7 w5 k' K* d, F/ h& W
1889362 SCM                IMPORTS       Cannot selectively update changes in Visual Design Differences4 }% Q# q/ z" Z- i. Y- k: Z
1958545 SCM                SETUP         Auto assign models does not work in SCM same way as in DE-HDL
+ f  N3 g" W: W" Y8 [5 f7 W1988841 SIG_EXPLORER       INTERACTIV    SigXplorer stops responding or crashes in hotfix 047 when a design is saved& K( C7 |% T- j3 ^; @( O
1988943 SIG_EXPLORER       INTERACTIV    SigXplorer crashes on selecting Update Constraint Manager7 M$ N4 t: ^8 A# P/ J
1991375 SIG_EXPLORER       INTERACTIV    SigXplorer crashes when clicking Save
5 E7 t; b; O+ b9 V1993749 SIG_EXPLORER       INTERACTIV    SigXplorer crashes on saving topology
' i- v" N) ^3 g1969975 SIG_INTEGRITY      GUI           Model Browser edits model above the one that is selected
3 F6 r% F* P& k4 C8 z% g; K+ t% m4 {1953184 SIP_LAYOUT         IMPORT_DATA   Sub Drawing not saving dashed lines0 ^* Z+ B3 P( ?7 p, B6 m2 ?
1913864 SIP_LAYOUT         ORBITIO_IF    SiP Layout design import results in wrong die rotation6 D6 W$ m' O( i4 Z6 d
1880237 SIP_LAYOUT         PADSTACK_EDIT Background Window comes to the forefront when closing the Padstack editor1 |* [- s6 R4 ~0 P' |% H1 C) ~
1972560 SIP_LAYOUT         STREAM_IF     GDS Export fidelity issue: inverted arcs
' K5 Q7 i- P0 ^  T: c4 W9 |4 ~" f- Y1920317 SIP_LAYOUT         THIEVING      Thieving pattern does not allow for OOPS operation
6 n/ d0 |( \7 Q/ [$ i' y1909075 SYSTEMSI           DOC           SystemSI PBA channel and circuit simulations do not respond if bit pattern is 1s or 0s
5 ?6 ~0 p! m+ |& s1916101 SYSTEMSI           DOC           Lack of stimulus in file causes Serial Link Analysis to become unresponsive  w1 S6 |: ]5 N, j4 E
1919562 SYSTEMSI           ENG_PBA       SystemSI generates wrong timing bathtub curves in channel simulations for write and read6 C8 R; w$ O4 A8 R2 F
1964064 SYSTEMSI           GUI_PBA       Able to sweep AMI parameters in SSI-PBA
2 c6 q5 ?$ q5 e/ Q1971266 SYSTEMSI           GUI_PBA       MCP header shows only 49 ckt nodes instead of 52 for s52p S-parameter file
8 a. d% r% ~) T+ N8 t0 n' ?+ }3 y1885625 SYSTEMSI           GUI_SLA       Manage AMI + DLL from Setup Analysis Window
) c$ F1 \- F( g& Y: M0 L1924382 SYSTEMSI           GUI_SLA       Data Rate field in SystemSI Stimulus property form is confusing for PAM4 operation9 Q. p" ?6 e( `) T+ h: y9 ~4 \
1982341 SYSTEM_CAPTURE     CANVAS_EDIT   Signal rename does not maintain new signal name value
- N/ V; n% ]; s; l" Y! Y1976857 SYSTEM_CAPTURE     CONSTRAINT_MA System Capture-CM Match Group Creation is not updating correctly
7 h' m3 f* y/ l, b- }3 q1929606 SYSTEM_CAPTURE     DESIGN_CORRUP Opening design causes System Capture to crash8 ~5 {7 V# [* g. v8 Q& L9 c; H
1914697 SYSTEM_CAPTURE     DRC           Overlapping component DRC does not work
  t8 \0 Y7 m- d, }3 Z+ r  O1973467 SYSTEM_CAPTURE     IMPORT_PCB    System Capture Import Physical shows many component and physical differences on a design that is synced up; c) M8 t; `3 ^4 q& w6 u
1962603 SYSTEM_CAPTURE     NAVLINKS      Ability to not underline hyperlinks for Navigation Link values2 M5 Q& G9 Z+ l- E% z2 V# S
1967639 SYSTEM_CAPTURE     PART_MANAGER  Part Manager does not open in System Capture for part property value changes even after setting the cpm directive.+ W  c; r7 O2 n- \- ?& I) r, X
1964388 SYSTEM_CAPTURE     SMART_PDF     Some shapes are not visible in the smart PDF schematics/ i. h5 v+ b: ?3 D
1976832 SYSTEM_CAPTURE     TDO           Rolling Back local lower-block requires check-out of higher-level packaged & variant views
- B! e- L  x$ R- w! l. @1976844 SYSTEM_CAPTURE     TDO           CM - TDO check-out dependencies are broken: |. m. W0 l# M# R$ n& e; T
1976859 SYSTEM_CAPTURE     TDO           Variant Editor in System Capture -TDO allows to delete a variant without checking out variants view% q  ]1 z0 ]4 G& _1 o1 A
1839816 TDA                CORE          All the design objects are locked in the EDM dashboard after a DSFrame error
" D. N# t. z7 N/ J8 C1 d1889898 TDA                CORE          Cannot check in the top level of the project in TDO; F8 @5 Y9 s: n( z; c
1892411 TDA                CORE          Unable to undo the block checkout if something fails1 W9 L7 L; M' A5 S. K, |( l; N
1877757 TDA                DEHDL         Refresh Hierarchy does not show latest TDO lock/unlock status in DE-HDL
1 W/ s. r& F( }( F( m% {( K2 R1 G" }% D8 R0 A6 q3 _, g6 v

3 D: d" o5 B* H$ B( z" lFixed CCRs: SPB 17.2 HF047
3 Q0 e( M# h( h! [0 H09-9-2018+ ~5 K: F* O$ U5 s+ S3 Q) K
========================================================================================================================================================
% L" {/ y$ e7 N0 C, G2 v3 X9 D$ qCCRID   Product            ProductLevel2 Title
/ G3 j7 g9 Z  s+ V# K========================================================================================================================================================1 @9 s; r( i4 j5 V  c9 \7 a
1969527 ADW                LIBIMPORT     Getting  java.lang.NullPointerException error on bulk import in hotfix 044
  h! c/ F  k0 ]% c; W% F7 T/ V3 a1976219 ALLEGRO_EDITOR     DATABASE      .SAV file not created although message states it is created. n2 m2 y7 a: v0 M1 H
1968270 ALLEGRO_EDITOR     DFM           PCB Editor crashes when running DRC
. i1 \+ W8 u/ [- n- N) g1978421 ALLEGRO_EDITOR     DRC_CONSTR    False DRCs between via and its fillet shown after editing shape boundary" z+ R9 z4 M- e: E2 W  y  z+ y
1966772 ALLEGRO_EDITOR     PAD_EDITOR    PCB Editor and DBDoctor crash on editing DRA file: Found bad pointer, run dbdoctor
. \, `. Z  [6 _5 V1973866 ALLEGRO_EDITOR     SHAPE         PCB Editor crashes when deleting a group4 z. i4 ?) i7 l2 r# n9 N: @
1818779 ALLEGRO_EDITOR     UI_FORMS      Dialog box goes behind main window on clicking PCB Editor canvas8 U1 |  b# ]7 Q7 f1 S
1880175 ALLEGRO_EDITOR     UI_GENERAL    Multiple sessions of PCB Editor gets mixed up in Linux in release 17.2-2016
! i' J, S% n0 c7 [! m9 Q2 p1946027 ALLEGRO_EDITOR     UI_GENERAL    Arrow Keys in Canvas stop responding after changing the view., c9 r7 r: r: }; N9 H, k
1967701 ALLEGRO_EDITOR     UI_GENERAL    Arrow Key panning does not work when third-party SKILL call is active, ~' `/ D* Y' v4 u1 [7 D9 g% T) a
1967706 ALLEGRO_EDITOR     UI_GENERAL    Observe Special Characters when command is run2 I/ B; G8 h. Y- c" N
1971183 ALLEGRO_EDITOR     UI_GENERAL    Focus is lost from command line when Save icon is used
+ A2 O/ b- M7 h1971186 ALLEGRO_EDITOR     UI_GENERAL    Focus from Command line is lost when using CTRL + N- d4 U0 u. h2 C1 f
1971190 ALLEGRO_EDITOR     UI_GENERAL    Focus from Command line is lost when using CTRL + Alt
2 p$ k$ |9 P7 O- U1 n! S1971200 ALLEGRO_EDITOR     UI_GENERAL    Focus is lost in comand line when you save using command save- h3 T# ?3 l0 y: i: C  ?1 q7 H" O
1961833 APD                SHAPE         Crash when changing dimension of existing via padstack in the design
( r1 n7 ~8 p, T0 m1968256 ASDA               EXPORT_PCB    SDA crashes directly after Export to PCB
9 J8 @" [: `+ E" r% z0 p: y1970284 ASDA               EXPORT_PCB    Placing part crashes SDA5 E# u7 O  z; r- ~" y5 q

% |; h8 o- x; u7 ?' q7 g' p% o6 _" A: \
Fixed CCRs: SPB 17.2 HF046
  b* R, N. f% B  g* \08-24-2018
# K: s9 Q4 a9 Z: _+ V========================================================================================================================================================
$ F, z; o+ s6 Z: m4 _CCRID   Product            ProductLevel2 Title8 u( {3 x9 s; r& K* x, C3 y/ c
========================================================================================================================================================7 W" o4 q# k+ j8 b) i
1880800 ADW                PART_BROWSER  Server connection failure on a running SDA session.4 n; O8 m5 O4 s6 ]: S/ j$ I! ~
1880895 ADW                PART_BROWSER  NCB - components missing from the component browser
  r- X: w* ~. y; k1962336 ALLEGRO_EDITOR     INTERFACES    Smart PDF shows both top and bottom probe layers for a film layer with only a single probe layer (top or bottom)8 h& d% x# j9 T; R8 \# |  l8 ~
1955128 ALLEGRO_EDITOR     MANUFACT      Need to close PCB Editor to delete xsectionChart.log generated on placing a cross-section chart$ _% h# L) o/ k
1969088 ALLEGRO_EDITOR     SHAPE         PCB Editor crashes on updating shapes to smooth9 e2 r/ l2 Y* }  X
1963828 ASDA               DESIGN_EXPLOR Unwired schematic block movement with text is not correct' z# n! l7 i4 _
1954426 ASDA               OPEN_CLOSE_PR Double-clicking to paste a note crashes SDA
" \1 k3 H  b. {; Z$ w9 [+ f1965423 ASDA               OPEN_CLOSE_PR Crash when working with notes in SDA
) C" W% x+ o) P$ b1960060 ASDA               PART_MANAGER  Original property differences not displayed in Part Manager on selecting a new part from CB and doing reset
! d; _, _: m# z# y1960112 ASDA               PART_MANAGER  Part Manager incorrectly updating part property values# z0 N) }3 V9 d4 D9 O5 r1 l
1955723 ASDA               ROUTING       Draw Multiple Bits misses bit 0 when in reverse order.1 x5 ], a( o# `$ Z
1952963 CONCEPT_HDL        CORE          Variant Editor takes a long time to load
3 g$ B6 F5 ^4 v/ K7 f* A8 q1962568 CONCEPT_HDL        CORE          Directive DEHDL_BROWSER_FILEPATH does not work
7 ]) J& v5 S9 L1939192 PCB_LIBRARIAN      SYMBOL_EDITOR pin_text size and location very different between DE-HDL and Symbol Editor resulting in text overlap2 |- e/ ~. m0 b4 @
1952967 SCM                OTHER         Error while copying a release 17.2-2016 design: message says design created in release 16.3 or an earlier version( C6 R( x/ M( _
1948999 SPIF               OTHER         Some place_keepout shapes and antipads not exported
( \& X2 s* m4 u4 y  b$ o5 X
# Q, B7 b9 W5 j
- k" `  M2 \: o0 r' v# y5 b' ?, h7 WFixed CCRs: SPB 17.2 HF045
9 P4 }6 y, i9 M9 G( e  [0 Q- U  Q08-10-20185 u; \' O' Z! F8 \5 r- L# U+ X
========================================================================================================================================================
( l2 R9 j9 _# I: A% gCCRID   Product            ProductLevel2 Title1 G; m; r9 v/ D. N& M) @. j; z
========================================================================================================================================================! |, q' v; ?/ b( B. k
1934956 ADW                DBEDITOR      Footprint missing from part in release 17.2-2016
3 ~/ h/ }& u6 M6 e9 T* e: Z0 V1945005 ADW                DSN_MIGRATION Right side of Migration dialog box is cut off8 j) Z2 m5 ~2 p6 C
1933245 ADW                FLOW_MGR      'Open last Project' button should open the last opened project
) P. j! W( M3 S2 n1953210 ADW                LIBDISTRIBUTI Library Distribution is not distributing all symbols. No errors for the missing schematic models.
9 R* q" y9 j7 F# ]8 i1953727 ADW                LRM           LRM missing two symbols when migrating from release 16.6 to 17.2-20165 h! |$ P$ F) c! s# g% Q( N' _' [
1952923 ALLEGRO_EDITOR     DATABASE      PCB Editor crashes on trying to delete layer
4 w7 e9 b5 |4 F/ a) X1 Z1957171 ALLEGRO_EDITOR     DATABASE      Pastemask offset not working when creating a symbol that requires two top-paste masks
( S8 Z9 v% A2 Y# ?. E. n0 x8 M1960059 ALLEGRO_EDITOR     DATABASE      Stackup definition causes custom script to crash
2 q# ^* F8 l3 y) ?+ L1932864 ALLEGRO_EDITOR     DFM           Exporting DFM Constraints losing the association to design level( T9 P# ~9 z+ z( n
1957467 ALLEGRO_EDITOR     EDIT_SHAPE    Compose Shape copies lines to wrong subclass* j/ D! u/ f' m" q) R2 {) Q
1938536 ALLEGRO_EDITOR     GRAPHICS      Multiple crashes on different boards after installing hotfix 040
- Y0 q5 U. E( n! c! V( A! R( E( z1954075 ALLEGRO_EDITOR     SHAPE         Dynamic Crosshatch shapes should be clipped inside RKI if RKI Autoclip is enabled
/ d; m' Y6 o* `$ f. z% S' V, F' y1957803 ALLEGRO_EDITOR     SHAPE         Wrong dynamic shape status
0 v! l) H2 O% C- \3 F/ M0 _! C1949923 ALLEGRO_EDITOR     UI_GENERAL    Focus lost from command window when any command is active
/ ~. ?; p* X* w5 q# O! B; [9 V1963245 ALLEGRO_EDITOR     UI_GENERAL    Alias behaves as Funckey in release 17.2-2016, hotfix 044
' k7 M* P6 I% u' @1892126 ALLEGRO_PROD_TOOLB CORE          Clines disappear and then reappear suddenly on using Route - Shield Generator
. K5 W' H- y( f9 g1931127 ALLEGRO_PROD_TOOLB CORE          ZDRC not working for Xhatch Shape) {1 g) y* O! j2 K$ z" t5 M- S
1932563 ALLEGRO_PROD_TOOLB CORE          allegro_legacy_board_outline environment variable not set in PCB Design Compare.7 J* w4 f! k7 K. b$ k3 w" d- c8 ~
1929855 ALLEGRO_PROD_TOOLB OTHERS        Outline not exported correctly for PCB design compare if Design_Outline and Cutout exist; x- d! K+ {! t
1956494 APD                DATABASE      DBDoctor removes pads
% G! _* F( f! c; q" L% e: P5 s4 E* a1956291 APD                INTERACTIVE   axlSpreadsheetSetStyleProp should accept 0 and 1 as Boolean values for protection style
* g3 U6 ~5 w- z  p  p8 K1960127 ASDA               ARCHIVER      Using the Tcl command 'archiveproject' crashes SDA
/ m6 v9 D# E- J1 G% D% T3 n# S9 A1953718 ASDA               CONSTRAINT_MA SDA Import Pin Delay fails with extra columns, does not explain why
0 C( ]6 L7 r& I! E6 _; `% e9 n3 l1924498 CAPTURE            SCHEMATIC_EDI Cannot place part 'B' for heterogeneous part if 'Preferences - Miscellaneous - Auto References' not set
" Y0 g! S1 l, e( R3 A1927129 CAPTURE            SCHEMATIC_EDI unable to place heterogeneous part section directly from place part window8 R  ~; |+ H2 o: |0 y
1928255 CAPTURE            SCHEMATIC_EDI Unable to place a specific section from Place Part
& t7 b; M3 G7 R1 G: u" o4 u& u1945207 CAPTURE            SCHEMATIC_EDI Part selection pull-down reverts to part '1|A' when placing heterogeneous part
5 @) p+ H7 t6 K- ^, Z2 t& q# ^1945661 CAPTURE            SCHEMATIC_EDI Section drop-down in Place Part window is not working7 Z9 `. \- f6 z+ P1 Z/ Z, g4 c' T
1958121 CAPTURE            SCHEMATIC_EDI Preview and placement of sections of Heterogeneous parts is not correct in New Symbol Editor  a3 R! S- ^% A; W1 y
1956535 CONCEPT_HDL        CORE          DE-HDL crashes on Import Pin Delay for a CSV file% |# ]7 J8 l5 y, z
1960922 CONCEPT_HDL        CORE          DE-HDL crashes on moving netgroup on Windows 10, Y& X4 P. m! |  c
1964016 CONCEPT_HDL        CORE          In DE-HDL moving around nets connected to Netgroups causes crash on Windows 10/ t& [* D/ T; y
1907040 F2B                PACKAGERXL    Export Physical output board file name reverts to old when changing options
0 w! k. ]9 E+ u2 D: p1957862 ORBITIO            ALLEGRO_SIP_I allegro2orbit failed to translate rounded rectangle padstack5 _  V# x! g' w, }% ]% K
  S8 N6 D) R# d5 g
! |% j; u" r4 _4 u
Fixed CCRs: SPB 17.2 HF0445 @# ^  D' ?6 L$ ]
07-27-2018) y5 V' I/ U' Z- J2 g
========================================================================================================================================================
& v4 F7 U1 f% XCCRID   Product            ProductLevel2 Title
8 x6 t; R* l9 {) P========================================================================================================================================================% y! w, ~7 i# @" {2 n* y0 |9 g
1943727 ADW                DBEDITOR      EDM DBEditor: Cannot check in/out schematic model symbols with many linked parts
) w+ N, L* _& d4 q' f( X1800630 ADW                FLOW_MGR      Support spaces in design directory path on Windows: m& ~: p5 X" I/ K) D' ]4 D; F
1951052 ADW                LRM           LRM stops responding on project update and removes parts from design
" |: t( }3 ?- _2 M5 v0 @! L1891428 ADW                PART_MANAGER  Resistor turns into a capacitor when placed8 T3 }+ j0 @0 c6 ?! g
1945194 ALLEGRO_EDITOR     3D_CANVAS     3D Viewer crashes when opening from board file.
7 e* l3 M) R: \: P' B1935558 ALLEGRO_EDITOR     INTERFACES    Exported STEP file missing components when viewed in free STEP viewer
3 E' T2 J5 c2 @3 Z1945640 ALLEGRO_EDITOR     MULTI_USER    Symphony client disconnects from server without any notification
" Q! R6 G1 p4 l1 Q( R1948454 ALLEGRO_EDITOR     MULTI_USER    Window DRC stops responding when run in Symphony
8 w/ s1 H) p) r! X7 B! M  ~1946619 ALLEGRO_EDITOR     SHAPE         Pin/via with suppressed pad on shape layer and thermal connection type of none should void to drill hole./ R, ~$ ]$ s0 w  v
1946708 ALLEGRO_EDITOR     SHAPE         Same net hole to shape voiding is incorrect.* m* o" |. G. O
1952213 ALLEGRO_EDITOR     SHAPE         Shape voiding from Thru Via when the via regular pad is not completely drilled out by Backdrill hole is not consistent3 k6 H4 ?8 Q0 M
1889433 ALLEGRO_EDITOR     UI_GENERAL    Command window shows result at the end of a command rather than showing dynamic updates
, j# Z: Y2 b" d' [0 g/ w; q1933503 ALLEGRO_EDITOR     UI_GENERAL    Extra click required to enable command window% d8 ~. x+ J8 R: A# ]) Z" m. K
1943692 ALLEGRO_EDITOR     UI_GENERAL    Funckey commands are not working7 F# N5 ~; ^" e; C
1945914 ALLEGRO_EDITOR     UI_GENERAL    Mouse focus lost in the command console when doing an 'undo' from the toolbar icon
5 _& N) s* z% _1945920 ALLEGRO_EDITOR     UI_GENERAL    Focus lost from command window when the toolbar is used for any operation* n0 b1 u& z$ u/ Z, ^: A
1949922 ALLEGRO_EDITOR     UI_GENERAL    Focus lost from command window after save or even autosave
  x. Y* T; a  j4 c" K9 q; ^1947551 ALLEGRO_EDITOR     WIREBOND      PCB Editor crashes in wirebond edit mode
2 W. M4 |- c# e( D$ Y7 m, h1935722 ALLEGRO_PROD_TOOLB OTHERS        Panelization: Cannot place parts after migrating design from release 16.6 to 17.2-2016' J6 S& n5 O) U
1951511 APD                REPORTS       The result of Metal Usage Report is incorrect.
; d4 M7 _) @: [+ B( z1952942 ASDA               GRAPHICS      Need metric (mm) support in grids in SDA
8 K4 m7 u6 U  \- e- Q9 K! N) V1948122 ASDA               TDO           If user ID has uppercase characters in teamassignmenttemplate.xml, TDO fails to join a project
: X' t9 u7 w8 S6 {3 z) [( m. L7 a1931199 CONCEPT_HDL        COPY_PROJECT  Stop hard coding Copy Project license inside EDM6 @7 M) S6 J! R+ P' ]4 h+ \
1938153 CONCEPT_HDL        OTHER         Component Browser stops responding on replacing and modifying components
  A9 I8 s% P0 ^' p1770601 CONCEPT_HDL        PDF           Wire Pattern set to two-dot chain line not shown in PDF0 ^! q! R( ]1 j6 e2 K+ U
1791175 PCB_LIBRARIAN      CORE          Allow baseline of cells with pins at symbol origin: change error to warning
& H7 L: V5 T% B1922238 PCB_LIBRARIAN      CORE          Unable to check in into EDM Server due to con2con error SPLBPD-323 - Origin on pin connection point
! t" H2 D* |; I7 R2 ?( @" b6 @3 H6 B1936812 PCB_LIBRARIAN      GRAPHICAL_EDI New Symbol Editor: Wrong text being updated when editing text after copy and paste
; ]. o" I. B2 o. p5 h2 [' S1804159 PCB_LIBRARIAN      SYMBOL_EDITOR Copy and paste of pins in new symbol editor: issues with pin name, rotation, and move1 T" \1 b; ^  C5 }
1927422 PCB_LIBRARIAN      SYMBOL_EDITOR Symbol outline not updated correctly in the new default graphic editor in Part Developer release 17.2-2016* x" L4 B# O' D* k9 J" F
1939272 PCB_LIBRARIAN      SYMBOL_EDITOR Symbol Editor changes origin to bottom left, outline to invisible, shows rectangle with center rectangle at new origin
; Z' `# t$ w; W+ q1 N  P2 t" b1928076 RF_PCB             DISCRETE_LIBX dlibx2iff does not work with managed libraries and library-level PTF
* a' J7 e8 R3 v3 X8 z' P$ z, ]1 _1929574 RF_PCB             DISCRETE_LIBX Discrete Library to third-party Translator does not populate the Available Parts section correctly
2 {  s/ V* Q7 ]1 o1850360 TDA                CORE          TDO crashes while changing the root design
" X! M8 u2 a  g) d* w9 x7 O, X1934388 TDA                SDA           SDA TDO crashes on attempting to check in a 'New Block in Shared Area'4 ~, k; v5 z' {# Y$ z
$ ?& K& B( l* l6 h/ j) S, n
) a4 J7 q" w2 w8 ]6 Z
Fixed CCRs: SPB 17.2 HF043$ K8 B' d( Z  J1 K$ P( B3 G+ {3 W
07-13-2018+ K: I" s+ x0 w3 r9 a# s4 ^0 _
========================================================================================================================================================
( p1 X; b2 C( B" BCCRID   Product            ProductLevel2 Title" x: y# q& ^" s& p0 G' v
========================================================================================================================================================
* m4 J% C/ h6 c6 X) ?1935813 ADW                DBEDITOR      Auto merging of DE-HDL and Capture Classifications is not working, S+ t7 K# ~7 q3 r1 X4 P9 q
1935834 ADW                DBEDITOR      Some DE-HDL only classifications are removed during the CSV merge process of libimport
6 E$ M" }# K. U, Z1941570 ALLEGRO_EDITOR     DATABASE      PCB Editor crashes or stops responding on performing 'Info' or 'edit properties' on select pins
! p; d& U! C# K. Y9 ]0 ?( \+ y% @1942536 ALLEGRO_EDITOR     DATABASE      Allegro PCB Editor fails to create backdrill plunges in Zone area
$ q- f  K- ?7 y# {4 Y+ I1925899 ALLEGRO_EDITOR     DFM           PCB Editor crashes when placing components in Hotfix 039
, T+ X; b- y! P8 X2 e' ?7 Y1943113 ALLEGRO_EDITOR     DFM           Restore normal move/slide via performance when annular ring checking is enabled.& ~/ c* s" A# l' p1 o  E. Y2 }
1940939 ALLEGRO_EDITOR     EDIT_ETCH     PCB Editor crashed on running the Gloss - Line and via cleanup tool
& Q( h1 L; @  B2 v) F1937754 ALLEGRO_EDITOR     GRAPHICS      Text string disappears when selected during 'Edit - Text' if using PCB_CURSOR7 `% O5 y! L1 P/ L
1937056 ALLEGRO_EDITOR     INTERFACES    Cannot import IDX acceptance of third-party change to PCB Editor1 n, k  \4 d! |+ [* U" t, d
1940197 ALLEGRO_EDITOR     INTERFACES    PCB Editor crashes when reading IDX file from third-party' P, o6 m) a6 }; f5 ]4 g- e0 ]
1940232 ALLEGRO_EDITOR     IN_DESIGN_ANA PCB Editor crashes when running Return path DRC
4 T) E7 R! {* W9 r* w- V' S1 z1916921 ALLEGRO_EDITOR     PLACEMENT     Property Pin_Global_Fiducial not inherited from symbol into board; E3 l: z; {- S5 u0 \
1862241 ALLEGRO_EDITOR     REPORTS       In 'Summary Drawing Report', the listed quantity for HDI vias is incorrect under Drilling Statistics
9 }. _6 `, }3 _$ Z  S; S* u4 ~1935448 ALLEGRO_EDITOR     REPORTS       Etch Detailed Length Report lists only one coordinate pair per trace
( ]7 }- x7 q! |9 l3 {8 q1948322 ALLEGRO_EDITOR     SHAPE         Allegro hangs when axlPolyOperation api is called3 L- Z, J% R& G! G4 Z) A
1795564 ALLEGRO_EDITOR     UI_GENERAL    In release 17.2-2016, focus is lost from command window after right-click% x8 n" Z, X: g
1919247 ALLEGRO_EDITOR     UI_GENERAL    Infinite cursor graphics issues on move: Cursor disappears and symbol image remains at old location till refresh- G3 {% C# _* T' r5 Q
1919256 ALLEGRO_EDITOR     UI_GENERAL    Infinite cursor graphics issue: Symbol disappears during rotate+ s+ X- \% I2 v5 ]8 m( r- v- ?9 o
1933526 ALLEGRO_EDITOR     UI_GENERAL    Panning is slow in PCB Editor in Hotfix 0388 h4 X; n: T/ T
1933530 ALLEGRO_EDITOR     UI_GENERAL    Strokes are slower to respond in release 17.2-2016
3 V) C0 ~. b" e1 ^4 |) D* x8 H9 z1933536 ALLEGRO_EDITOR     UI_GENERAL    Third-party dialog stops responding on running commands8 S9 Q+ m) z2 v7 U6 b6 V( ?
1782227 APD                DIE_GENERATOR Ability to specify rectangular shapes in die text in6 f3 i5 Y4 x# {, Y+ a& h' A/ \
1933011 ASDA               PART_MANAGER  Parts changed in library with new pin names are not reported or updated by Part Manager* m3 X- K! x  z, {: N  T* X
1924529 CAPTURE            NEW_SYM_EDITO Global colors for pin name and number and part body not allowed in release 17.2-2016, Hotfix 038/0399 p) i* C; s; x' Z8 w& I9 U2 }
1925846 CAPTURE            NEW_SYM_EDITO Opening library or component with special characters in path throws JavaScript exception# h5 I% m) I! ~+ Y& Y9 R* {" \& D5 i
1928905 CAPTURE            NEW_SYM_EDITO Pin name justification, length, and casing incorrect for generated parts in Hotfix 038
; u, `, R4 ?$ _1928965 CAPTURE            NEW_SYM_EDITO Cannot move pins in Capture if Pin Name is missing9 N5 F. |1 ~- L
1932149 CAPTURE            NEW_SYM_EDITO JavaScript exception if path to part contains special characters in Hotfix 039
! V# a; H/ o9 U- R1 Q1936301 CAPTURE            NEW_SYM_EDITO Cannot edit symbol in new symbol editor: Displays parsing error (SPSMI-1)+ F9 f% p. J  A4 B5 n
1917172 CAPTURE            PART_EDITOR   Pin name rotating on schematic even when pin name rotate is off in symbol editor+ _- u4 V2 |$ [% g. x2 b1 M
1924456 CAPTURE            PART_EDITOR   Color preferences for pin, pin name, and pin number do not apply in part editor but only in schematic
/ I% Y8 Q! D' j" i1 ^# b8 C1928872 CAPTURE            PART_EDITOR   Pin name locations are wrong and each needs to be placed manually: z5 b1 x0 f0 f  h: ?1 k2 Z
1929562 CAPTURE            PART_EDITOR   Changing pin name while adding a pin not intuitive in Symbol Editor
3 z0 v2 k' W) v; k/ `( D! ^, s1932732 CAPTURE            PART_EDITOR   Part Editor issue: Pin name selection box too long and text not justified in Hotfix 040
4 r0 D7 c% I# F$ B1933523 CAPTURE            PART_EDITOR   Connection box does not appear after changing pin of a placed part in Hotfix 0401 d6 e; s7 R" h" |
1936994 CAPTURE            PART_EDITOR   Error because of illegal characters in pin name and number and net name, W# l7 [" T* I3 _/ q- Q  W
1943074 CAPTURE            PART_EDITOR   Pin names rotated in Part Editor not rotated when placed on page9 `# @+ D# l9 q' j: O( w+ q# |
1943078 CAPTURE            PART_EDITOR   Pin name rotate not working.9 h5 F0 @6 b2 n/ Z" K& x" K8 l
1945055 CAPTURE            PART_EDITOR   Pin names not rotated in schematic
- ~- s+ J0 B" D! T4 C1 V  D' }1925700 CAPTURE            VIEWER        Pin numbers and text not shown during Variant View mode anymore.0 b$ [8 R  t% y: |9 [
1914437 CONSTRAINT_MGR     CONCEPT_HDL   Constraint Difference Report appears even though there is no difference in constraint.; e) d2 S/ T2 T+ Q
1935152 CONSTRAINT_MGR     CONCEPT_HDL   Match Groups are not formed with the correct pin pairs
# N0 z5 G0 j/ Y$ o$ I6 x0 ~3 ~1940575 SIP_LAYOUT         ORBITIO_IF    Need new routing flow
2 I' i- L2 Q8 m1 l5 H1923722 SIP_LAYOUT         STREAM_IF     Use one symbol for all instances of a Via Structure
7 s* m3 [+ d: Q% U+ l$ p8 a4 E1 Q" R/ H8 c1 N# b
  ?3 }4 r5 T7 A# s" o; P
Fixed CCRs: SPB 17.2 HF042
+ u3 J8 b6 G1 _7 |06-22-2018/ n' ?6 p, d* d- Y
========================================================================================================================================================
" H! j. {( v; p; sCCRID   Product            ProductLevel2 Title) ]" ^; T2 p& Z. A5 c
========================================================================================================================================================& l  s" I4 w0 V. S" ]( h, k
1922654 ALLEGRO_EDITOR     ARTWORK       Difference in board and Gerber display5 Q2 d; C+ a: u7 B) G( r# e$ W
1932714 ALLEGRO_EDITOR     COLOR         Manufacturing subclass NCDRILL_FIGURE missing from Color Dialog when editing .dra file- I6 H+ v9 x% G
1932316 ALLEGRO_EDITOR     DFM           DFM constraint reporting wrong DRC between backdrill via hole to shape clearance under copper spacing( k, G! e% N0 C; J/ A. S
1914334 ALLEGRO_EDITOR     INTERFACES    Design Compare does not import some netlists created using Export - Netlist with properties from PCB Editor7 |) p* Q8 ~  G3 x( i
1910213 ALLEGRO_EDITOR     MANUFACT      OrCAD PCB Designer shows Backdrill Status in Check - Design Status
' w$ T) n6 Y# _9 v1933049 ALLEGRO_EDITOR     MANUFACT      NC Route seems to put all routed drills in the same .rou file regardless of what layer they are on.+ M" \/ e5 b& g/ i$ j5 @5 x
1880576 ALLEGRO_EDITOR     PLOTTING      Extra lines appearing in plots that are mirrored; @4 j5 B+ {. {: k' F& t. `$ v: J! O
1881031 ALLEGRO_EDITOR     PLOTTING      Plot Preview with the Mirror option in the Plot setup creates fancy lines on shapes
" p$ Y- ]3 `& W( [1 @+ \$ I( R1908005 ALLEGRO_EDITOR     PLOTTING      Plotting with mirror options set results in strange lines on the plot8 d: J' ^& @# C; M7 R& ^( B  y; m2 S% ?
1909530 ALLEGRO_EDITOR     PLOTTING      Use mirror function when plotting lines to design
8 Y/ K  a& H" u2 K0 B+ @  n) e( b1919405 ALLEGRO_EDITOR     PLOTTING      Printing with the mirror option results in arcs in Print Preview
9 }" C7 ~& |2 D! \: ~$ I8 S# Q1830419 ALLEGRO_EDITOR     SCHEM_FTB     Import Logic with 'Overwrite current constraints' deletes attributes from drawing9 s7 m  V; {3 z! u! J& r
1935253 ALLEGRO_EDITOR     SHAPE         Compose shape command causes tool to stop responding
: g& {! h) V5 N0 h3 u7 b1571600 ALLEGRO_EDITOR     UI_GENERAL    File - Capture Canvas Image missing in release 17.2-2016
% S; t- \; L6 ~! L1650403 ALLEGRO_EDITOR     UI_GENERAL    Include Capture Canvas Image command in Allegro PCB Editor release 17.2-2016
: A# Q- M# f0 G6 s1 |( M1710310 ALLEGRO_EDITOR     UI_GENERAL    'Capture Canvas Image' command is absent from the file menu in PCB Editor in release 17.2-2016
# T: W* S- R% I, `1718407 ALLEGRO_EDITOR     UI_GENERAL    Reintroduce the Capture Canvas Image command
5 {6 B+ C" v+ _+ y- Q6 z1729699 ALLEGRO_EDITOR     UI_GENERAL    Capture Canvas Image is not present in release 17.2-20169 Q0 u) W& A4 C. _2 [
1753234 ALLEGRO_EDITOR     UI_GENERAL    Capture Canvas Image missing from the File menu8 n$ }9 P8 A& v5 U8 v7 C; C
1754222 ALLEGRO_EDITOR     UI_GENERAL    Need command to capture view window as image in release 17.2-2016% J$ o9 s6 s( Q9 r7 f3 O
1794348 ALLEGRO_EDITOR     UI_GENERAL    Reintroduce Capture Canvas Image in PCB Editor in release 17.2-2016. v  J, W- y6 _2 E
1818610 ALLEGRO_EDITOR     UI_GENERAL    Restore the option to capture canvas image in PCB Editor in release 17.2-2016' u8 [1 Q0 `1 A- U
1844591 ALLEGRO_EDITOR     UI_GENERAL    Reintroduce 'Capture Canvas Image' in release 17.2-2016
9 q5 {: j$ j4 {. u) r& [1869380 ALLEGRO_EDITOR     UI_GENERAL    File - Capture Canvas Image missing in release 17.2-2016
7 q. B7 o% ]( ]: V( ~# a1889412 ALLEGRO_EDITOR     UI_GENERAL    Cross-probing between two boards in release 17.2-2016
0 |- }, ]5 x- M8 L0 ^1 |1922329 ALLEGRO_EDITOR     UI_GENERAL    Add the 'Capture Canvas Image' command in release 17.2-2016
8 V' M  u7 Y" O) M( V6 k4 _0 i# l0 n1932070 ALLEGRO_EDITOR     UI_GENERAL    File - Capture Canvas Image is missing in release 17.2-2016
4 a! a1 T9 o9 E+ [0 o) E1885594 ASDA               PACKAGER      Export to PCB Layout exits without reporting error when Netrev fails* t; l  |- l/ X$ B' L* O
1931657 ASDA               PACKAGER      Export to PCB Editor does not work for a project  J# l0 z) d# V3 T" ~3 i! w3 P
1937757 ECW                METRICS       SDA metrics not getting collected6 ]! u( F' Z. `4 @' ^7 ?. D
1934482 EMI                SETUP         EMControl function flow is not working correctly in release 17.2-2016
4 Q) ^) G1 L- C+ x# x$ a0 i. a1931623 SIP_LAYOUT         EDIT_ETCH     Shapes are not updated and force update does not work
, c# g, h3 Q% f* G1 n2 L
6 ]$ T6 L; E5 s! b5 o2 A' E8 e7 g$ P3 {* N1 \  {: Q
Fixed CCRs: SPB 17.2 HF041. v6 Z+ k4 k) b! x! p
06-9-2018  C+ [3 D/ g% F, L" u- y( a
========================================================================================================================================================
2 U+ b0 b' A9 `9 hCCRID   Product            ProductLevel2 Title) C# H/ G1 ^* E$ z
========================================================================================================================================================
; Y0 p7 |$ L1 U# J! H  Y1880083 ADW                ADWSERVER     ALM fails to connect and authenticate LDAP server
: i# X+ W5 C. t1922218 ALLEGRO_EDITOR     3D_CANVAS     PCB Editor stops responding when 3D Canvas is opened for a symbol
$ ?* y4 t) R0 @6 d; [1 P$ L5 r% }1915838 ALLEGRO_EDITOR     DFM           Outline to non-signal geometry is not working for non-etch layers in design
$ u2 N0 I1 z1 w' s$ h1925263 ALLEGRO_EDITOR     DFM           False minimum spoke count DRC
! y' R3 K$ K6 \) @+ D. z1895486 ALLEGRO_EDITOR     INTERFACES    Importing IPF displays error regarding line being outside drawing extents (SPMHMF-409)
  n0 o# l" x; M" ?1927266 ALLEGRO_EDITOR     INTERFACES    Miniaturization license required when using enterprise licenses6 s& \' s2 {8 D8 q  q
1912186 ALLEGRO_EDITOR     IN_DESIGN_ANA Coupling analysis on one net takes a long time7 M5 P5 `7 K9 |; H
1916015 ALLEGRO_EDITOR     NC            Improve the message for reporting unsupported characters in the directory path while generating NC Drill data  w8 J( v, ]" e) a4 ~6 n: Q
1926072 ALLEGRO_EDITOR     SHAPE         Dynamic shape to route keepout not voiding correctly
3 H, q7 E+ Q8 ]' ^* q3 Y) O4 C1903202 ALLEGRO_EDITOR     UI_GENERAL    HTML report dialog does not handle relative links to files correctly
: m0 g2 ~, l5 H1880684 ALTM_TRANSLATOR    CAPTURE       Importing third-party schematic is not working in Capture  a" o3 h: w: r! _: _
1870218 ALTM_TRANSLATOR    DE_HDL        Unable to translate a third-party design to DE-HDL. H  ?) D% N! R, U% z/ A+ I/ J
1881208 ALTM_TRANSLATOR    DE_HDL        Third-party to DE-HDL translation: schematic symbols missing all pins+ `: r2 x) T& l) H0 m
1889909 ALTM_TRANSLATOR    DE_HDL        Third-party to DE-HDL and OrCAD Capture translator fails with error message or crash
& d% z) \  b' O- x1924375 ASDA               NEW_PROJECT   SDA new project path truncated at ellipses
. X5 g$ [* C' l- s0 V+ @1 b# X1900957 ASI_SI             OTHER         axlLicDefaultVersion() in SKILL console crashes PCB Editor in release 17.2-2016 and works in release 16.6# p0 B) s" s* a0 ~0 }  O
1918499 CAPTURE            NEW_SYM_EDITO Text in new Part Editor is always left-justified and justification cannot be changed3 g# R% v8 v" s
1921505 CAPTURE            NEW_SYM_EDITO Error if property name starts with the less than character '<'
9 ?4 V# J( ~, p& G1924273 CAPTURE            NEW_SYM_EDITO Error if property name starts with the less than character '<'* Y, t. i8 Y% T6 G' n$ d
1924332 CAPTURE            NEW_SYM_EDITO Capture reports an error when editing pin numbers where names contain the less than character '<'
8 R0 A/ O$ N+ }/ E# g$ w1934655 CAPTURE            NEW_SYM_EDITO Properties populated in older release show up blank in new Symbol Editor
/ E$ d, V+ b# ]2 ?! T: Y5 j1855851 CAPTURE            OTHER         Crystal Reports not working in release 17.2-2016
8 u1 l, j- l5 a# E1918048 CAPTURE            PART_EDITOR   Unable to modify pin type and shapes for multiple pins simultaneously in new Part Editor
; P6 _& k% N: l1919459 CAPTURE            PART_EDITOR   Part Editor background display color is not consistent when zoomed out/in
. y; `  n! t) i% L) X1920078 CAPTURE            PART_EDITOR   Option needed for updating pin type of multiple pins in the 'Edit all pins' menu
5 w2 z& N- F; w7 t1 R3 x% {1922785 CAPTURE            PART_EDITOR   Cannot place pin array with zero in the suffix in Symbol Editor8 C( o! w1 G2 M7 [
1922831 CAPTURE            PART_EDITOR   Symbol Editor redraws when scrolling with non-default background and when zoomed out
" N7 @( E. H9 t* S( R1923772 CAPTURE            PART_EDITOR   Placing pin arrays results in error
0 N& _. O, C8 V" E+ ], N' R1 d. w+ l1888897 CAPTURE            SCHEMATICS    Capture slowly redraws schematic page5 q: d- Z8 U1 K6 w, I6 T' R
1910087 CONCEPT_HDL        CORE          DE-HDL crashes when adding Current Probe to a design
( u1 B0 j0 S, B; t8 o! ]: L1930364 CONCEPT_HDL        CORE          SIGNAL_MODEL properties not deleted on importing release 16.6 DML design into release 17.2-2016 non-DML design
' E& V* }: z1 i2 r0 Y5 l: Y1920716 CONSTRAINT_MGR     CONCEPT_HDL   Issue with the passing of physical and spacing CSets between Design Entry HDL and PCB Editor
3 m! ?4 @/ }% T9 ?1902591 ECW                OTHER         Flow Manager reports a digital certificate error when launched with Pulse
/ }) @9 y* e! Y- O) k+ p0 _/ Y2 v& l1926029 PCB_LIBRARIAN      GRAPHICAL_EDI PDV Symbol Editor opens to a blank page in release 17.2-2016
& M& j6 y/ ?, i$ _0 z6 q1884694 PSPICE             ENCRYPTION    User-defined library encryption is not working as expected9 I9 n& G3 R, M# N( b' f
1927537 SIP_LAYOUT         ASSY_RULE_CHE SiP Layout crashes when running manufacturing checks on specific designs
+ R8 ?( k7 K3 v8 E$ j7 g# D1878733 SIP_LAYOUT         CROSS_SECTION Layer Function and Manufacture fields in Cross-section Editor are grayed out for soldermask layers in SiP Layout
/ W- v" ^8 N+ S& K0 X/ Z+ \$ W. _1900628 SIP_LAYOUT         CROSS_SECTION Board thickness in Cross-section Editor does not change even after soldermask layers are added
$ S  X) O2 U, P- I) N) e5 a
5 O& f6 R' f- t2 h  B4 Q+ m+ o, i
' z4 X. S* C- f0 U6 z. JFixed CCRs: SPB 17.2 HF040
8 }: S9 T) r; \. _2 E7 F05-27-2018* j$ z* F: I% V8 D& P
========================================================================================================================================================, s1 T+ Z  E2 j% a8 F: }
CCRID   Product            ProductLevel2 Title
4 z* q8 W% ?. e$ S, c: @========================================================================================================================================================
0 L: c& B# w/ C/ l5 j8 D; D; x1924541 ADW                CONF          Designer Server configuration cannot be completed# ?3 o) X, f9 O
1906973 ADW                DBEDITOR      Rename attribute fails to preserve values in affected parts
2 h9 V6 o! {7 P. X1718524 ADW                FLOW_MGR      FM: Find Projects does not find any projects when Project Path contains a period3 y/ F* P, @9 N" H& s
1803310 ADW                FLOW_MGR      EDM Find Project no longer supports dot in the project path
( F' I4 d3 k9 M. N7 U' g1916898 ADW                FLOW_MGR      Flow Manager does not recognize projects with a dot in the path1 b& z& |) J4 p. ~1 H8 E3 F
1887669 ADW                LIBDISTRIBUTI ptfgen displaying Java errors
6 w! N$ o( u4 ?1 ~. V4 G1897991 ADW                LIBDISTRIBUTI ptfgen fails with error LIBDIST-1062 in library distribution., E* S1 J! L/ P* p' \
1915319 ADW                LIBDISTRIBUTI ptfgen should rerun with the -rewrite2db option automatically
& N. j7 O$ }6 I) v/ G1 V% j6 Y1920309 ADW                LIBDISTRIBUTI Java exceptions in the ptfgen log file
, x" _, l! |8 V, `/ g$ r8 _1914706 ALLEGRO_EDITOR     DFM           False Mask to trace DRCs3 w3 \4 x; a" c& y1 _# T
1912290 ALLEGRO_EDITOR     GRAPHICS      Infinite PCB cursor: symbol move results in symbol trail and disappearance of cursor and symbol/ v) }4 w5 f# L, G0 J% f6 O1 F
1927425 ALLEGRO_EDITOR     GRAPHICS      Infinite PCB Cursor disappear while moving objects on layout! G2 y& O6 s; \6 T8 v- @! Q
1908867 ALLEGRO_EDITOR     INTERACTIV    PCB Editor crashes in release 17.2-2016, Hotfix 036 and 0372 d, U( `- c( l# H) d2 V6 T% _
1906116 ALLEGRO_EDITOR     IN_DESIGN_ANA Allegro Integrated Analysis and Checking: Coupling vision shows the influence of voltage net
* [* O( p+ H$ n1 Q1918161 ALLEGRO_EDITOR     MULTI_USER    Symphony crashing and clients disconnecting from server cannot leave session, error applying DBupdate* o) a) u4 S( i# Y) h
1919467 ALLEGRO_EDITOR     MULTI_USER    Random crashes while routing design in Symphony: ]5 L8 ]1 z0 C2 l2 k+ A0 m
1918702 ALLEGRO_EDITOR     SHAPE         Differential Pair vias not voided in a split plane  Y3 R7 {; Y! {6 z( |5 D% R
1905109 ALLEGRO_EDITOR     UI_GENERAL    PCB Editor randomly stops responding in release 17.2-2016 in Linux1 W" U6 R$ Y. B
1882365 ASDA               CANVAS_EDIT   SDA - body changes but not properties when changing version of a symbol0 v$ V1 t5 K7 V5 x: Q$ c: O
1900370 ASDA               CANVAS_EDIT   Version command in SDA should use placeholders from selected version# g6 J' Z0 @8 p" r
1901120 ASDA               CANVAS_EDIT   Choosing a different version of a placed component does not use the property placeholders as per the new symbol' O1 @4 t: d# D( b: _, v6 Z3 U2 L
1907497 ASDA               GRAPHICS      DNI Cross Mark much larger than Components
2 ~. \3 ~4 E* N: ?1895135 ASDA               MISCELLANEOUS Design created in SDA has the cds.lib containing a pointer to worklib
/ h2 ^* c4 ]# l% g4 e# P1895139 ASDA               MISCELLANEOUS Irrelevant warning related to worklib when running checkplus on SDA design
6 B+ O( Q$ S  \3 `4 v9 W' k1920753 CAPTURE            LIBRARY       JavaScript exception reported on opening part with name containing '\' in hotfix 038
1 v- H8 n5 @* u1925848 CAPTURE            LIBRARY       New (QIR6) Symbol Editor has Script error / SR 600037969
1 g6 _- @8 f3 J) t( h" G9 N7 Y  F1916991 CAPTURE            NEW_SYM_EDITO New part/symbol editor ignores grid color set in Preferences8 A3 K& e! B" g
1917090 CAPTURE            NEW_SYM_EDITO New symbol editor goes into permanent pan mode on clicking the middle mouse button7 t1 V* c, T" R' H% c( l
1918041 CAPTURE            NEW_SYM_EDITO Saves As for symbol in library from new symbol editor saving 0 byte files
: l* R4 M9 \' Y# \4 M* R1918497 CAPTURE            NEW_SYM_EDITO Moving multiple items using the arrow keys results in error in new part editor4 ?$ b8 t5 ^! X/ D
1918711 CAPTURE            NEW_SYM_EDITO Unable to do a Save As from a Library part to change the name, N& _! g* I4 l" T* D* a: v
1920889 CAPTURE            NEW_SYM_EDITO Unable to edit symbol with name containing '/'
& ~! I2 u! \9 B* T  X5 ~* e2 [1922123 CAPTURE            NEW_SYM_EDITO Save As for symbol in library from new symbol editor saving 0 byte files! O% W. V* Q& N  G6 d4 |7 ?
1922276 CAPTURE            NEW_SYM_EDITO Space between pin name and pin for names having bar
; G' E1 g0 `5 Q4 ]6 R% m0 |1922282 CAPTURE            NEW_SYM_EDITO JavaScript exception on closing new part editor window using keyboard shortcuts
9 l* E4 Y* R" r6 O; p" b1923526 CAPTURE            NEW_SYM_EDITO Unable to "Save As" in new symbol editor.2 C% m: Q1 ~3 k. y, [
1927262 CAPTURE            NEW_SYM_EDITO The File > Save As command in version 17.2-s038 differs from earlier versions
8 L; Q1 m1 _+ c/ B) O$ R1919322 CAPTURE            PART_EDITOR   JavaScript exception on opening parts and creating new part using right-click* L# K1 {8 d: ?% b6 d9 B
1914183 CONSTRAINT_MGR     XNET_DIFFPAIR ECSet fails to map in PCB Editor but maps fine in DE-HDL
% q. y3 a; N/ d7 O* l7 y' J4 h) |3 r- a1908102 ECW                DASHBOARD     Some lines in Design Dashboard in Pulse are grayed out
. C) l* y  ^: w1914812 F2B                PACKAGERXL    Hierarchical variable not evaluated5 c  i- K2 f; P) G% V3 T4 h. z
1639231 PSPICE             ENVIRONMENT   Remember last location in simulation settings
" M- y! D8 T7 j6 y3 Z1804391 PSPICE             ENVIRONMENT   Libraries with uppercase extension (.LIB) not retained if added using 'Add to Profile'
- l8 x6 u% t; I2 ]; l! U8 U1879915 PSPICE             ENVIRONMENT   Check points cannot be loaded from a directory with space in its name
* X: a: d, o* E4 \- k+ o1695306 SIP_LAYOUT         STREAM_IF     SiP Layout - Stream out issue: Embedded or stacked components using pad reference in more than one layer
, _6 n0 F; m- f9 F% S: q" _7 [+ h. k. Y0 e+ `  `* s; o
5 s0 z5 K2 X8 y
Fixed CCRs: SPB 17.2 HF0392 h4 I' q' Y/ S( Q+ Z* J
05-11-20180 s8 c* L* c3 }
========================================================================================================================================================, N/ X0 g  w9 [! K7 P) z
CCRID   Product            ProductLevel2 Title% a0 s/ m* J5 K4 X6 k! g
========================================================================================================================================================
9 D5 k! M* T$ N/ W1915149 ADV_PKG_ROUTER     OTHER         Auto-connect fails to initialize when rats are selected, but works with bundle0 b- a+ K9 R1 ]
1870109 ADW                ADW_UPREV     Most mandatory properties turned into optional properties following database uprev$ Y3 U8 q  ?: N% D1 N1 O2 m% Q. ?
1758396 ADW                CONF          Server Memory setting in setting.ini is lost if server is re-configured using Conf6 I/ E" h7 |3 {% R! @& c. d
1911591 ADW                FLOW_MGR      Flow Manager does not start on high latency (> 25ms) networks: displays Java Content Disabled dialog+ c* s: K' f6 [3 X0 u% e
1887861 ADW                LIBIMPORT     Library Consolidation reports front2back issues but does not provide information about the issues.( L- u6 D' G2 c
1778977 ADW                REPORT_GENERA reportgen memory setting too high in release 17.2-2016 resulting in launch failure
5 L- {- Y! X- R) R, W) |: l2 D+ @1900422 ADW                REPORT_GENERA Save in reportgen does not save Preferred Part List entry into .rep file
5 {% m& h% s; b4 k1903888 ADW                REPORT_GENERA Report generator not outputting values as expected for PPL field8 B; U( z4 w9 S1 \
1916903 ADW                REPORT_GENERA Reportgen -gui is not producing the expected result! |) e1 t2 a; ^6 Y
1902184 ALLEGRO_EDITOR     DATABASE      Add connect in package symbol crashes PCB Editor when using the 'clearance_view' variable$ t' }. @1 F- w" E0 @: Q1 t
1914793 ALLEGRO_EDITOR     DATABASE      Updating shape crashes Allegro PCB Editor; [' ~5 M9 \5 w1 s
1905138 ALLEGRO_EDITOR     DRC_CONSTR    Max Via count DRC disappears on running DRC update' ^( A3 X6 N/ b# M$ _0 {
1848015 ALLEGRO_EDITOR     MANUFACT      Export Creo View cannot find the webpage on the PTC site
$ o2 \- k# y7 F9 [! J4 B1850553 ALLEGRO_EDITOR     MANUFACT      'File - Export - Creo View' is not working9 K9 ?  l! V* {! h+ r
1853960 ALLEGRO_EDITOR     MANUFACT      PTC Creo Interface link is broken
5 d5 Y& x& ~* \3 U) i% `1862305 ALLEGRO_EDITOR     MANUFACT      PTC Creo interface link is not working
! [! P+ Q  Z/ z5 G" g, N5 y1878682 ALLEGRO_EDITOR     MULTI_USER    Delay in Symphony server session when server is started from Allegro PCB Editor- Z% v! W4 R+ ]) I! R+ B  q
1890108 ALLEGRO_EDITOR     MULTI_USER    Database rejections in Symphony
& l; i& c% g" Z  v/ M1887331 ALLEGRO_EDITOR     NC            Milling (NC route) in Gerber tools is not the same as what it is in the board.+ A' _& e4 n9 b3 ?" C
1898179 ALLEGRO_EDITOR     RAVEL_CHECKS  PCB High-Speed option required for high-speed rules when Venture license is selected! X( H: |  w# ~! ~/ w! b
1461142 ALLEGRO_EDITOR     SHAPE         Pin with nearly-tangent via fails to generate void in dynamic shape, results in short.
# Q( D0 h, [# t1863467 ASDA               CROSSPROBE    Highlighting all parts in PCB Editor does not highlight all parts in SDA! w; M3 g& {6 H, _
1910974 ASDA               CROSSPROBE    Cross-probing between SDA and PCB Editor does not work
( t- X8 C" P! m: k! W1904440 CONCEPT_HDL        CORE          SPCOCD-577 error on migrating from release 16.6 to release 17.2-2016
- t1 U4 K, m) [  P( Q! L; B1909611 CONCEPT_HDL        CORE          DE-HDL stops responding on running '_movetogrid' and clicking 'No') v# V: D' r, v0 {  D! j* K( d( G3 W) a
1808743 CONCEPT_HDL        PDF           Inconsistent display of Publish PDF hyperlinks
4 m& a' m; d& C4 w( r8 B( O1894868 CONCEPT_HDL        PDF           XREFs getting clipped in the Published PDF
- y( \, n6 P4 v% q& _) V1911676 CONSTRAINT_MGR     CONCEPT_HDL   DE-HDL Constraint Manager crashes on selecting ECSet and then creating pin-pair option% f! A+ e7 ?: Q9 A
1913968 CONSTRAINT_MGR     CONCEPT_HDL   Match Group pin-pairs are not created on applying ECSet to differential pair
" F* ~% a  M4 i, {/ b; ]1899638 CONSTRAINT_MGR     XNET_DIFFPAIR Differential pair buffer models are extracted differently in release 17.2-2016 and release 16.6
( N7 `1 R1 e) ~! T* X- B1914116 ORBITIO            ALLEGRO_SIP_I Unable to import OrbitIO file to SiP Layout
# A0 B) b1 d" s1896487 PCB_LIBRARIAN      GRAPHICAL_EDI Use lower-case characters for notes and pin text in New Symbol Editor' w3 Z+ @% e8 e, \
1898008 PCB_LIBRARIAN      SYMBOL_EDITOR Styling is not available for custom shape and pins.7 S: L: q3 Q* |" j! L
1644787 PSPICE             FRONTENDPLUGI PSpice Model Search window does not show complete library path
+ t$ \( V5 q8 }0 C  ~  p1785939 PSPICE             FRONTENDPLUGI PSpice Part Search library browser should display path of the library directories
3 ~& o& M' J( _+ V6 S2 q) C1855867 PSPICE             FRONTENDPLUGI PSpice Model Search window does not show complete library path
9 k) F# f% {$ Q* ~- a1887016 PSPICE             SIMULATOR     Pseudotran should always be invoked first time in case autoconvergence is ON
. E1 }$ g0 P6 N+ @1895752 SIG_INTEGRITY      OTHER         Layout Cross Section: Wrong Differential Impedance calculation (0 ohms) in RHEL Linux 7.1 or later versions
- o& U8 U& k+ x# z4 C1895759 SIG_INTEGRITY      OTHER         Cross Section does not calculate correct differential pair impedance in Linux CENTOS 7 and gives 0 value4 ~, q2 p! y6 ^
1909257 SIP_LAYOUT         INTERACTIVE   Error 'E- (SPMHGE-639): Copying component with bond wire is not allowed' when copying SMD symbols
! a' L( U( }5 q* m9 k1900970 SIP_LAYOUT         SHAPE         Shape does not void around SMD Pins and Vias inside pad, @% L3 |1 J3 F$ ?
1885496 SIP_LAYOUT         SYMB_EDIT_APP Pin Numbering: different results for release 16.6 and 17.2-2016 for the same case.( y7 a: g7 E5 I5 l9 t! X
1907796 SIP_LAYOUT         SYMB_EDIT_APP SKILL commands fail to change pin number in SiP Layout
! X- K. I5 _6 Y; ~) S0 e# f4 b0 p1887703 SIP_LAYOUT         WIREBOND      On trying to add wire bond to a die, SiP Layout crashes displaying a restart message/ o1 r' R3 o3 I2 F# l8 `+ M
1903081 SPECCTRA           LICENSING     PCB Router is failing in Linux 7.1 in release 17.2-2016
0 j& V. R1 g- J1721606 SPECCTRA           ROUTE         PCB Router stops responding on exit if opened in the stand-alone mode
4 ~% d3 _" ~! G. @+ e1 M! A; M1844366 SPECCTRA           ROUTE         Allegro PCB Router will not exit
& U$ h9 _8 j# m( g- R* ^  C1873716 SPECCTRA           ROUTE         PCB Router does not close if opened from Allegro PCB Editor or in the stand-alone mode. l! K/ {* X4 \. m) W6 C/ v/ f
1907703 SPIF               OTHER         PCB Editor crashes on choosing 'File - Export - Router' in release 17.2-2016/ b: M1 I3 x6 G! t7 p
1889059 VSDP               DIEEXPORT     Incorrect pin location if bump cell origin is not at lower left for rotation other than R0" a0 t; b# y) l3 F
9 q, b$ f$ R; x2 n8 j
- D# I/ ]! j+ M" l# z
Fixed CCRs: SPB 17.2 HF038
+ l% |$ {8 H2 E! C04-27-2018$ }3 l. `4 {/ M2 J
========================================================================================================================================================: D: y, H: t- D) O( Z- w, Y
CCRID   Product            ProductLevel2 Title& n( a/ Y; P6 J( g# E3 U; \' k
========================================================================================================================================================" S4 E  ~6 J  e6 o) p- [( S
1861616 ADW                TDO-SHAREPOIN Team Design Option requires Allegro_ECAD_Collab_Workbench license feature
" L* f+ T; O9 P* K) t: @  \1784170 ALLEGRO_EDITOR     3D_CANVAS     Allegro 3D Canvas does not show the flex zone thickness correctly% }6 W) z, f* n+ a
1801053 ALLEGRO_EDITOR     3D_CANVAS     Moving component in 3D Canvas does not move the pads# U3 I: T, {5 W; C$ i% X0 j
1805038 ALLEGRO_EDITOR     3D_CANVAS     Soldermask and drill not refreshed when component is moved in 3D Canvas, or on the board with Canvas open. }2 p1 Z+ `. J( f
1808579 ALLEGRO_EDITOR     3D_CANVAS     3D Canvas displays annular ring incorrectly
7 i' |# N0 @0 M3 W) s1816732 ALLEGRO_EDITOR     3D_CANVAS     Mismatch in shape width between board and 3D Canvas
* T1 C! H+ Y, m! |/ a1822778 ALLEGRO_EDITOR     3D_CANVAS     3D Canvas does not display nets when selection is done through click drag
6 J# R/ w& Z8 Z- `% q( J: y1838129 ALLEGRO_EDITOR     3D_CANVAS     User is not able to create a pastemask layer that is visible in 3D Canvas2 K3 B, Z$ v$ [3 U$ `/ x, C& M; A
1842911 ALLEGRO_EDITOR     3D_CANVAS     Etch shapes not visible in the 3D Canvas when invoked from a symbol drawing
. D3 B7 g8 a( H  b) o1849380 ALLEGRO_EDITOR     3D_CANVAS     Mirrored components placed in flex zones are not displayed in the 3D Canvas
7 H& h' Q# m0 m( A1851898 ALLEGRO_EDITOR     3D_CANVAS     STL export from 3D Viewer scales it up by 100
4 K# }( }, O5 f' }# m1853378 ALLEGRO_EDITOR     3D_CANVAS     The new interactive 3D Canvas has a display issue with the off-centered drills.
8 e  r0 A+ {, I: G1859713 ALLEGRO_EDITOR     3D_CANVAS     PLACE_BOUND shape with package_height_max and package_height_min set displayed incorrectly in 3D Canvas6 p" e: Z5 c. H
1880073 ALLEGRO_EDITOR     3D_CANVAS     Design Outline is not displayed correctly in 3D Canvas3 O& q* ~* _7 h0 Y4 N7 x$ m' T
1880338 ALLEGRO_EDITOR     3D_CANVAS     Step Model missing in interactive 3D canvas.
$ b" E: O! ]5 [1 p2 B6 }  i1881889 ALLEGRO_EDITOR     3D_CANVAS     Changing the color of STEP model in STEP Mapping Window does not display this color in 3D Canvas.% X3 u0 @7 p. D" K* J
1889861 ALLEGRO_EDITOR     3D_CANVAS     3D Canvas swaps padstack from Bottom to Top
9 m: W( B: t- q# t1830749 ALLEGRO_EDITOR     ARTWORK       Gerber 4x and 6x output do not fill the shape1 |+ u& ~% k9 n0 C0 ]4 a* d
1848514 ALLEGRO_EDITOR     COLOR         axlVisibleDesign does not interact with wirebonds
: a& o2 s1 ]) w) M1837388 ALLEGRO_EDITOR     CROSS_SECTION Cannot add solder mask to the site layer mask file
4 g/ L$ P- r- a& Q* O1859797 ALLEGRO_EDITOR     CROSS_SECTION The Report only option does not work when choosing Setup - Cross-section - Import - IPC2581
! b3 y$ v' y' `) k  x% R1877858 ALLEGRO_EDITOR     CROSS_SECTION Dynamic Pads Suppression option is not working correctly, W1 i* ?% Z* D: x- R
1880093 ALLEGRO_EDITOR     CROSS_SECTION Unused Pad Suppression options are not working correctly and are reset on opening cross-section8 D" o0 `6 a$ o/ N6 Y3 A- p# ~
1886283 ALLEGRO_EDITOR     CROSS_SECTION Unable to turn on 'Dynamic Unused Pads Suppression'
' C: _0 B$ b: B1 k+ _8 X1890959 ALLEGRO_EDITOR     CROSS_SECTION Dynamic Pads Suppression option is not working correctly1 @; c4 Z8 p* ^3 r9 q
1900397 ALLEGRO_EDITOR     CROSS_SECTION Dynamic Unused Pad Suppression option in Cross-section not working at one go.7 A' @8 f! v( I, t" v& C2 z6 R
1905315 ALLEGRO_EDITOR     CROSS_SECTION 'Dynamic Unused Pad Suppression' cannot be turned on.
! }2 J; r8 J9 k# z3 s/ _1861406 ALLEGRO_EDITOR     DATABASE      Refresh symbol for flex zone not mapping padstack layers correctly0 x5 b1 h3 C7 I. I
1877132 ALLEGRO_EDITOR     DATABASE      Fail to open #Taaaaed17598.tmp file and save database6 |' r' I( j+ Q- b
1883747 ALLEGRO_EDITOR     DATABASE      PCB Editor crashes on stackup modification
0 I4 ^" c0 e; B$ A6 _1860238 ALLEGRO_EDITOR     DFM           Applying a DFF constraint set closes PCB Editor instantly* Y1 R( V2 ?- W# t
1872780 ALLEGRO_EDITOR     DFM           DFF false pin to via DRCs: Copper Spacing, SMD pin Pad to Thru Via pad. n8 Z: W' |) c- M/ X2 e' d9 L5 |/ \3 r
1823912 ALLEGRO_EDITOR     DRC_CONSTR    Thru pin to Thru pin DRC between Symbol Pin to Mechanical Hole (with NO regular pad)
5 c& D) }- k( ]) t# y  k6 _" L1828168 ALLEGRO_EDITOR     DRC_CONSTR    Upgrading from release 16.3 to 17.2-2016: Differences in spacing constraints
6 c6 H8 C8 L2 {' I& i' ~1844780 ALLEGRO_EDITOR     DRC_CONSTR    Mechanical Pin to Shape Air Gap value is reduced when updating shape& N2 ?1 B$ g- C7 m
1845011 ALLEGRO_EDITOR     DRC_CONSTR    When upgrading from 16.6 to 17.2, Spacing constraints for shape to mechanical pin not being resolved properly/ Z' F8 s+ @; w2 I9 ~9 y/ N8 W
1861548 ALLEGRO_EDITOR     DRC_CONSTR    Inconsistent Micro via to Micro via drill to drill overlap DRCs& V+ k* `: B' k1 a- g* Y0 v1 g  C' f
1862281 ALLEGRO_EDITOR     DRC_CONSTR    Mechanical Pin/hole to Shape spacing too small
2 ]& f" J2 Q! c( `6 c; t4 o! R: Q1 F1887145 ALLEGRO_EDITOR     DRC_CONSTR    Mechanical pin to conductor spacing setting is overriding constraint region in release 17.2-20166 J2 g' i. |* J, P" A8 G. X$ Q4 n
1893012 ALLEGRO_EDITOR     DRC_CONSTR    Shape voiding not taking the shape to hole spacing rules for NPTH: `) S6 |8 x5 [, A8 Q
1906840 ALLEGRO_EDITOR     GRAPHICS      Context menu stays when PCB Editor is minimized.
  ~% \  i7 r' s- [  p4 Y1738624 ALLEGRO_EDITOR     INTERACTIV    'Invalid Sector' error when saving psm file for symbol that has die pads, which are copied
# T8 Z0 Z( f& x1800741 ALLEGRO_EDITOR     INTERACTIV    Search in User Preferences Editor is giving incorrect results: [5 G$ C1 s; e9 Y2 J1 Y, L  {
1812530 ALLEGRO_EDITOR     INTERACTIV    PCB Editor crashes when opening a file that is in an unsupported format
, X2 ]3 G: \8 X4 j$ L# P& g1812570 ALLEGRO_EDITOR     INTERACTIV    PCB Editor hangs when an invalid pin number value is specified as the rotation point in the symbol preselect mode. H# K/ L0 G2 m4 h
1826819 ALLEGRO_EDITOR     INTERACTIV    'Route - Resize/Respace - Align Vias' menu is not available. [! j" l& [, ]# J1 e
1842645 ALLEGRO_EDITOR     INTERACTIV    Via align command is missing from the menu path4 d# ?) ]7 z# f* u) u
1845748 ALLEGRO_EDITOR     INTERACTIV    With 'Shape - Change Shape Type' enabled, changing visibility reverts the Shape Fill selection to dynamic copper.
# N' o! T% ^1 r* V2 z1849700 ALLEGRO_EDITOR     INTERACTIV    Add the reason for generating DBFIX_PAD, to the dbdoctor.log.
- [% s( a, N5 h. o, n' w, h1860934 ALLEGRO_EDITOR     INTERACTIV    Auto-Paste environment variable is not working as it should
! w( `+ D( ^2 A" X) h0 E1861928 ALLEGRO_EDITOR     INTERACTIV    Provide a Persistent snap pick option for Display - Measure
( I1 ?0 z: ?7 o& E1864238 ALLEGRO_EDITOR     INTERACTIV    Shape place rectangle issue: Dimension of placed rectangle changes on cancelling action
* l" c7 M( \* X( a( v; c8 O1877026 ALLEGRO_EDITOR     INTERACTIV    Filled rectangles on ETCH/TOP and ETCH/BOTTOM are not getting copied
9 e  _* C' s" {8 P9 A, S% F1881637 ALLEGRO_EDITOR     INTERACTIV    Radius of Shape changes when trying to place circle using Place Circle mode." G9 r- i+ V& S6 e  z1 y. X  ~
1883032 ALLEGRO_EDITOR     INTERACTIV    Find by Query does not find all padstacks in a symbol drawing/ E  }3 j( {/ t. X8 k
1855248 ALLEGRO_EDITOR     INTERFACES    The Technology Dependent Footprint command returns an error; `1 X# r4 ]( o0 U  |
1885716 ALLEGRO_EDITOR     INTERFACES    Increase supported STEP model size to enable the use of models larger then 500MB
; Z+ C9 g; r+ d8 |1860835 ALLEGRO_EDITOR     MANUFACT      Display a message when backdrill_max_pth_stub is defined for vias or pins only0 k4 y# f6 E! T) ]* u7 a
1869528 ALLEGRO_EDITOR     MANUFACT      Backdrill out of date when deleting Teardrop and Sliding cline with Teardrop* s8 V7 m* Y) h' q
1885672 ALLEGRO_EDITOR     NC            NC drill is creating false backdrills when repeat code is turned on in release 17.2-2016
% o+ c5 `/ L( r4 B# n+ H" B# F1895084 ALLEGRO_EDITOR     NC            Padstacks with backdrill data trigger backdrill out-of-date even if the board is not set up for backdrilling/ A% I. m3 [: F) _+ Z9 O/ N
1837514 ALLEGRO_EDITOR     PAD_EDITOR    Offset is not consistent for keepout and mask layers in padstack editor.( n  I0 Z& E6 h$ k( i8 r
1842902 ALLEGRO_EDITOR     PAD_EDITOR    Scrolling through the .pad files in the Library Padstack Browser displays Error(SPMHA1-161)6 _7 G( Q2 N. O4 b# \
1846504 ALLEGRO_EDITOR     PAD_EDITOR    COVERLAY_TOP definition lost while opening and saving a 16.6 pad in 17.2 padstack editor
9 h% a* S6 C* R1879453 ALLEGRO_EDITOR     PAD_EDITOR    The 'Y' tolerance in the Padstack Editor does not update when changing the units of the padstack.
4 `/ M/ ]7 L; r1 c1 f( {1805202 ALLEGRO_EDITOR     PLACEMENT     Place via array adds via on differential pairs incorrectly9 s, A  M1 s( X3 W6 [
1806675 ALLEGRO_EDITOR     PLACEMENT     Place - Manually - Quickview displays the Assembly Top details only
; S2 Z# f4 S% L5 E+ K3 a1835177 ALLEGRO_EDITOR     PLACEMENT     Can place symbol even after cancelling copy by choosing 'Oops' from pop-up0 g! n" Y( D' t* J
1846892 ALLEGRO_EDITOR     PLOTTING      PCB Editor Export PDF does not show lines correct for certain component
* }9 _1 V$ s" ]" ^) E1 j' c0 d  o1006328 ALLEGRO_EDITOR     SHAPE         Static shapes should void around corners as dynamic shapes do$ Z* w: W2 g% W
1033326 ALLEGRO_EDITOR     SHAPE         Cannot compose lines to shape; s6 r4 v  `$ {8 O5 i/ r( K4 _0 \$ A9 A
1045089 ALLEGRO_EDITOR     SHAPE         Dynamic shape voiding is inconsistent for solid and xhatch shape fill type- H" q0 q+ X, o8 }" z
1069959 ALLEGRO_EDITOR     SHAPE         Compose shape crashes PCB Editor
) |8 G, G% f0 _& Z' T" j3 M" w1085907 ALLEGRO_EDITOR     SHAPE         Pad does not get thermal connections to shape if outside of the shape outline by more than DRC spacing.
$ v% x9 p3 {: P. J1 \3 @+ S1143563 ALLEGRO_EDITOR     SHAPE         The pin void inline clearance does not seem to dynamically update the shape and requires a 'force update'.: o9 _- }/ F9 m1 Q7 a( ~) ?
1243688 ALLEGRO_EDITOR     SHAPE         shape_rki_autoclip fails to clip shape to route keepin  S2 G* N1 I( l6 P* s# y
1269069 ALLEGRO_EDITOR     SHAPE         Shape void not working properly in release 16.5 hotfix 054
1 c9 y) p3 P  I1327755 ALLEGRO_EDITOR     SHAPE         Need the ability to nest dynamic shapes on different nets partially or entirely$ d/ w5 \9 e) D9 ~' J6 _
1417394 ALLEGRO_EDITOR     SHAPE         Shape not updating correctly
) E# m2 C& z, J4 ^! J/ W) q1430742 ALLEGRO_EDITOR     SHAPE         When adding fillet to an irregular pad, the fillet might not be added or be strangely shaped
& F" @( ]6 ?. _7 s3 }3 ?1750760 ALLEGRO_EDITOR     SHAPE         Shape to Route Keepout DRC for a void that meets route keepout
4 c* [+ R8 Q7 R" P6 t( Q' v1793898 ALLEGRO_EDITOR     SHAPE         Add teardrops fails to add anything with different settings  H) L! O& _  {1 h, u9 b/ W9 M
1811662 ALLEGRO_EDITOR     SHAPE         'show measure' gives incorrect air gap value between two pins
/ D( A4 O* A5 h5 H+ P2 C% t8 R1820901 ALLEGRO_EDITOR     SHAPE         The pins on adjacent layers are voided as Rounded Rectangle instead of Rectangular as defined in padstacks+ V- g2 ?$ K; f  u/ @* ]) @; b
1829570 ALLEGRO_EDITOR     SHAPE         Display measure airgap value is very large
+ h: M6 ]' z9 o% D4 ]1858696 ALLEGRO_EDITOR     SHAPE         The via to the edge of the board is not connecting to shape even with the PAD_SHAPE_TOUCH_CONNECTION property added
9 \& {  C+ y+ Z& z5 `1873384 ALLEGRO_EDITOR     SHAPE         Boolean AND operation returning nil
6 [* c6 j* o3 L% K1873860 ALLEGRO_EDITOR     SHAPE         Copper shape does not respect route keepout
* ~1 Y7 M' z+ t" x, [1889312 ALLEGRO_EDITOR     SHAPE         Shape voided for net vias on adding 'PAD_SHAPE_TOUCH_CONNECTIONS' when enabling via suppression
1 j1 E: ^2 i8 t: a1 a8 N, P& t1890702 ALLEGRO_EDITOR     SHAPE         Not able to add teardrop in release 17.2-2016
9 @2 a4 `$ L# x7 z3 n8 q1892692 ALLEGRO_EDITOR     SHAPE         Thermal relief connections being added to static shapes present in the void inside Dynamic Shapes
1 L" k7 C, B7 y( f- B1893492 ALLEGRO_EDITOR     SHAPE         'merge shapes' results in moved void! v4 v6 p9 h% u, Q
1896543 ALLEGRO_EDITOR     SHAPE         Same net pin will not add thermal connection to shape if it is a rotated slot in the symdef3 {7 T4 P% R1 Z, d
1897645 ALLEGRO_EDITOR     SKILL         axlCNSGetSpacing() returns nil if active class is non-etch.
( m; Z4 X) l# @- D$ Y" z1822364 ALLEGRO_EDITOR     UI_FORMS      Design Parameters dialog disappears if prmed is called while show measure is active
* v0 H" A, ~% C8 j2 I1834395 ALLEGRO_EDITOR     UI_FORMS      Setup menu of OrCAD PCB Editor is missing the Anchor 3D View command# {/ ^$ G% A1 @) {, d5 ?5 c
1838941 ALLEGRO_EDITOR     UI_FORMS      Anchor 3D View command is not available in OrCAD PCB Editor Setup menu
" U# e0 s+ o/ u. `% E1716433 ALLEGRO_EDITOR     UI_GENERAL    Alias keys do not work until mouse scroll key is activated; T* w6 L& d0 v; {
1721761 ALLEGRO_EDITOR     UI_GENERAL    During manual placement of symbols, hovering over symbols does not highlight them% Q6 r- T* ?2 L- m
1732915 ALLEGRO_EDITOR     UI_GENERAL    Alias does not work in release 17.2-2016 when switching windows8 d5 i8 k( `( q# l" `5 k7 e
1770723 ALLEGRO_EDITOR     UI_GENERAL    Funckey does not work if focus is not on canvas in release 17.2-2016
' }/ n, W+ u4 m3 _* s* x5 T1793839 ALLEGRO_EDITOR     UI_GENERAL    Function Key does not work if a form is opened by a previous command/ A' N$ H+ r6 Q- [2 C/ R1 d
1813961 ALLEGRO_EDITOR     UI_GENERAL    Inconsistent file formats available when saving reports) j  n; z8 C1 P/ |; e8 i
1816716 ALLEGRO_EDITOR     UI_GENERAL    Shortcut not working when using working layer with 'add connect'
4 k: l; ~* u  J; b1 E" r1864321 ALLEGRO_EDITOR     UI_GENERAL    Funckeys not being registered after focus has moved to other window and back again in PCB Editor
: c* A7 R( J) K, l1865010 ALLEGRO_EDITOR     UI_GENERAL    PCB Editor does not get focus when clicking shortcut after switching from any other program or application
3 N5 L; [, ~8 ]+ _1868708 ALLEGRO_EDITOR     UI_GENERAL    Allegro PCB Editor, funckeys stop working intermittently in release 17.2-2016, hotfix 032
$ x/ t) I& P# y0 z+ z# b0 J1869745 ALLEGRO_EDITOR     UI_GENERAL    Allegro 3D Canvas window becomes active on pointing at minimized icon on taskbar0 m. d( y  ~. g( K# z
1869860 ALLEGRO_EDITOR     UI_GENERAL    Hotkeys no longer functional on switching from PCB Editor to another application and then back again
# b6 \. Q: r- y/ j1870744 ALLEGRO_EDITOR     UI_GENERAL    Need html extension added to Save pull down menu.$ `% w% ]- K5 u" \% N& C9 u
1870996 ALLEGRO_EDITOR     UI_GENERAL    If you switch from one active window to other, hotkeys stop working
: k2 ~' ~) N: N' |# i1883507 ALLEGRO_EDITOR     UI_GENERAL    Hotkeys stop working after Allegro PCB Editor UI window is opened: z9 F+ ]8 P8 s; `; }; Q$ R9 F9 r
1886981 ALLEGRO_EDITOR     UI_GENERAL    Focus lost from layout when switching between PCB Editor and Capture. ^! P( D' m  C: w/ f  D; ~
1887519 ALLEGRO_EDITOR     UI_GENERAL    Release 17.2-2016, hotfix 034: Shortcuts defined using funckeys not working correctly
: \/ N* X4 `: U1887660 ALLEGRO_EDITOR     UI_GENERAL    Alias does not work in release 17.2-2016 when switching windows.
% v, Q4 V& F7 w: D) s1891204 ALLEGRO_EDITOR     UI_GENERAL    PCB Editor crashes if SKILL form is closed using the Close icon ('X'). ?% x) Q% \; u2 v
1898059 ALLEGRO_EDITOR     UI_GENERAL    Funckey commands are not working consistently in release 17.2-2016
$ Y( `! r5 T; H3 A$ H0 H, [5 z1902322 ALLEGRO_EDITOR     UI_GENERAL    Cannot use funckey commands when cross-probing
; u0 Z* t8 K$ D1905906 ALLEGRO_EDITOR     UI_GENERAL    Issue with keys and focus when navigating between windows
+ E# j' z( |9 \. o1913768 ALLEGRO_EDITOR     UI_GENERAL    Uppercase funckey shortcuts do not work* |% |6 G- i  M2 \0 `! Q  m6 E/ ~
1751586 APD                OTHER         axlGetMetalUsageForLayer() for etch returns value including pins and vias
+ @6 B! }' Y- E. p1863241 APD                SHAPE         Fillet is left on the T-Point without Cline(center) connection.& ?1 s; D2 {- K+ `
1894438 APD                STREAM_IF     APD/SiP Layout: Export rounded features as circumscribed and not inscribed polygon in GDS
4 p) I5 p- J; Y5 `# p' L* Z/ U1812699 ASDA               AUTOMATION    Enhance the performance when extracting data from SDA, using TCL functions
% w0 A$ v4 q: O1 u8 y1 o( |! k' [1863436 ASDA               CANVAS_EDIT   alignment guides are not displayed when placing or copy a part, only when moving. They are most needed during placement
5 K1 A- H8 @6 y) z8 v! [& Y8 Z2 t( Z1863445 ASDA               CANVAS_EDIT   Dark theme blue text in docked CM needs to be of a different color: difficult to read  [- g: l0 s: ^9 T% h) W. D" @8 I
1802111 ASDA               DARK_THEME    Dark theme in SDA should also change the border line color and text color of grid references: they are still black
# C4 D+ o. w9 b8 r. i1869951 ASDA               EXPORT_PCB    File browser button in Export to PCB Layout flashes graphics of the window behind the form2 c' y+ A' _/ ?3 J" x# c+ D
1845831 ASDA               FORMAT_OBJECT Width of the twisted pair of wire should automatically be set to 6, otherwise it is not drawn correctly
) q  L4 _9 Z. p0 [1879914 ASDA               INTERNATIONAL Using French Keyboard cannot use the . (point) delimiter to set VOLTAGE property value  p7 {1 g3 `6 I; h2 K' D
1865753 ASDA               MISCELLANEOUS Inconsistent and non-ideal behavior in SDA product choice dialog, small box, hard to check unlike the bottom box
& [, R# S  N( J$ Z; |/ C" ^( j1863457 ASDA               PACKAGER      Unset all user-assigned references globally
8 o! l: q# T. n  {1889301 ASDA               TDO           SDA TDO Crashes when switching to/from Offline mode% Q0 c- K$ B% v5 s
1823203 ASDA               VARIANT_MANAG Variant setting part to not present does not do anything
) f9 d' B, G+ _) h1823992 ASDA               VARIANT_MANAG Variant Editor fails to read netlist if a net is named NC. U' `% F; D. _
1863451 ASDA               VARIANT_MANAG variant mode can select multiple parts to add to variant but can't select multiple parts to hit reset2 M) b& U: J1 i
1863455 ASDA               VARIANT_MANAG Cannot resize any panels in the Variant mode- D! f7 s) \3 [# w3 Y- k1 T' s
1874952 ASDA               VARIANT_MANAG Letter I in the alternate part icons in variant spreadsheet should be  white for readability
% ~# w8 Q- I+ S$ g3 D( ~1 K) |1878401 ASDA               VARIANT_MANAG SDA Variant Display - DNI marker color switches between black and red& r! _$ i' Z2 i, r* @
1877239 ASDA               WORKSPACE     SDA DRC window is hidden if undocked and minimized
) J, \% b$ |( Z; ~) s6 _4 v1809605 CAPTURE            LIBRARY       Part has pins in the incorrect order in the Connectors library
- z: o7 j. {% T+ u1 h; z3 q1638693 CAPTURE            OTHER         Capture Footprint Viewer not showing footprint.9 k$ n+ U* _1 J+ K& w& {
1873612 CONCEPT_HDL        COPY_PROJECT  Copy project causes nets to be added to net groups and ports - fails to package due to mismatch
; |, x& q) [! D* n+ ~1779289 CONCEPT_HDL        CORE          Adding a component and wire and saving the design results in a 'Connectivity save failed' error
, ]5 G; d3 L, Q  d1 ?1878719 CONCEPT_HDL        CORE          Cannot enable or apply block variants at the top-level in a hierarchical design.5 A5 x6 ^( t. L& e4 Z1 G
1865480 CONCEPT_HDL        OTHER         'partmgr -ptfMode shoppingCart' cannot output cell name with project ptf file into shoppingCart.xml% O: V, U0 b& F$ w
1829966 CONSTRAINT_MGR     CONCEPT_HDL   DML independent flow: Export Physical audits missing signal models in release 17.2& \! h% A0 n# b9 ~6 _& E' Y7 }
1904458 CONSTRAINT_MGR     ECS_APPLY     'Audit - ECSets' crashes DE-HDL in release 17.2-2016, Hotfix 037
  ]3 a' F+ O, q1798269 CONSTRAINT_MGR     OTHER         Script changes '-' in layer name to '_'
: u/ }6 q, ]/ w  B' f3 H0 {. @2 j6 U, [1835520 CONSTRAINT_MGR     OTHER         Cannot add members to netclass name with parenthesis) D1 z' q  t8 U
1896638 CONSTRAINT_MGR     OTHER         Constraint Manager worksheets jump abruptly
. E8 k) K: g: \1801938 CONSTRAINT_MGR     UI_FORMS      Add To Netclass window: Focus not on ClassSelection* }$ [: @; R9 W$ A' j+ u
1854060 CONSTRAINT_MGR     UI_FORMS      Using the tab key in the Manufacturing workbook jumps a cell. F3 c6 h0 t* u# J% Z# X* L6 ]
1881832 ECW                ROLES_PERMISS Adding Users in SSO environment using PS is error prone6 X! ]! R7 R4 d) s* Y3 q) w
1864870 F2B                BOM           Incomplete BOM report generated
" i& _+ R6 ]9 v1846578 PCB_LIBRARIAN      GRAPHICAL_EDI radio buttons and clickable buttons are hidden in the UI for verify rules( |4 \" x5 f% I" N  P' u7 C4 O/ w
1854080 PCB_LIBRARIAN      METADATA      con2con needs to support special characters in Primitive Name; n" I: H7 `9 s/ N' I/ @; V
1796377 PCB_LIBRARIAN      SYMBOL_EDITOR Unable to move pins using arrows when symbol is opened in Symbol Editor
' A3 i+ y" E* d# O3 F0 q4 n1839692 PCB_LIBRARIAN      SYMBOL_EDITOR Properties tab grayed out in Symbol preview window4 x! K. d5 [' r( |# G% X
1865657 PCB_LIBRARIAN      SYMBOL_EDITOR Cannot change symbol properties using the General tab
$ z; f6 [8 S: T; E, Y. Q! Q  r1906888 PCB_LIBRARIAN      SYMBOL_EDITOR Properties button in Symbol Pins tab of the Symbols section is inactive.' k4 ?2 [" h4 w; z$ T
1891248 PCB_LIBRARIAN      SYMBOL_EDITOR Copy and mirror arc drawing object in the new Symbol Editor results in wrong arc on opening symbol in DE-HDL9 a' W/ V: @4 k
1908381 PDN_ANALYSIS       PCB_STATICIRD Allegro PCB PDN Analysis crashes after performing analysis and saving result in release 17.2-2016
/ U0 B+ d' N0 B) `1825087 PSPICE             AA_OPT        Graph view menu does not appear when we use 'Curve Fit' in Optimizer.0 m  Q& M7 d, ^  h
1808091 PSPICE             ENVIRONMENT   'orSimSetup' crashes when 'Restart Simulation' is selected
2 |" C! L4 b3 u! c7 \/ K1 k1811782 PSPICE             ENVIRONMENT   Setup Simulation Profile no longer enables Advanced Markers when appropriate
, |, N; z) z( \1834147 PSPICE             ENVIRONMENT   PSpice Part Search library icons not displayed if product is installed in the Program Files folder in release 17.2-2016# L' l9 U' n- e, I  j+ F5 Q: A- Z( {- {
1841992 PSPICE             FRONTENDPLUGI Getting a blank Error dialog while adding a marker
4 H# x, C$ `4 y* s* T1858574 PSPICE             NETLISTER     PSpice simulation: Some models cannot be used after upgrading to release 17.2-2016$ M. J, S6 a! Y/ |  W- R1 N9 o9 l
1865022 PSPICE             NETLISTER     The division operator is not recognized by PSpice in DEV expressions in release 17.2-2016
1 k! Q0 l! @7 r2 a1677119 PSPICE             PROBE         PSpice crashes when plotting simulation message summary$ q( x6 b4 t' D: `& f9 X
1837046 PSPICE             PROBE         On Windows 10, PSpice crashes on clicking Yes to see message1 P% ]+ z& n( v2 H& D+ A  e
1879387 PSPICE             PROBE         PSpice crashes when we choose to plot simulation message summary
$ m8 r! ~. r0 G( u  Z) h( h6 _1842231 PSPICE             SIMULATOR     Wrong results in PSpice Advanced Analysis for DC Sweep Analysis
1 C: G8 [8 R! @' P) {4 b1843446 PSPICE             SIMULATOR     Distribution type is not showing under Assign Tolerance window for transistor9 E- o0 F6 F7 i* y% {8 i2 K
1872630 RF_PCB             ROUTING       Transition taper length does not work in route- Add RF trace
) t& z7 m2 ^" I1872636 RF_PCB             ROUTING       Inherit Width parameter in Route -RF trace only uses width of one side0 d4 @+ V' Z  L4 H+ Z0 ]
1872644 RF_PCB             ROUTING       Regression RF trace: change in trace width not retained while routing- }  X2 _% L1 W, s' d0 \
1901201 SIP_LAYOUT         EXTRACT       extracta is not retaining custom layer names/ V4 i" M0 {3 E& z2 t7 @; }- M
1813380 SIP_LAYOUT         OTHER         Layer Compare is not adding the required shapes
! a" n" @& Q( O' L1852762 SIP_LAYOUT         OTHER         Error generated in Package Design Integrity Check when adding soldermask to my design
" G' F( \. V" j$ a( S1886847 SIP_LAYOUT         REPORTS       Incorrect metal area in metal usage report, c% r4 Y& ~1 `9 S% Z' Q
1491315 SIP_LAYOUT         SHAPE         Dynamic shape filling exceeds the shape boundary on running 'create bounding shape' command
! L2 d! g. @0 D+ P* O1853989 SIP_LAYOUT         SHAPE         'Shape - Select' and then' Move' from pop-up with ix 500 iy 0 moves shape diagonally
3 x, ~& B, G# C! y; P# c1868509 SPECCTRA           PARSER        Autorouter takes long time to invoke  h5 D3 K6 i# X6 a$ F
1869317 SYSTEMSI           ENG_PBA       SystemSI PBA does not align correlation waveforms correctly on Linux platform
( o* k4 i  F; O9 ~* u4 ]( K! |
/ Q7 F7 i' e% Q" `6 ]8 N0 r  q  p2 A. o8 P% S8 f1 x" r
Fixed CCRs: SPB 17.2 HF037% `  x' `2 b% x$ F
03-30-2018
) P" @4 c7 D6 \/ a; O! Y========================================================================================================================================================
9 p/ b6 \/ e- C  g) U  cCCRID   Product            ProductLevel2 Title
% ~" `- m0 |) a) I========================================================================================================================================================
/ C* G4 H( f. x9 m& [/ b% K1886573 ALLEGRO_EDITOR     IN_DESIGN_ANA Fail to launch Sigrity executable from release 17.2-2016
3 Z: K$ h% f1 E8 g' J' C1891113 ALLEGRO_EDITOR     NC            Clubbing total backdrill layerwise data1 C  ?) r& a: z1 B
1886085 ALLEGRO_EDITOR     SHAPE         Line to Thru Via DRC is not displayed automatically" p# _5 m/ m  K! N1 F+ X3 p
1850888 ALLEGRO_PROD_TOOLB CORE          Design Compare crashes immediately after execution
6 O7 ]( ~; p, E5 ]# z1639079 ALTM_TRANSLATOR    CAPTURE       Title block issues with third-party design3 A' U' G! B8 W3 T8 v' T% @0 h
1722577 ALTM_TRANSLATOR    CAPTURE       Third-party translator does not work in Capture in release 17.2-2016 if CDSROOT is not defined5 s  J6 e7 Y( {1 ^4 ]2 j# q8 p
1744697 ALTM_TRANSLATOR    CAPTURE       Third-party translator crashes# i6 j  F2 q' z* C+ j; o8 D
1820160 ALTM_TRANSLATOR    CAPTURE       Title block does not show ghost image when selecting it for placement6 r+ f9 l8 f8 L" E/ p! O% f
1628560 ALTM_TRANSLATOR    PCB_EDITOR    Third-party translation to PCB Editor not working properly. d/ l8 v3 V9 T" r. o& s$ C  G
1836750 ALTM_TRANSLATOR    PCB_EDITOR    Third-party translator fails to translate a complete design
- l0 F- k' \) T2 M: i1844423 ALTM_TRANSLATOR    PCB_EDITOR    Third-party translation takes a long time in release 17.2-20160 [# R0 W& Y, f% X* f) r
1849338 ALTM_TRANSLATOR    PCB_EDITOR    Third-party translated board not correct2 k5 a8 Q) V$ U9 b) A4 S% d- A
1894607 CONCEPT_HDL        CORE          Closing CM during 'Save Hierarchy' crashes DE-HDL1 y! W5 i  H1 ^0 i
1703351 CONSTRAINT_MGR     CONCEPT_HDL   SigXplorer shows invalid models instead of default models in extracted topology$ x7 F+ i0 p* v
1868687 CONSTRAINT_MGR     CONCEPT_HDL   DML-independent flow: some pin-pairs missing for Differential Pair XNets when migrating 16.6 design to 17.2
" P, N+ f$ q% A5 G4 X8 n' z1868747 CONSTRAINT_MGR     CONCEPT_HDL   Additional pin-pairs created on migrating design to release 17.2-2016 DML-Independent flow1 R. ?# \+ u* n& P
1887794 CONSTRAINT_MGR     OTHER         Ability to disable cross-section changes in F2B flow) Z. {1 Q0 C6 d4 G
1859193 MODEL_EDITOR       TRANSLATION   DML provided by Model Integrity has a parsing error: curve must start at time zero) H9 V+ K  l1 Z" ~& L% F1 ^
$ A$ E- P: r" u, ^; s2 P( {

+ C6 C$ H' b. S8 o, j: l6 z. }- vFixed CCRs: SPB 17.2 HF0367 N$ o. z; Q& X$ Z& l! m- C
03-16-2018! \1 x2 Q( O3 a, B) G& S8 D
========================================================================================================================================================
4 q- [! T4 P9 S4 N+ w& jCCRID   Product            ProductLevel2 Title7 F7 c2 i: N2 f3 B+ Y6 u
========================================================================================================================================================
% V3 C, z1 J' }3 t6 m4 X1880209 ADW                DBEDITOR      DBEditor quick search is resetting the check boxes in the Attributes tab
% d  x6 C: U6 w1 E$ d" x2 H1880376 ADW                DBEDITOR      Allegro EDM Database Editor wildcard search functionality broken after installing hotfix 034.
% c5 x1 j0 b9 i* h5 o1855444 ALLEGRO_EDITOR     DATABASE      PCB Editor crashes on creating MDD files after deleting subclasses3 m6 P5 T( {; O- V8 C& [; j3 ]
1863478 ALLEGRO_EDITOR     DATABASE      PCB Editor crashes on a specific machine when loading any .mdd file4 m; E5 a8 n+ b. Q; Q7 I9 L; w
1875544 ALLEGRO_EDITOR     SCHEM_FTB     Constraints are getting removed
4 Q! C7 L& u/ P- l& d1 w6 }2 D6 R1 y1719683 ALLEGRO_EDITOR     UI_GENERAL    Incorrect display when using infinite cursor.
: |& X, j. ?" p; ^1765989 ALLEGRO_EDITOR     UI_GENERAL    Selection window does not work correctly with infinite cursor option checked
9 E# G  y4 }. h* {8 W+ I1885667 ALLEGRO_EDITOR     UI_GENERAL    Infinite cursor is not working correctly" y# w3 B3 h& |2 k
1873954 ASDA               IMPORT_DEHDL_ SDA: Inconsistent pin number positions on part in an imported DE-HDL project
- M- R6 O! S2 e1 Y$ j1873883 ASDA               NEW_PROJECT   SDA: New project from DE-HDL creates blank Page 17 n% c0 F5 _# I' I9 g: y
1852036 ASDA               VARIANT_MANAG Design with variant cannot generate a variant BOM
" h# d9 ~5 P- K1875549 CONCEPT_HDL        CORE          Incorrect PART_NUMBER/VALUE properties on schematic
' I0 [) n& ~# p+ \/ K" ?) _5 p1881848 CONCEPT_HDL        OTHER         License issue: Cannot open Allegro Design Authoring and unable to choose options and features
- I# w7 ~7 t0 j1872189 CONSTRAINT_MGR     CONCEPT_HDL   Pin-pairs are created for incorrect members of differential pair after ECSet is applied0 l5 D6 A5 J/ D8 W/ ^; |
1880235 CONSTRAINT_MGR     UI_FORMS      Ability to lock auto-generated Constraint Set in UI
; k" m5 O  L) K( i1868711 CONSTRAINT_MGR     XNET_DIFFPAIR Nets are dropped from XNets on the BRD file in the front-to-back flow
8 U1 \  b" F; {1 U1879296 ECW                PROJECT_MANAG Mode to remove Uprev Lock from locked webs in admin keys
5 q/ `- k( b$ b1881632 PSPICE             SLPS          PSpice creates 'psp_input.log' during co-simulation flow
% d; r7 j0 P) ?" h, V& e# g0 U1879302 SCM                OTHER         SCM crashes when global nets are changed in the Block Packaging Options dialog box( z% `9 c# I/ s/ H& A: \
1879580 TDA                SHAREPOINT    GetData error when opening a project in Design Data Management; c9 z" h# B3 |+ l5 ^
( v& e2 y: W# L0 J- e3 b

3 N0 z% c8 t8 t9 UFixed CCRs: SPB 17.2 HF035
( `- X; d6 F0 w9 d; d9 @03-02-2018
8 j0 a0 h, F- o# a========================================================================================================================================================
& X) m0 a1 L( a8 w1 ], x# t: JCCRID   Product            ProductLevel2 Title2 c0 [7 i" M' k
========================================================================================================================================================
  p4 i8 _; Q& |% G1 ]4 q1873547 ADW                ADW_UPREV     adw_uprev resulted in incomplete footprint XML8 e4 U0 z' _5 f- W8 K! j  D& P
1643895 ADW                DBEDITOR      Create Footprint model name is not working properly if footprint exists in local flatlib
& ^9 T) o- U# y+ }" I1846400 ADW                DBEDITOR      'Copy As' and 'Rename' STEP model options do not work3 J' W. O: Z5 s
1868299 ADW                FLOW_MGR      Copy Project fails and makes Flow Manager unresponsive; x1 B6 z( C) s! a2 y, n' |
1872796 ADW                PART_BROWSER  Part/Model Details Attributes are all empty when connected to the EDM DB( I& p7 H7 V4 w% M! H4 }3 R
1877199 ALLEGRO_EDITOR     DATABASE      Purging backdrill adds bottom filmmask to vias when it is not defined in the padstack' n! }# k) ?6 X) o* R
1877219 ALLEGRO_EDITOR     DRC_CONSTR    PCB Editor crashes on updating DRC
0 m5 W  g6 h: Z4 x& Y* r1875528 ALLEGRO_EDITOR     GRAPHICS      Subclasses disappear in partition
/ |; [: w! N$ J, ~' L! q* ?1868364 ALLEGRO_EDITOR     OTHER         Translator for Layout to PCB Editor fails in release 17.2-2016 but works in 16.6: l, B+ ~6 M8 [# `' o( x/ Z
1822989 ALLEGRO_EDITOR     UI_GENERAL    PCB Editor very slow when using infinite cursor1 ]7 K( E) R$ a" ~5 `( H) V6 i
1855275 ALLEGRO_EDITOR     UI_GENERAL    PCB Editor becomes slow if OpenGL is disabled9 `( P  O2 p- X6 \% E, A$ H2 E
1868803 ALLEGRO_EDITOR     UI_GENERAL    Infinite cursor not working as expected1 [3 u3 L; [% d
1869523 ALLEGRO_EDITOR     UI_GENERAL    PCB Editor hangs inconsistently on axlOpenDesign
+ C; V% }% z9 J+ C; [: Y3 B1871409 ALLEGRO_EDITOR     UI_GENERAL    ESC key does not function with Enable_command_window_history set
5 a, L) Z* g9 t  P6 L1812306 ALLEGRO_PROD_TOOLB CORE          Incorrect DIFF result of PCB Design Compare
( c$ s1 O6 a( \3 R' i1872772 ASDA               MISCELLANEOUS SDA pulls a license for 'Allegro_performance'" b! V: q9 {6 c$ j' q. a
1877070 CAPTURE            OTHER         Capture redraws icons
1 ~& h5 e2 N! k# o+ f3 T/ P& O8 _1863624 CONCEPT_HDL        CONSTRAINT_MG XNet names are changed in the designs migrated to release 17.2-20168 E' `& Q, k& E. x
1866290 CONCEPT_HDL        CORE          variant editor/DE-DHL crashed when changing a component property
3 w& ^) _/ W/ z( P1858139 CONCEPT_HDL        OTHER         Slow graphic response in Windows10: Icons redraw
( Q* [1 V& @8 J) z# w) G, l1872703 CONCEPT_HDL        OTHER         Icon and toolbar in DE-HDL keeps on refreshing for every command
! K) h1 ~. e# a2 n1873949 CONCEPT_HDL        OTHER         DE-HDL user interface refreshes frequently/ v3 f: b; _0 O2 z; H5 x7 _
1871542 CONSTRAINT_MGR     INTERACTIV    Extracting object with 'Referenced ECSet' does not inherit T-points from the applied ECSet- P' L8 `+ U5 @
1868812 CONSTRAINT_MGR     UI_FORMS      Cannot Save Log File from CM ECSet Audit.5 v1 [0 d' Z! u; X% D
1878574 ECW                PROJECT_MANAG Duplicate entries are created in SharePoint users list while creating project on SSO setup/ Z1 m! n: C3 Z* E! V3 x! \9 F
1878619 ECW                PROJECT_MANAG Too many mails generated on doing create project
) a% }7 {/ q3 b1862772 ECW                TDO-SHAREPOIN Logical BOM file name not displayed in Changed Files of Pulse Activity Log.& Y$ s& C* @& n$ s5 b1 ?: l
1860641 INSTALLATION       DOWNLOAD_MGR  Download Manager remembers credential settings/ l3 h( ?, Q3 V3 ?
1867195 INSTALLATION       DOWNLOAD_MGR  Download manager crash
1 u& U( |3 F9 r* r2 y1 J4 y; P1872187 SIP_LAYOUT         DRC_CONSTRAIN Sliding a cline removes DRC markers but updating DRC shows more DRC markers
, h9 l: R$ [+ Q! Z0 |7 N8 b: D( o, p8 W% o- W: S4 p
0 {8 M; x) w; x* E
Fixed CCRs: SPB 17.2 HF0342 ]& u; k8 t& b  V% y8 [3 }0 g$ k
02-11-2018
# k( D3 h7 b) B) a( o+ x' b========================================================================================================================================================
0 V& ?( Y' @( N2 T; I5 aCCRID   Product            ProductLevel2 Title" J/ m+ F1 {8 B
========================================================================================================================================================
$ @- _8 E5 Q+ \5 h* B  u1863981 ADW                ADW_UPREV     adw_uprev is taking a long time after installing hotfix 031
% V1 p6 _! l7 V4 i1868186 ADW                DBEDITOR      Configured LDAP authentication giving error on launching DBeditor after ISR31 installation
; y: U& |( y( P7 {& c1861524 ADW                LIBDISTRIBUTI Library distribution is checking for obsolete classifications every time it is run hence taking more time
( T8 S/ F% r6 r: B0 Y1842998 ADW                LIB_FLOW      Footprint model check-in fails with verification checks failed error6 x9 k. m2 u# e' h9 g; A9 z! q
1863047 ALLEGRO_EDITOR     DATABASE      The layer added above the TOP layer in SiP Layout cannot be deleted from database.
- t& H. y' V, x) x1852799 ALLEGRO_EDITOR     DFM           Refresh symbols crashing inside constraint re-enablement code+ h" I- j5 Y# ^& S0 a  H9 @
1865732 ALLEGRO_EDITOR     DFM           The Thru via hole to Pad check in Annular Ring should check only the Finished hole size instead of backdrill diameter
1 V7 l1 g7 Z4 F9 ^% ]4 z3 ^1862977 ALLEGRO_EDITOR     DRC_CONSTR    Differential pair phase tolerance DRCs introduced in release 17.2-2016 DML-independent flow# U5 b. M! @4 f  d
1864460 ALLEGRO_EDITOR     EXTRACT       Running Extracta from outside using command window writes layer name for top/bottom layers incorrectly for SiP designs
0 ^6 o* N3 K* t# N, N! u( ^1859208 ALLEGRO_EDITOR     GRAPHICS      Pop-up menu remains on desktop when PCB Editor is minimized8 C0 C* R3 Q4 z
1866422 ALLEGRO_EDITOR     MANUFACT      Backdrill update taking a long time
: Z) Y4 U; v) w2 m  t* A- M& b4 s1867148 ALLEGRO_EDITOR     MANUFACT      Backdrill update taking longer time to process./ e$ Z- Z3 u8 l2 A
1872127 ALLEGRO_EDITOR     MANUFACT      Backdrill performance issues - Additional fixes required for S034
$ n  E. |% ]: b1 n+ |% o1866577 ALLEGRO_EDITOR     SHAPE         Board becomes unresponsive on Shape Update or Slide Trace
+ @+ _' Y6 L- B% _" R) d1 M7 {" x1867590 ALLEGRO_EDITOR     SHAPE         The Shape to Pad clearance on multi drill oblong padstacks is not working correctly
7 Q% s4 \1 v; M5 x* g& w$ D1871902 ALLEGRO_EDITOR     SHAPE         Void issue during rotation of symbol with multi-drill padstack from hotfix S0321 T' |/ k( D) Z
1866778 ALLEGRO_EDITOR     UI_GENERAL    Unsupported prototype 'Enable_command_window_history'  is not allowing text edits using arrow keys
' s8 e; ]9 A0 j# t: f1865757 ASDA               DESIGN_CORRUP SDA hangs when trying to save design or copy page or circuitry( w  {- M# O5 C  ^8 r5 `0 I
1865872 ASDA               DESIGN_CORRUP Corrupt design crashes on editing.
: X$ `5 |) C3 ^9 d, K1867039 ASDA               DESIGN_CORRUP Design corruption issues6 [, a) t- P  \2 d
1831263 CAPTURE            OTHER         Toolbar refresh is very slow on windows 10 after installing latest windows patch
/ y  a& D% j+ F6 h% b2 J, ~1843595 CAPTURE            OTHER         Icon refresh is very slow on Windows 10 Professional after installing Hotfix 0292 L% \8 W* g: s
1845003 CAPTURE            OTHER         Application slow to respond after running for a long time9 ^4 |# h7 X" z9 M  Z1 G
1847062 CAPTURE            OTHER         Starting OrCAD Capture redraws the toolbar icons many times./ f& T% c. u3 H* u- a
1850816 CAPTURE            OTHER         Capture redraws toolbar very slowly and repeatedly
8 |# u; o7 _5 X: I: x1851346 CAPTURE            OTHER         Capture CIS redraws toolbars repeatedly2 ^9 ~, }2 G! i1 y/ F
1851354 CAPTURE            OTHER         Capture slows down in Hotfix 30 as tools icons are repeatedly redrawn very slowly
6 ~2 U' N3 F* U, j- J/ Y! N! X& S3 Y1851883 CAPTURE            OTHER         Toolbar content refresh is very slow
0 s  J+ ~% ~$ Y. N+ M8 n1852819 CAPTURE            OTHER         Capture refreshes toolbar again and again
! O; I% \4 W' z1853395 CAPTURE            OTHER         Release 17.2-2016: Capture is refreshing toolbar icons many times at startup with latest hotfix
1 y. f9 y+ ]0 k/ t3 L9 o  b$ T1853972 CAPTURE            OTHER         Capture starts and redraws toolbar very slowly) i' }2 |3 v. S+ \
1854735 CAPTURE            OTHER         Capture toolbar reloads multiple times7 K3 D/ J; Y6 e5 w1 X: K) y; C
1855850 CAPTURE            OTHER         Toolbar content refresh is very slow) M- O/ ?1 B1 v1 ^1 J
1857523 CAPTURE            OTHER         Toolbar icons refresh multiple times and very slowly in release 17.2-2016# h! T' {! \6 C9 X  Z6 P0 e
1859219 CAPTURE            OTHER         Toolbar is refreshed multiple times while starting Capture CIS8 R9 y3 a9 X4 O) W
1859626 CAPTURE            OTHER         OrCAD Capture does not work with the latest Windows 10 update
3 q2 o( p3 Y+ [5 \6 m: F1863341 CAPTURE            OTHER         Toolbar icon refresh is very slow
/ c8 h0 ?% g4 d: P, m; y3 z9 S& I1865661 CAPTURE            OTHER         Release 17.2-2016, hotfix 032: Capture extremely slow on Windows 10
% v- I8 E( T+ D1867009 CAPTURE            OTHER         Slow graphics with Design Entry CIS on Windows 10.0 U, P0 k% {; B8 Q
1869160 CAPTURE            OTHER         OrCAD Capture poor performance (toolbar related)5 J3 o4 I( v- M6 E: C# g" ?$ K, l9 l
1869692 CAPTURE            OTHER         Redrawing of toolbars on Windows 10  V( _, b( L" c" G9 L6 U$ m# {! X
1870310 CAPTURE            OTHER         Allegro Design Entry CIS redraw issue
# Y" t$ C) t! H: J4 c0 k! s1870367 CAPTURE            OTHER         OrCAD Capture Slow Redraw5 e% ~: u4 R4 f* k0 T2 l# o
1871382 CAPTURE            OTHER         Schematic will not open and toolbars refreshed repeatedly
# M! m6 h, N9 R1872427 CAPTURE            OTHER         OrCAD Capture freeze on Windows 10* z$ W$ E* S( A: }1 U7 r* `
1862679 CONCEPT_HDL        COMP_BROWSER  Unable to input property value to search in Part Information Manager
; B  e" F( {7 a3 p1 q5 ?3 m+ K1865039 CONCEPT_HDL        CORE          'Save Hierarchy'  of a release 16.6 design opened in release 17.2-2016 results in unexpected part changes
2 r9 I& g  c: [( c5 U1866544 CONCEPT_HDL        CORE          XNET_PINS added to migrate Design as DML Independentflow does not get saved in the CSA files4 F/ a2 h# V& P  g* Z
1849363 SIG_INTEGRITY      SIMULATION    Differential impedance calculation shows ZERO when changing dielectric constant
& Q' ~- j: R5 r0 k7 h1854195 SIP_LAYOUT         UI_GENERAL    After setting 'enable_command_window_history' in QIR5/Hotfix 031,  Edit - Text no longer functions
' l* r7 \1 a& x4 S6 ?( H
$ O0 V& P! D5 c* O& I$ w2 P: G
; |4 {2 i; U0 o1 |2 ^Fixed CCRs: SPB 17.2 HF033
+ D3 J2 ~2 F) y9 f6 q0 m) n01-25-2018
, n, \" i" q& n4 t5 ^2 G( h9 F# A7 v: E========================================================================================================================================================
# l7 q5 x6 Z3 L( SCCRID   Product            ProductLevel2 Title8 {8 t2 L7 f+ J1 |+ u
========================================================================================================================================================
5 H, w# C. p$ K6 ^, B" x1828672 ADW                ADWSERVER     LDAP connection error while trying to log in to DBeditor
7 ~) K. z8 ~% S, r+ _1840699 ADW                DBEDITOR      Unable to release footprint model due to older version being linked to a DE-HDL Block Model7 s  K; {* Y$ d. N  _9 a) q
1852402 ALLEGRO_EDITOR     DATABASE      Cutouts are not converted correctly when opening release 16.6 board in release 17.2-2016
& p2 y# h' u) S& ]" T; r5 B4 Y1855223 ALLEGRO_EDITOR     DATABASE      Release 16.6. BoardOutline not fully converted to release 17.2-2016 Cutout Layer% Q1 N# o. o- `7 \: S* b# G
1855252 ALLEGRO_EDITOR     DATABASE      Unable to open a previously saved release 17.2-2016 database
( X, ?" c" j" g6 ]1 L# [8 j3 N1863025 ALLEGRO_EDITOR     DRC_CONSTR    Shape voiding to Via pad with backdrill keepout is oversizing the Dynamic shape void by the backdrill keepout/ V# r/ N/ f  F% `  @' y
1854087 ALLEGRO_EDITOR     EDIT_ETCH     Sliding arc crashes PCB Editor
7 w7 g) u6 k/ p0 S; {- T1840667 ALLEGRO_EDITOR     INTERACTIV    Choosing 'Change Text block to' from pop-up displays message 'E- (SPMHGE-150): Text font is not defined'
/ |. ?6 L) w( Z$ Z0 J" @# x1849133 ALLEGRO_EDITOR     INTERACTIV    On choosing 'Change Text block to' on text , 'Text font is not defined' message appears2 t! T& g( N' [7 H3 d( R' c' N
1854695 ALLEGRO_EDITOR     MANUFACT      PCB Editor crashes while performing nc_route
" |5 S1 M$ P8 i, _( m2 Q& l1854634 ALLEGRO_EDITOR     NC            NC Drill file is generated with half the number of Drill Holes on enabling 'Optimize drill head travel'
+ C" s! G: J2 Z& o! a1856773 ALLEGRO_EDITOR     NC            Issue with Optimize Drill head travel in hotfix 031: Missing drill holes
7 N# n9 C0 d  g/ t* m/ r1860876 ALLEGRO_EDITOR     NC            NC route critical difference between hotfix 031 and 022: No slots found warning
3 Y. G' U% Z0 l! k1758671 ALLEGRO_EDITOR     OTHER         Export parameters takes long time to export and some times the process hangs
4 J; r. {0 ~8 N( z3 r3 b2 K( ]( n3 j/ k1040989 ALLEGRO_EDITOR     SHAPE         PCB Editor crashes while editing board outline
$ a2 r+ W; @6 A) @! N1328385 ALLEGRO_EDITOR     SHAPE         Check for missing thermal reliefs when shapes overlap
( o& {- Y8 {6 d, ~; |9 i. C4 t1366376 ALLEGRO_EDITOR     SHAPE         Thermal created for Xhatch shape overlapping another shape, but not created when solid shapes overlap0 N; [! S( r) S4 ]- n
1716436 ALLEGRO_EDITOR     SHAPE         Acute angle trim should not violate DRC.; U& G7 ~' m: X! E+ c/ u! d1 G: W  \
1822377 ALLEGRO_EDITOR     SHAPE         Setting shape parameter Acute angle trim control to Full round produces unwanted shape to keepout DRCs# N$ F' F" y9 d: Z9 _0 y
1826436 ALLEGRO_EDITOR     SHAPE         Same net shape to hole spacing not voiding shape for cline of different net moved close to vias of same net shapes
4 a5 @- z5 l$ y9 c5 _1834510 ALLEGRO_EDITOR     SHAPE         Same Net Shape to Via Spacing does not always clear correctly5 M+ k- ]2 D3 j3 \4 U$ C4 c
1850716 ALLEGRO_EDITOR     SHAPE         'DiffPair combined void for vias added with Return Path option' does not work with fillet and pad suppression
; M* n( r( W+ m. y/ c1852814 ALLEGRO_EDITOR     SHAPE         Thermal reliefs are not created after placing modules./ f1 y4 ~5 ~6 s0 z' a
1853453 ALLEGRO_EDITOR     SHAPE         Route keepout clipping of cross-hatched shapes needs to be corrected6 m$ q4 R1 Z9 Y# b% C
1859391 ALLEGRO_EDITOR     SHAPE         Shapes are not using 'minimum aperture for gap width' for voiding after back drill update.  s5 \8 h, C  T/ ~9 V3 q
1859410 ALLEGRO_EDITOR     SHAPE         Shape to Teardrop is not using same net spacing rules! \  Q" r& ?9 q5 D6 o3 s
1825397 ALLEGRO_EDITOR     UI_FORMS      Option panel disappears in release 17.2-2016
! x; [& N2 G& X) w7 k; K1854070 ALLEGRO_EDITOR     UI_GENERAL    enable_command_window_history prevents many aliases and commands from working correctly/ l7 A* C: \6 |
1855180 ALLEGRO_EDITOR     UI_GENERAL    Comma and dot do not work in funckey if 'enable_command_window_history' is set( A. I: ~5 h, B% X( }, j! h8 Y
1860003 ALLEGRO_EDITOR     UI_GENERAL    Icons and features missing or behaving differently in release 17.2-2016, Hotfix 031
( Q2 D: V9 B" ^' I% {: D# t, t1861278 ALLEGRO_EDITOR     UI_GENERAL    Icons and menus missing in PCB Editor in release 17.2-2016, Hotfix 031" S2 n. |6 B) t0 ]) W2 @: n
1862292 ALLEGRO_EDITOR     UI_GENERAL    Layout Pins icon missing in toolbar in Symbol Editor since Hotfix 031) d4 b3 x3 a0 S* o3 k  D# W
1793284 ALLEGRO_PROD_TOOLB CORE          Limit View (V1R, V2R, COM) for OUTLINE layer.
( {& |! h" [0 z$ }$ o1712701 ALTM_TRANSLATOR    CAPTURE       Third-party translator shows error for missing operand
' a; ~! z( W$ i7 O6 [8 m1802182 ALTM_TRANSLATOR    CAPTURE       Imported schematic has connectivity loss/ v7 O" L# o# |3 t' C2 l
1802462 ALTM_TRANSLATOR    CAPTURE       Hierarchical ports placed incorrectly for imported third-party design
( q9 Z1 L' E' ~2 O- C9 h1823935 ALTM_TRANSLATOR    CAPTURE       Translating third-party schematics with hierarchical pages from Design Entry CIS
+ s2 C  h# f4 u1830570 ALTM_TRANSLATOR    CAPTURE       Third-party to Capture translation is translating only one page out of 32
0 n7 [! O1 r; f& p0 {9 o0 m: }1839627 ALTM_TRANSLATOR    CAPTURE       Third-party translator is not importing complete schematic
! ?" f0 t, {2 L0 I9 t1846965 ALTM_TRANSLATOR    CAPTURE       Cannot translate third-party schematic: H; k. I' S. }3 w
1816767 ALTM_TRANSLATOR    DE_HDL        Error when translating third-party schematic to DE-HDL5 [) I$ ?& v5 ?  x! }3 v
1845601 ALTM_TRANSLATOR    PCB_EDITOR    Cannot operate third-party PCB translation in release 17.2-2016 Allegro Venture PCB Designer license
  K' ?8 @- I/ h( Y1841060 APD                DIE_GENERATOR Cannot 'die text out' from SiP Layout or Allegro Package Designer7 r: y- a+ e! \  ~: M9 z1 g
1793232 APD                SHAPE         When fillet/taper not connected to a pin, voiding process incorrectly applies shape clearance values
' [+ C  D3 T# J9 |1846541 APD                SHAPE         shape degassing does not obey void to shape boundary7 p7 B8 H. P6 @1 \4 i
1863446 ASDA               CONSTRAINT_MA A space in the name of a spacing or physical constraint results in the incorrect constraint set name
6 P! B; r( e+ C; [3 P$ y1859678 ASDA               VARIANT_MANAG SDA - When hovering over all three buttons, under Preferred Parts in the Variant info it says (Do not install)+ H  D  y, `. |/ W) L' T- c' R
1815839 CONCEPT_HDL        CORE          Allegro Design Entry HDL crashes when entering Location data manually3 ]( l1 J) V0 h1 K; B+ x! p. h
1841857 CONCEPT_HDL        CORE          Unable to modify Components in non-windows mode* k. O. a* d- {; M
1852096 CONCEPT_HDL        CORE          Creating a block using top-down approach does not generate the CSB file. `- h1 d  ]* H% u$ A. o
1857390 CONCEPT_HDL        CORE          DE-HDL crashes on moving symbol
7 d( \0 R. Q6 j# `; n; h1789070 CONCEPT_HDL        OTHER         Having folder 'allegro' in cpm root directory gives error while launching layout editor from Project Manager
! d9 h, p5 ?/ `! p6 d  Z6 l2 D) n1862484 CONSTRAINT_MGR     CONCEPT_HDL   Extracting an ECSet in SigXP is missing a t-point! J6 `7 O7 p6 R' ^' ]
1863045 CONSTRAINT_MGR     CONCEPT_HDL   Pin pairs deleted for a few differential pairs after upreving the design to release 17.2-2016
3 r/ P9 }2 q# e2 ?7 }1863054 CONSTRAINT_MGR     CONCEPT_HDL   Differential Pairs are treated as invalid objects on upreved design
- \% `) l4 F* d: b% Y6 R1863094 CONSTRAINT_MGR     CONCEPT_HDL   Pin-Pairs are shown duplicated in the topology for the extracted object (Diff Pair)7 a3 U: L; q  X1 l7 Z% o2 f
1831998 CONSTRAINT_MGR     OTHER         'Tools - Options' settings not saved on closing Constraint Manager; f9 v- ?# {$ {
1855324 CONSTRAINT_MGR     OTHER         Enable the option 'Expand Hierarchy' in 'Find and Replace' dialog, by default
, h; J: m; L6 v8 s5 m1860847 CONSTRAINT_MGR     OTHER         'Include Routed interconnect' option once enabled, should remain enabled for that board file2 k5 [( d* ~2 o0 P- g0 ]/ I
1843359 EAGLE_TRANSLATOR   PCB_EDITOR    While importing third-party PCB, many footprints do not convert, even though the log file says footprint created
* d' p$ S3 }. J* R, V: t1839978 SCM                REPORTS       dsreportgen unable to output reference designator from a lower-level hierarchical block if it has a single component% N2 D' k! J% n* F6 T8 x
1850013 SIP_LAYOUT         OTHER         Environment variable 'icp_disable_cte_auto_update' needs grammatical change6 d/ p3 V( q  z" G7 W  D3 ~3 R
1833742 SIP_LAYOUT         PADSTACK_EDIT When creating Die to Die Via using Generate Padstacks, resultant pad stack has wrong Layers
9 P8 d6 U" F- _9 w9 }1619098 SIP_LAYOUT         SHAPE         Acute angle of shape in design7 t. w) B5 J7 T, q
1728628 SIP_LAYOUT         SHAPE         Auto-void in dynamic shape does not disappear if object is removed
, g6 d. R! ~) G" {8 |  U: M: B1854592 SIP_LAYOUT         VIA_STRUCTURE Create via structure returns an error) H: j' T3 A, B! c$ y1 B7 {+ C
& l6 t/ X9 C: B2 l7 i) }  S  L
; x& z/ y0 b: k) h. g, E  A7 M
Fixed CCRs: SPB 17.2 HF032
. s% W: h4 S) f! G01-13-20183 H4 a( M: ?0 P$ I/ \- ?4 p
========================================================================================================================================================; S& n' w7 p% l+ B! H
CCRID   Product            ProductLevel2 Title$ r) ?$ _( ^# ]8 w: u( q7 A
========================================================================================================================================================/ a! p3 L+ g1 o0 Q+ p; m3 d
1846603 ADW                FLOW_MGR      Copy project GUI not displaying correct design name after changing the project folder name
4 g/ R+ C$ g( b1 I) d% W, o; M/ m1831152 ALLEGRO_EDITOR     3D_CANVAS     New 3D viewer canvas is blank
: _- A5 N- G& S- I: r0 C, ~1 J1805870 ALLEGRO_EDITOR     COLOR         Color file with dot (.) in the filename is not recognized for setting color from the Visibility tab
2 K6 e  L5 `2 v* N/ r$ z1843126 ALLEGRO_EDITOR     DATABASE      DBDoctor UI is taking very long7 G0 h6 I5 }& I! L+ G9 g5 k8 x
1857588 ALLEGRO_EDITOR     DFM           Design for Fabrication - Aspect Ratio is not taking correct drill hole size5 P- f& g4 O) o8 K8 e
1844313 ALLEGRO_EDITOR     INTERFACES    STEP output viewed in third-party tool has parts sunken into the secondary side, `6 e# z7 {% q/ j% |/ w0 Q: {+ T
1801301 ALLEGRO_EDITOR     MANUFACT      Export IPC 2581 fails if VOLTAGE property is attached to the nets on each side of a RF component6 r  Y4 [7 w3 Z  X" ]0 m
1850078 ALLEGRO_EDITOR     MANUFACT      Choosing 'Manufacture - Artwork' crashes tool
7 x2 o; h2 M% I" \1844049 ALLEGRO_EDITOR     MODULES       Module deletion not removing related component information.# V* E  c- b; s1 }+ I
1849665 ALLEGRO_EDITOR     MULTI_USER    Shape rejected by muserver7 V: {2 e3 t+ m3 |# q! r
1782831 ALLEGRO_EDITOR     RAVEL_CHECKS  RAVEL file does not load when it is located on a network with a UNC path specified% |% ^3 g9 t' q* ^2 p4 s# O* L
1830442 ALLEGRO_EDITOR     SCHEM_FTB     Fail to import technology file with message for failure to read the configuration file
' e: Z! O3 J! F0 [* K0 j& X1837391 ALLEGRO_EDITOR     SCHEM_FTB     Capture Property cannot rewrite or update constraints in PCB Editor
2 L! N: Y/ J& Z6 z3 t# Z4 R& v1840643 ALLEGRO_EDITOR     SCHEM_FTB     Export physical does not work after modifying PCB cross section
$ M( u6 p2 ]! i4 ^! I1718165 ALLEGRO_EDITOR     SHAPE         Drill hole cannot be voided by shape
' v4 |- U! P. {* ^1 E1753245 ALLEGRO_EDITOR     SHAPE         Update Shape retracts more than the shape to shape spacing
5 b7 g1 D! R* N1 E& I& S: k1827366 ALLEGRO_EDITOR     SHAPE         out of date shape is not flagged as out of date2 z8 z# }4 C7 [: n9 ?7 F
1828208 ALLEGRO_EDITOR     SHAPE         Shape remains out of date, but status shows otherwise( a  Z4 ]( }% d
1832098 ALLEGRO_EDITOR     SHAPE         Skip via shorts to plane at few places even after the necessary keep-outs are assigned to the via pad-stack.
! B2 c) W& n2 N5 u- e1834281 ALLEGRO_EDITOR     SHAPE         DBDoctor creates a large number of DRCs
+ X! I9 ~9 b. f0 e/ b" n, C1842121 ALLEGRO_EDITOR     SHAPE         Unable to clear the Drill Hole to Shape Spacing DRC as Pin is not able void to the shape correctly.; i! C4 Z  |- j* n" |" w
1846010 ALLEGRO_EDITOR     SHAPE         Changing MCAD hole to copper spacing in Analysis Modes - Design does not make shapes out-of-date" }2 O4 K3 ?. {
1839119 ALLEGRO_EDITOR     UI_GENERAL    On some machines, PCB Editor hangs when launched with a script that uses SKILL to open a design
+ ^2 ?) Y+ `3 Y; f2 y( I1828794 APD                SHAPE         Setting Shape Fill Xhatch Cells option to HIGH, crashes the application/ `4 J" k% c( ^# k3 S5 e
1840748 CAPTURE            PROJECT_MANAG Capture crashes on opening or creating designs
8 o+ z. a" x( l; g' l1785298 CONCEPT_HDL        CORE          Incorrect object access during variant load
$ p- u2 G1 f$ V2 i& h. d3 d% O1832119 CONCEPT_HDL        CORE          Save Hierarchy shows ERROR(SPCOCN-2010) messages but design packages without error
  T, G) Z( P4 |0 C/ N1833036 CONCEPT_HDL        CORE          nconcepthdl crashes with a core dump when running an external script, Q; g1 f5 @7 t, u
1841545 CONCEPT_HDL        CORE          NO_XNET_CONNECTION properties added to two-pin filters after upreving to release 17.2-2016' N* Y* |9 F, e+ |1 Z+ [
1842289 CONCEPT_HDL        CORE          Opening a schematic in release 17.2-2016 causes the .dcf file to be overwritten2 Q' p/ Z7 j" C1 p2 \
1841543 CONCEPT_HDL        OTHER         DE-HDL crashes when changing a net name/page name/bit bus after installing release 17.2-2016, Hotfix 029+ @$ H8 _. R2 L+ n' L2 _
1843791 CONCEPT_HDL        OTHER         Table of contents listing does not update for some hierarchy blocks at the top level. l) L# R: C; [
1850709 CONCEPT_HDL        OTHER         DE-HDL crashes on editing text on canvas in release 17.2-2016, Hotfix 030
; S( G' o" p8 @$ X1853377 CONCEPT_HDL        OTHER         DE-HDL crashes on trying to edit bus tap value on Windows 10.+ w0 C- c1 W& X" `7 o" R5 ^5 T& @: Q
1857213 CONCEPT_HDL        OTHER         DE-HDL crashes when changing Power Property
9 q6 m5 }7 j# ]: q+ C1857214 CONCEPT_HDL        OTHER         In release 17.2-2016, DE-HDL crashes on using 'Change' for a $LOCATION text value on Windows 10
" m* G6 @1 x+ K8 [' n1 I8 m. |8 K1821982 CONCEPT_HDL        PDF           Pin number shown in PDF published from DE-HDL
* r5 s9 Y& J( M+ f( B4 K1848615 CONCEPT_HDL        PDF           PDF Publisher shows incorrect pin text values for parts
1 E4 Z* ]# v9 _4 Y/ z8 }1845996 CONSTRAINT_MGR     CONCEPT_HDL   Confusing error message regarding 'Auto XNets Off Mode' vs 'DML Enabled'8 U1 b# `* }8 w/ _1 A. W
1854190 CONSTRAINT_MGR     CONCEPT_HDL   'Audit - Electrical CSets' hangs Constraint Manager after the design is upreved to release 17.2-2016
- j8 A, v; S. Q' c; `1854868 CONSTRAINT_MGR     CONCEPT_HDL   Match Group getting deleted after upreving the design to 17.2 and removing the signal_models
: W7 H- H2 S7 {) r! _1854872 CONSTRAINT_MGR     CONCEPT_HDL   Additional Pin-Pairs getting created on the DiffPair after upreving to 17.2
7 `0 ]1 c6 b2 b$ Y1822624 CONSTRAINT_MGR     ECS_APPLY     Cannot copy PCB net schedule from a net to other nets
4 U5 x# K6 y7 f2 n) S5 l1854883 CONSTRAINT_MGR     ECS_APPLY     Match group showing 0 length for pin pairs in design upreved from release 16.6 to 17.2-2016
0 C  x; H, n3 c5 Z! W5 X# Z1855893 CONSTRAINT_MGR     OTHER         SigXplorer extraction crashes PCB Editor
; I, Y* v4 O; n6 {' ]( N1855917 CONSTRAINT_MGR     OTHER         SigXplorer extraction does not extract constraints unless the worksheet is opened once in CM
$ L2 k( w/ h6 a& |2 i1855350 CONSTRAINT_MGR     UI_FORMS      Constraint Manager significantly slower in release 17.2-2016, Hotfix 031! Y# f7 }& Y- t
1855860 EAGLE_TRANSLATOR   PCB_EDITOR    Cannot invoke a CAD translator in PCB Editor/ |$ e+ K9 `2 V, k0 R; A. {
1857745 EAGLE_TRANSLATOR   PCB_EDITOR    A CAD translator does not invoke in PCB Editor
7 z# e* ?8 I& \& j1859005 EAGLE_TRANSLATOR   PCB_EDITOR    Eagle translator is not invoking at all
) P. q7 X& D, S7 z/ Z" n' `. Y5 K1843091 F2B                DESIGNVARI    Variant Editor allows mismatched JEDEC_TYPEs in release 17.2-2016, S) H6 F5 }- L$ d7 j# j9 c( O
1719059 FSP                DE-HDL_SCHEMA Termination resistors on buses not being drawn efficiently
, _- ~- |/ u4 t8 }- S2 ~1823419 FSP                GUI           Net Name Template not visible in Change Net Name in Windows 10
- _& w& Z0 _, I/ N% X' L% A1480035 ORBITIO            ALLEGRO_SIP_I Die symbols are mirrored when imported back to SiP Layout4 v- w4 M& K! U: p  Z2 ]- W: Z
1853331 PCB_LIBRARIAN      SETUP         CPM file not updated from PCB Librarian setup2 L; {9 ^7 u+ _$ L, @1 f
1841308 PCB_LIBRARIAN      SYMBOL_EDITOR Symbol not updated in Library View
# Y# z/ g( C; [3 X" a1831269 SCM                OTHER         Blank properties of associated components are being filled with NULL. e% x; b# t. Z( `) @6 p
1719057 SCM                SCHGEN        Pins off grid for voltage nets
4 ]/ ]6 Q( o, t' ]% m0 R; q& m1719060 SCM                SCHGEN        Pull-ups and pull-downs showing upside down in view1 q* m/ Z  N) O1 D5 j
1732687 SCM                SCHGEN        Schematic generation deletes IO ports; says it's placing them on last page, but never places them! p! ^: f! s6 e2 g$ o1 K" I2 I  ]' P
1855932 SIG_EXPLORER       OTHER         For non-DML designs, SigXplorer defaulting to mils when PCB Editor design units and CM constraints are in mm+ j8 T) u' Q* C$ c4 M  g
1824035 SIP_LAYOUT         WLP           SiP Layout DRC GUI not reading Tcl blocks in PVS DRC rule deck
6 K- K3 i* A! A0 D  p' Q6 M4 l; K/ ?, E; i$ n7 M) C

1 @* ^5 S* Y: l  ~( H  D0 E9 ]Fixed CCRs: SPB 17.2 HF031
5 Y  D9 T( B2 V3 B: P12-8-2017$ ~5 E; n( ^7 W- a8 _4 w* m
========================================================================================================================================================
$ Y/ ^1 y3 P/ C% Y' _CCRID   Product            ProductLevel2 Title
- n* c+ m4 Q- v# E3 j========================================================================================================================================================
' B2 l. e4 H  ]8 y/ i; `1 N1746108 ADW                DBADMIN       Adding and then saving a custom rule set in rule manager results in corrupt rules.xml
+ n6 P3 d/ W; t1609983 ADW                DBEDITOR      dbeditor should automatically change mechanical kit names to uppercase
9 k4 ?8 u. W1 h' V1 u1807139 ADW                DBEDITOR      Cannot add new properties, though the new properties were shown in dbeditor9 A1 J8 Z" m' B& s, @* o6 @
1807410 ADW                LIB_FLOW      Checked-in parts not available in database$ I. F2 t4 }8 s% [4 I* Y1 X, G+ t
1797408 ADW                TDA           TDO crashes without displaying exception during check-in
: w, i) H; H( x/ }( A1804500 ALLEGRO_EDITOR     3D_CANVAS     Interactive 3D canvas fails to show all placebounds of a .dra
9 e9 Q3 V( _% {6 I3 M6 }+ [. \1810758 ALLEGRO_EDITOR     3D_CANVAS     3D Viewer represents symbol incorrectly in hotfix 025 but as expected in hotfix 024/ U: C: B, W: u3 {$ J
1795567 ALLEGRO_EDITOR     EDIT_ETCH     Route menu has same hot key for 'Connect' and 'Convert Fanout') v' w3 D( A8 l7 m- t
1796525 ALLEGRO_EDITOR     EDIT_ETCH     AiPT is not pushing dynamic shape to add bumps to resolve dynamic phase DRC
- R: J& w# s9 g' G# O/ t1818170 ALLEGRO_EDITOR     EDIT_ETCH     Fanout with Outward Via direction is shorting few pins
' _7 E9 F5 }, \, G/ T+ |1 t  ?1712658 ALLEGRO_EDITOR     INTERACTIV    Add connect: Pin remains highlighted even after choosing 'Done'
% ~+ d- q# }% t1727193 ALLEGRO_EDITOR     INTERACTIV    Logic - Part List truncates device names to 64 characters though database allows longer names
% j7 \0 f) Y$ g1775484 ALLEGRO_EDITOR     INTERACTIV    Choosing Next with persistent snap in Show Measure disables persistent snap6 N' _7 K! U. z2 e( i; b: T+ m
1711860 ALLEGRO_EDITOR     MULTI_USER    Multi-user lock cannot be cancelled5 x+ [0 j& d7 z0 E, A
1812448 ALLEGRO_EDITOR     NC            Crash when canceling NC Parameters dialog
* h" r4 ]% q. h8 R2 l$ f& `1792987 ALLEGRO_EDITOR     PAD_EDITOR    Pad Designer does not recognize flash names longer than 31 characters
* ]; B0 ~/ {5 z! G2 `, U1810958 ALLEGRO_EDITOR     PAD_EDITOR    Padstacks with offset holes
* g6 e* D, Q; b  X2 R787024  ALLEGRO_EDITOR     SHAPE         Improve dynamic shape voiding in regions
& ^' c# H) y  X' x% ?( ?, \0 Q/ Z793232  ALLEGRO_EDITOR     SHAPE         Line to Shape spacing rule outside region affects shape void in region
5 t! j- v) t( N) A797245  ALLEGRO_EDITOR     SHAPE         Line to Shape Spacing with Region not followed8 f7 B4 d. K. q4 O  {
865822  ALLEGRO_EDITOR     SHAPE         The autovoid functionality should use the true line-to-shape spacing value. N! o  l- H$ l" A: @3 F) G& n
912051  ALLEGRO_EDITOR     SHAPE         Improve dynamic shape voiding in regions
. @% Y3 @- x! Y5 b  O965714  ALLEGRO_EDITOR     SHAPE         Region constraints are not working correctly on dynamic shapes
- a& {. ]* A! I+ N6 [8 d968342  ALLEGRO_EDITOR     SHAPE         Shape Voiding when crossing constraint region is taking conservative value and not the actual spacing value' C3 n0 Q5 I* m) K4 L0 r
974734  ALLEGRO_EDITOR     SHAPE         Shape Voiding when crossing constraint region takes conservative value and not actual spacing value
" V0 x) d1 X: ]/ V- ]1073908 ALLEGRO_EDITOR     SHAPE         Allow line to shape spacing in Region
6 ^7 m5 X0 U, l5 f1154787 ALLEGRO_EDITOR     SHAPE         Region constraints not applied correctly to dynamic shapes
, z" B: E0 j4 ]; w5 v1171283 ALLEGRO_EDITOR     SHAPE         Shape Voiding when crossing constraint region takes conservative value and not actual spacing value8 b  v5 I$ D8 ^; X
1181767 ALLEGRO_EDITOR     SHAPE         Allow override on line to shape spacing in Constraint Region1 }1 A: W" l  I: D. q
1183792 ALLEGRO_EDITOR     SHAPE         Allow override on line to shape spacing in Constraint Region0 Y# p% D/ n0 ]8 r% o5 `- X
1186210 ALLEGRO_EDITOR     SHAPE         Line to shape spacing constraint does not follow the Constraint Region value" \& H/ O6 i0 |3 f
1192312 ALLEGRO_EDITOR     SHAPE         Region constraints are not working correctly.
5 ^5 I4 B& ]0 c! ?" t( K$ q+ n1 W# W2 A1387021 ALLEGRO_EDITOR     SHAPE         Improve dynamic shape voiding in Regions
4 A5 K2 {- I+ F$ N1447891 ALLEGRO_EDITOR     SHAPE         Resolved constraint and actual air gap differ4 B" @+ C; E- K! S$ V  C& J9 e5 ~, E
1465383 ALLEGRO_EDITOR     SHAPE         Line to shape spacing constraint does not follow the Constraint Region4 j2 {+ K3 p" w- y
1583144 ALLEGRO_EDITOR     SHAPE         Line to shape spacing inside the constraint region does not follow region rules: ?/ n3 ]5 t5 z' {/ d
1591320 ALLEGRO_EDITOR     SHAPE         Resolve shape to pin constraint in constraint region0 C) r! _) D! p  D6 Z2 G0 T
1627305 ALLEGRO_EDITOR     SHAPE         Shape Voiding when crossing constraint region takes conservative value and not actual spacing value5 R1 Z. K: l) t4 X& E9 q( N0 ^
1694552 ALLEGRO_EDITOR     SHAPE         Constraint region not working correctly! m% ^) I& M/ l4 s; ~+ c/ r
1764474 ALLEGRO_EDITOR     SHAPE         Line to Shape Spacing for Region should be used inside region instead of conservative value, h7 J  x( `. Z- I5 U$ H7 w
1775119 ALLEGRO_EDITOR     SHAPE         Shape voiding is not following constraint rules for dynamic shapes in a constraint region! d' _/ b' j' k: K/ m$ e
1784916 ALLEGRO_EDITOR     SHAPE         Shapes are not voiding to other shapes against DRC settings, creating random DRCs.. C" y- R* G, |* A: x" K3 T( A) x
1793179 ALLEGRO_EDITOR     SHAPE         'Same net shape to hole spacing' is only detecting the DRC and not voiding the shape
4 x' A- X' k! a( Q9 B1803365 ALLEGRO_EDITOR     SHAPE         Region shape to shape constraints take precedence when shapes have multiple constraints
( n2 F, D( D) g2 J( _1800530 ALLEGRO_EDITOR     UI_FORMS      3D Anchor menu missing when using new style OrCAD PCB Editor menu7 V0 h! X1 `- Q! V! N
1813604 ALLEGRO_EDITOR     UI_FORMS      3D Anchor View is not available on OrCAD PCB Editor menu.
0 C& B* v3 x% J- I5 j1784710 ALLEGRO_EDITOR     UI_GENERAL    During Place Replicate and saving file with same name, the warning pop-up window does not show on top3 D2 q0 |0 a8 _* @+ h. F- f
1784728 ALLEGRO_EDITOR     UI_GENERAL    During Place Replicate and saving file with same name, the warning pop-up window does not show on top
# L; S/ v& i1 v% Q% t% k1721853 ASDA               CANVAS_EDIT   Movement of components results in shorts and inconsistent routing
/ M8 d& @9 o) D6 C1 }1802120 ASDA               CONTEXT_MENUS Ports are selected though filter is set to Components  |1 ~5 h; i9 n; x* {- S  Q
1803832 ASDA               MISCELLANEOUS Browse and select new libraries without editing cds.lib
. ~; k! _) h9 l% R1804643 ASDA               TABLE         Exception when pasting table data from third-party tool in SDA: i! V' s+ ]7 Z
1794004 CAPTURE            LIBRARY       Diode pin numbers different in Capture in release 16.6 and 17.2-2016
2 r& q0 v6 x. N- I1735506 CAPTURE            OTHER         File menu is missing in Capture1 [4 a2 J) ~1 \0 l+ n
1766663 CAPTURE            SCHEMATICS    Capture crashes during part placement
. ]7 d9 @, L1 Z) d: W. T0 @1762181 CAPTURE            SCHEMATIC_EDI Crash on 'Push Occ. Prop into Instance'
( S4 r2 E  i) B2 M' I# f1786762 CAPTURE            SCHEMATIC_EDI 'Remove Occurrence Properties' and 'Push Occ. Prop into Instance' corrupt database
+ e% F4 @. @2 f" F! i1759424 CIS                PART_MANAGER  Unable to save the link database part from part manager; O  k( p- O8 [9 F0 t& P
1802670 CONCEPT_HDL        CORE          Variant commands take 6 to 10 hours to run on a block, d0 J) f: A* C1 u7 y
1816798 CONSTRAINT_MGR     CONCEPT_HDL   CM API ACNS_DESIGN returns the design name in mixed case
( g, b7 Y! O/ ]2 r" W2 I! k$ D. w1812656 CONSTRAINT_MGR     DATABASE      Constraint Value specified at the DEFAULT PCSet/SCSet is not shown in bold blue) k7 e: ^3 p8 I
1635766 CONSTRAINT_MGR     UI_FORMS      Worksheet views are not changed as per input4 Z" G4 _/ W5 h  g# b" L; l
1700505 ECW                PART_LIST_MAN Shopping Cart Quantity is not read or not displayed in Pulse1 D5 ]7 @: V1 C7 ?8 q
1797371 ECW                PROJECT_MANAG Clicking on another project sometimes takes you to the default project instead of the project you click on
7 n5 n; s. f) H0 M% S" m1843526 INSTALLATION       TRIAL         Trial installer should not check disk space in update licensing mode) `# ~) n! a) k" u- c
1762148 PCB_LIBRARIAN      SETUP         Part Developer: Text not readable in Setup form" O2 v" h, ]$ w4 J6 X6 q- g
1770760 PCB_LIBRARIAN      SYMBOL_EDITOR Symbol Editor does not remember the last size of the window
8 q3 q2 n- J5 R) b1 k1773604 PCB_LIBRARIAN      SYMBOL_EDITOR Option to switch between the new and legacy Symbol Editors: Q3 m  t% W/ b4 F# ^6 r
1800354 PCB_LIBRARIAN      SYMBOL_EDITOR Resistor has too many lines and looks wrong in new symbol editor7 Y5 j$ \; R1 I! S1 B, b( l
1813346 PCB_LIBRARIAN      SYMBOL_EDITOR Resistor looks different with multiple diagonal lines in new Symbol Editor but looks normal in DE-HDL
2 L7 }# b/ L9 s6 N" K% n1815279 PCB_LIBRARIAN      SYMBOL_EDITOR Unable to change Grid Settings from Lines to Dots) C+ [  ?  @/ ?- K
1738603 PSPICE             DIG_SIMULATOR Release 17.2-2016 PSpice digital model: Delay defined by PINDLY is not taken into account  N7 {  y: c  @8 \- g* ?8 Z( p
1802905 PSPICE             ENCRYPTION    Incorrect option shown in PSpiceENC syntax in usage detail
& W5 C+ U# o* }1765345 PSPICE             ENVIRONMENT   Custom distributions are not added to the dropdown' y! K' D" R/ D3 r
1784856 PSPICE             ENVIRONMENT   PSpice ignoring directory changes for Save check point in simulation setup session
, l- c. Y* J7 N1817805 PSPICE             ENVIRONMENT   Incorrect result for PSpice 'Start saving data after'
" j+ Z! R" T2 t/ i5 {  c1784507 PSPICE             FRONTENDPLUGI Spelling of 'Definition' in PSpice Part Search is not correct
) F$ L# v! \! i3 q/ d: w1801790 PSPICE             LIBRARIES     SAC model giving errors: A3 d& A% L$ o
1738776 PSPICE             SIMULATOR     PSpice simulation stops before TSTOP1 P5 Y3 [( x; D" B3 f! E- T  L
1795950 PSPICE             SIMULATOR     Simulation cannot be completed in release 17.2-2016 but is completed in release 16.65 L8 Y' h5 J1 H$ d1 k2 i- z
1803407 PSPICE             SIMULATOR     Getting convergence error on a model) w8 k7 y3 m" p$ J- p* N" {
1814759 PSPICE             SLPS          .INC file is not working with SLPS
  T0 |3 Y' t0 w  G, x( }1715859 SIP_LAYOUT         ETCH_BACK     Etchback mask not overlapping each other; creating floating metal0 G8 \: L% I) O! F
1729523 SIP_LAYOUT         INTERACTIVE   When creating a bond finger solder mask the results do not match the required settings& H+ y8 O3 t. w  A5 d
1800069 SIP_LAYOUT         INTERACTIVE   Corrupt dra/psm symbol, but the reason is unclear
0 T& C+ w" l' J( W! p2 H5 O1756620 SIP_LAYOUT         SHAPE         Performance issue when moving vias.
7 r) H7 P1 w' d8 W. c1782928 SIP_LAYOUT         SHAPE         Shape merging (logical operation) shows error though measuring shows elements are correctly spaced( B* L% V7 r$ G  [* q- M6 m- y
1816454 SIP_LAYOUT         THIEVING      Thieving: need thieving as a specific data type in CM to better control the filling pattern
' ?$ o9 [! {) c! f: [1728026 TDA                CORE          Check-in should not require all child objects to be checked in specially if they are not checked-out8 N" \5 Q0 P# P1 N/ n) I7 `+ k8 U
1823976 TDA                SHAREPOINT    Connection to server terminates when joining a project
+ a% b& c4 c3 E* R# J! G9 O& J+ A+ W

: y6 `1 e" L, P$ P) ]Fixed CCRs: SPB 17.2 HF030
0 W) n) N; p* ]" E11-17-20173 ~2 }' ^: d' \5 h
========================================================================================================================================================# z& H" g4 P/ I! T0 I2 P$ l
CCRID   Product            ProductLevel2 Title
" w* F% c* C; u( a5 S========================================================================================================================================================) C8 M* N% p* _0 J
1821774 ADW                DBEDITOR      MPN is tagged Pending Purge after deletion and lib_dist% _* D7 h+ ~$ m2 z8 ~; C
1829549 ALLEGRO_EDITOR     DRC_CONSTR    Dynamic phase DRC marker displayed at the design origin
/ F( `- z3 H+ d- {' M% \1690998 ALLEGRO_EDITOR     INTERFACES    Runtime error when running PDF Publisher# L8 v) A) T/ H$ ]6 g8 D
1805203 ALLEGRO_EDITOR     INTERFACES    Runtime error when exporting smart PDF on a large board with all film layers selected4 @  D! A7 s6 [7 ~$ w  g
1811698 ALLEGRO_EDITOR     INTERFACES    Runtime error while exporting PDF
5 C/ T6 V. p6 A6 Q1 `; i$ K- ]. _1823818 ALLEGRO_EDITOR     INTERFACES    Cannot map some step models- S, I7 V* C0 i# `6 a5 N1 r. |
1750654 ALLEGRO_EDITOR     MANUFACT      Cut marks cannot be generated on cut outline.3 d' A0 j5 Q% g0 K) [: c) c
1828293 ALLEGRO_EDITOR     NC            Incorrect status returned for backdrill
6 [, G  G8 N# C1825401 ALLEGRO_EDITOR     PADS_IN       In PADS library translation, pads_lib_in fails to create Placebound_Top as a shape7 a; a- d( A3 M$ `" T' ?
1825427 ALLEGRO_EDITOR     PADS_IN       Symbol drawing files (.dra) created after PADS Library translation are not getting renamed to their decals" p2 l2 W# Q6 z& n' Q, C
1825460 ALLEGRO_EDITOR     PADS_IN       Pins are moved from their correct locations during PADS Library Translation
9 m( Q" A; |* f, V3 G0 }5 Z1831200 ALLEGRO_EDITOR     PLOTTING      Incorrect PDF output for traces; r! p" Z$ r$ t0 U! s+ c5 T
1321314 ALLEGRO_EDITOR     SHAPE         Force update of dynamic shape generates thermal tie that causes net to short
0 i( M: F, S9 l: S  O5 _( H  o1647585 ALLEGRO_EDITOR     SHAPE         Void around holes is not circular but of the shape of the bounding box
* h/ l9 h" x2 L8 n5 E1830676 ALLEGRO_EDITOR     SHAPE         XHatch Shape not voiding properly/ X/ L  @# q7 W' [
1821286 ALLEGRO_EDITOR     SKILL         Using axlSetParam to set static shape clearance parameter crashes PCB Editor1 p7 Y) @; |( O# n% v
1804662 ASDA               DARK_THEME    Dark Theme: Change color of selected cells in Rename signals dialog so user can see they are selected5 T+ h( d9 d% l+ {& \4 X, R
1817486 ASDA               NEW_PROJECT   Need to save a project with a new name, 'copyprojectas' does not seem to work
$ i  {* r" z5 S" o* J1826023 ASDA               NEW_PROJECT   SDA requires user to go into project settings window twice to add a library
% o/ s# ?5 C6 B8 G, t; V" U- [1830632 ASDA               SCRIPTING     SDA crashes when you type 'find -types' in the Tcl command window. ]7 t( ?6 v) q4 _9 h) L! ?
1798864 ASDA               VARIANT_MANAG Retain default part visibility when substituting preferred part for variant
0 n! G1 @& [$ @7 E) U. G1798865 ASDA               VARIANT_MANAG Value attribute of variant is off while printing though on for default and view
' n" D; s" Q1 h& c% o) V: O0 f1798866 ASDA               VARIANT_MANAG Variant Printing: Pin numbers printed though set to off on default part/ ?4 x) k" O! T( ?# H  V, I' u; C
1831836 ASDA               VARIANT_MANAG Cannot delete existing variants in design( \! E/ V" h! l3 L0 j0 h: R
1821120 CONCEPT_HDL        CORE          SIGNAL_MODEL attached to a component is not displayed on the canvas in the Attributes form, u9 L; I1 v9 n7 o+ B- h( C7 L
1824714 CONCEPT_HDL        CORE          Display issue: Page border disappears when running the command _movetogrid
4 Y1 T2 d7 i! B- B% [1822587 CONCEPT_HDL        CREFER        CRefer crashes on a hierarchical design using split blocks
# V7 S# f/ q6 A, t3 P4 K* ~! U1825461 CONSTRAINT_MGR     CONCEPT_HDL   Uprevving to release 17.2-2016 adds NO_XNET_CONNECTIONS on components having custom models
3 d- M1 Y) x: O9 R8 M. [  E1825968 CONSTRAINT_MGR     DATABASE      cmxlGetObjects returns all the aliased nets and the physical net that goes to the netlist  s0 ]2 Y- \1 }+ k. a
1819622 CONSTRAINT_MGR     XNET_DIFFPAIR Discrete with NO_XNET_CONNECTION removed from topology when extracted with Routed Interconnect
' p2 F7 L0 a% e- \  s1829762 ECW                PROJECT_MANAG Pulse log in: Multiple processes triggered, generating many zip file packets and corrupting many of the packets
) s% b$ |! x+ }; b, m, R9 |4 b# L  E1810296 F2B                BOM           BOM includes status column,  nothing should ever be forced on a users BOM output
6 y7 t9 w0 \- t! e% y! |, c& W1824593 F2B                PACKAGERXL    PXL crashes and removes the pxl.log file from the Packaged directory( ?0 m. x: G. c0 P) s% l- K
1832005 F2B                PACKAGERXL    Message stating 'PXL has stopped working' when packaging design
% M; m+ ^1 ], Q( h1 D1 c4 E" c1822912 RF_PCB             AUTO_PLACE    rf_autoplace fails for RF component containing variable
- _2 n: o2 F7 q9 a1 V& M1803731 SIP_LAYOUT         DXF_IF        DXF export from 'Component Geometry/Pin_Number' subclass not working in release 17.2-2016
& H3 u% r; c1 p5 h1 `, _& W6 X9 X+ [1825478 SIP_LAYOUT         SHAPE         When running the Shape Islands report it is listing all the Fillets as Islands
3 ^4 @. r- `+ e0 i% R0 o
9 q: x, u. H. U. ^4 Q
) R6 E7 p4 r# Q, ^Fixed CCRs: SPB 17.2 HF029
. {! I% n* E/ W. h$ n" U11-3-2017
- f) m3 o8 I; \* h7 G# T========================================================================================================================================================; o7 F* [! q. [  i4 d- o
CCRID   Product            ProductLevel2 Title
5 Q0 r' F( F+ u1 o6 C9 ]========================================================================================================================================================% E5 Y6 W/ x* O6 H7 [, G
1814597 ADW                DBEDITOR      Associate part classification is very slow in release 17.2-2016 of Allegro EDM# Y$ w% e$ Y0 i$ F) [# T
1733482 ADW                FLOW_MGR      After installing QIR3, Flow Manager prompts with Java Help question
! {1 d. [. y/ `% t1814789 ADW                PART_BROWSER  PTF shows data in old component browser but not new component browser5 {2 G" b! c% ]+ H
1808620 ALLEGRO_EDITOR     DFM           Missing graphics in new drc browser.8 G8 Y( t( v6 v( ~2 T
1814558 ALLEGRO_EDITOR     DFM           Silkscreen checks do not work if silkscreen is defined as mask in cross section
) r/ \. J+ a2 B" W# ]: I1807996 ALLEGRO_EDITOR     EDIT_ETCH     Route Clearance View is not using the correct spacing constraint when nets are partially routed in a region5 u: w5 |1 y; O, h& r1 N/ R7 l
1747929 ALLEGRO_EDITOR     INTERFACES    Cannot import logo/bmp on a .dra file5 s4 i2 D4 m2 V. c  T+ \2 M9 S8 s9 ~
1820142 ALLEGRO_EDITOR     INTERFACES    pdf_out command not supporting UNC paths for the output pdf file1 F! G$ o& Z6 l6 Y
1671865 ALLEGRO_EDITOR     MANUFACT      Exceeding 20 characters in Artwork Control Form - General Parameters - Prefix displays 'Illegal Character(s)' error5 ?( K" {7 C$ H7 R$ r6 ]7 `* _; o
1710032 ALLEGRO_EDITOR     MANUFACT      Adding Artwork prefix gives error for illegal characters
& E! J& K& g! U# _" u( X1714911 ALLEGRO_EDITOR     MANUFACT      ERROR: 'illegal character(s) present in name or value' while adding prefix in Artwork Control Form" G  Y; t! |8 g0 V9 \. W2 q
1813950 ALLEGRO_EDITOR     MANUFACT      In the drill chart, the titles 'tolerance_drill' and 'tolerance_travel' seem to be reversed7 e% b* Q! e/ E
1820970 ALLEGRO_EDITOR     MANUFACT      IDX_EXCLUDE and BOM_IGNORE excluding objects from IDX export
# L7 d5 R7 h( w! o1822045 ALLEGRO_EDITOR     PARTITION     Shape fillet becomes static shape and loses fillet attribute after importing partition
8 ?3 @1 R# [" L8 x+ k( a1776181 ALLEGRO_EDITOR     SHAPE         Placing via arrays around a differential pair places vias only for one net+ z2 s$ O9 U* j8 Y% f8 c2 ]
1817283 ALLEGRO_EDITOR     SHAPE         Allegro PCB Editor Show Measure Air Gap shows a very large number2 p+ [) V4 n- A- ~; R
1815595 APD                DRC_CONSTRAIN Differential pair spacing constraint not propagating to physical cset nets4 e1 z! \- e* o, z' f1 B  u6 Y
1785116 APD                SHAPE         Big size die performance issue
6 V4 s: G) z% m0 r7 q1811134 APD                STREAM_IF     GDS stream out with 2000 precision has sharp edges along shapes.) W8 t/ Y, Q% }
1811882 APD                VIA_STRUCTURE High-speed via structure refresh fails
6 T% Z, x$ i6 x  y3 R4 _- b1814878 ASDA               DARK_THEME    Part Manager: Difficult to read black text on black background
3 ^4 ^, i8 \+ ?* N0 G1814889 ASDA               DARK_THEME    Change 'updating route in progress' message color: a bright orange bar in dark theme is difficult to read
7 Q/ u& z$ ]8 b) K* y4 P1817355 ASDA               PAGE_MANAGEME Double-clicking a library in project preferences library does not move the library but changes appearance
" g: e; a( ?) I; \" Q. _1817964 ASDA               SHORTCUTS     User Preferences shortcut misspelled
7 _1 L# o$ F( a$ b* D1 {6 ?1820247 CONCEPT_HDL        CORE          DE-HDL crashes while saving a design, A6 s8 W* G. o/ V7 k# L
1823187 CONCEPT_HDL        CORE          DEHDL allows editing of the locked component's refdes using change text editor, r5 y8 m6 n( n8 q' H' H
1824052 CONCEPT_HDL        CORE          Trying to edit on a group containing a LOCK component, deletes the packaging data on the schematic
- Y: ~5 [' k9 S1 L1813987 CONSTRAINT_MGR     OTHER         PCB Editor crashes when Constraint Manager is closed' B; q: O$ Q, R
1821129 CONSTRAINT_MGR     XNET_DIFFPAIR Uprev to release 17.2-2016 adds unwanted NO_XNET_CONNECTION property to discrete symbols
1 n5 J) B2 A5 g5 M7 q6 Q8 {2 i1814725 PSPICE             PROBE         PSpice Measurements crashes PSpice for a digital simulation8 B, X9 C# K  R; u( f+ Y& o0 m
1808672 SIP_LAYOUT         INTERACTIVE   create bounding shape command options: 'Min Area' and 'Sync with shape layer'
6 B! B# t  e" Y/ a) E& v) ^1817458 SIP_LAYOUT         MANUFACTURING Error in DXF conversion after updating SiP Layout  from Hotfix 066 to 082 in release 16.6
- r8 c* J$ n3 Q
9 L7 m( R! M7 o/ e: j  U6 U( z1 A; I; c1 z2 D: j4 q, S
Fixed CCRs: SPB 17.2 HF028
4 |$ _0 g, z% Z( K3 k3 A5 a: c) T10-14-20178 U! q& B1 C& f2 F9 h
========================================================================================================================================================
. k' a- ~4 v# l  G' f+ P4 x9 RCCRID   Product            ProductLevel2 Title
: [, j3 t" D$ C2 X8 v* a% ~$ i========================================================================================================================================================
3 z. n0 I$ T' f1773530 ADW                FLOW_MGR      DE-HDL hangs on importing components from another design or copying and pasting components within a design
4 S4 ?. y9 D% c1 o, V+ }1790584 ADW                FLOW_MGR      SKILL code for comparing two PCB Editor .brd files does not work in EDM in release 17.2-2016, Z8 t, x6 g" v, M2 n
1794116 ADW                FLOW_MGR      LRM fails to run on project! d0 C5 k9 H7 i$ S% @) X- U
1811532 ADW                FLOW_MGR      The message for missing tools.jar should not appear in adwcopyproject.log
( B- j& e* r" k6 R1812109 ADW                LRM           Library revision manager displays errors while re-importing updated sub-blocks
7 u' T! j' Y) `1771851 ADW                PCBCACHE      Problem in packaging upreved imported block7 j6 z' f1 e" c6 ?$ ]
1814785 ALLEGRO_EDITOR     3D_CANVAS     PCB Editor crashes when a bend is created and then viewed in 3D Viewer
  F* G" Q- B; u' P; u2 x1800131 ALLEGRO_EDITOR     DATABASE      allegro_downrev_library utility fails on Windows 108 n) a: Y( J5 w% q! V+ A
1814607 ALLEGRO_EDITOR     DFM           DFM check for soldermask does not include Package Geometry/ Soldermask if the soldermask is part of stackup) |- t: q4 c8 ]- C
1813996 ALLEGRO_EDITOR     EDIT_ETCH     Add Connect crashes PCB Editor if clearance view is set to channel# |7 w$ J1 |6 _+ l
1810832 ALLEGRO_EDITOR     SCHEM_FTB     Error while doing Export Physical from DE-HDL to PCB Editor/ H$ H* ~5 i6 K" f. h
1811785 ALLEGRO_EDITOR     SCHEM_FTB     Import > Logic > Import Directory does not resolve the relative path to the packaged folder
: q5 _( n( ]( G* n" Q/ [1814166 ALLEGRO_EDITOR     SCHEM_FTB     Error message when exporting design to board using an earlier version of database" U' W  v5 S, E( S9 i% j
1817891 ALLEGRO_EDITOR     SCHEM_FTB     Error message when exporting design to board using an earlier version5 {$ ?, j  `. ^; V
1818954 ALLEGRO_EDITOR     SCHEM_FTB     Error message when exporting design to board using an earlier version of database3 ?- [- k7 \& l" r
1812808 ALLEGRO_EDITOR     SHAPE         Artwork is different from PCB board2 m: n3 J" R8 m% N+ b# _
1814836 ALLEGRO_EDITOR     SKILL         Doing zcopy Xhatch pattern crashes PCB Editor in release 17.2-20160 ]4 T9 S, M6 b" r$ H0 J
1772218 ALLEGRO_EDITOR     UI_GENERAL    PCB Editor stops responding on Show Element3 b& G' {  e4 z! G
1778353 ALLEGRO_EDITOR     UI_GENERAL    Intermittent PCB Editor crashes on loading IDX in release 17.2-2016 Hotfix 020# ?* u( @4 q8 g1 e- H; @# g/ o9 ~% T
1818077 ALLEGRO_EDITOR     UI_GENERAL    axlViewFileCreate disappears behind window or is blank) c% j% K# e) S! n. \) E8 l
1807423 ASDA               NEW_PROJECT   SDA CPM file has erroneous date3 U* t/ Q' [, R% [' b
1809597 CONCEPT_HDL        CORE          Problem auditing SI model in Allegro Design Entry HDL from Hotfix 025 onward, no problem in Hotfix 024
( j, P$ }# c9 X' e- h7 G. {1810322 CONCEPT_HDL        CORE          Unable to package design if OK_NET_ONE_PIN property is set
4 ^: u; K5 I; P4 r# G0 x1813436 CONCEPT_HDL        CORE          Read-only block import issue in same session: displays error message SPCOCD-553
; W6 y% u, C& {( x6 S1813912 CONCEPT_HDL        CORE          The response in DE-HDL is sometimes extremely slow
6 P+ S' S3 K" z; {* v# T1812506 CONCEPT_HDL        INTERFACE_DES Error messages during packaging followed by a success message though there are errors in design
, R% }, o1 B2 H6 Z% a* f+ f4 d1808677 CONSTRAINT_MGR     CONCEPT_HDL   Auto-generation of differential pair finds several instances of the same net( v  T& s1 P) k2 h# u7 {
1808898 CONSTRAINT_MGR     CONCEPT_HDL   Unable to resolve the ECSet mapping errors if the topology has pin of PINUSE POWER & GROUND' o& k% i2 g/ F8 q( i
1810320 CONSTRAINT_MGR     CONCEPT_HDL   DE-HDL - Constraint Manager:  Cannot add group to net class if a net in group is a member of the net class0 H8 B( b. t% f8 K
1812459 CONSTRAINT_MGR     CONCEPT_HDL   Auto-generation of differential pairs has issues
% ?* c- P- P9 ]7 k) K" Z6 P# Z1796234 CONSTRAINT_MGR     OTHER         PCB Editor crashes on query (ALLOW_ON_ETCH_SUBCLASS) without data type defined. K' @' h* B. l* [: b9 y
1811692 CONSTRAINT_MGR     OTHER         Constraint Manager: Set Topology Constraints - Rel Prop Delay - Pins is empty in release 17.2-2016 Hotfix 026: P- m; C! }, o  D
1816311 CONSTRAINT_MGR     XNET_DIFFPAIR Extracting a differential pair into SigXplorer crashes DE-HDL; g3 r, i! u/ T5 X& @% l
1807593 ORBITIO            ALLEGRO_SIP_I Die symbol shifts when importing die from OrbitIO to SiP Layout+ z: ?8 a$ `+ X, F0 u1 v/ [4 b
1800763 PSPICE             SLPS          Error while running co-simulation in MATLAB for PSpice-SLPS demo designs
( q! {) L- x! b* S6 t
' ]! {" R7 O: W2 g8 v5 q/ e
( F7 {; o& b/ T; J0 W' M% E! MFixed CCRs: SPB 17.2 HF027/ ^$ b/ ~& h& j
09-29-2017  L& c( S3 G0 i. D/ g
========================================================================================================================================================( `4 c: a3 D% O/ U* N. J; k
CCRID   Product            ProductLevel2 Title
2 L/ Z' \. |. D8 `* _7 F========================================================================================================================================================2 _5 B3 \" O6 D# u
1795353 ADW                FLOW_MGR      Tool unable to find project in windows_project.txt; B/ Y  X3 Z( r# N
1810386 ADW                FLOW_MGR      Error regarding not finding project in 'windows_project.txt') Y3 G( N6 L/ i7 C/ M' L
1743732 ADW                LIBDISTRIBUTI adwserver -install does not give error if it cannot connect to server.. Q+ }- b' i- }" V6 B$ F
1804378 ALLEGRO_EDITOR     3D_CANVAS     Bend area issues in 3D Viewer8 n* M1 o( I9 Q; _# P
1795312 ALLEGRO_EDITOR     DATABASE      Cannot unlock symbols as status is changed to View on opening design+ X" [8 _" E2 ]7 c& y6 W
1803262 ALLEGRO_EDITOR     DATABASE      Donut pad With DYN_THERMAL_CON set to FULL_CONTACT has connectivity issues
- J5 W1 ~8 Z  q$ h2 u1802183 ALLEGRO_EDITOR     DFM           Using mouse wheel to scroll error information in DRC Browser changes font size) Z7 q6 y9 t' W' y3 S* T' a/ _, E
1797222 ALLEGRO_EDITOR     DRC_CONSTR    Updating DRC results in error 'SPMHDB-403'' d# D  M7 w6 s7 [- j0 U. N3 K6 l
1792163 ALLEGRO_EDITOR     EDIT_ETCH     PCB Editor crashes on moving components6 X2 q8 Q- u7 {- d, @% J! P1 v. D0 E
1806640 ALLEGRO_EDITOR     INTERFACES    Step Mapping not working in release 17.2-2016 Hotfix 025  O$ J, `2 [7 J! o
1807278 ALLEGRO_EDITOR     INTERFACES    Running 'step_export_product_asm.exe' displays 'vcruntime140.dll' missing error- v3 E( g7 L- y, U2 w! ]
1807286 ALLEGRO_EDITOR     INTERFACES    The facet file (.xml) for the STEP model 'modelname.step' cannot be found.  f7 v! v; }3 x( R+ `; E. F2 a5 C
1808006 ALLEGRO_EDITOR     INTERFACES    Facet file for step model cannot be found$ l: ~) o' i. a( X9 B
1704335 ALLEGRO_EDITOR     MANUFACT      Documentation Editor shows an error about backdrill while no backdrill was used in the design
' s7 u. s0 j+ d7 ?2 q4 g1800115 ALLEGRO_EDITOR     MANUFACT      IPC2581 Export giving error that backdrill is out of date even though no backdrill is defined in the design- q2 x2 z6 {; Z; M# z
1799444 ALLEGRO_EDITOR     PLACEMENT     Via Array - Boundary placement fails with error% G- B: s, L3 X$ I
1725242 ALLEGRO_EDITOR     SHAPE         'Same net shape to hole spacing' is only detecting the DRC and not voiding the shape- V" w5 L/ M9 h9 ]% j; e/ V. S7 M, ?& c
1804129 ALLEGRO_EDITOR     SHAPE         XHatch Shape not voiding properly5 k) B; w* [  @4 U6 ~8 R
1805238 ALLEGRO_EDITOR     SHAPE         PCB Editor crashes while importing netlist$ M4 {6 q  q3 ^. ?
1803542 ALLEGRO_EDITOR     SKILL         Using axlPadstackEdit to change drill size causes via net to change in release 17.2-2016 Hotfix 0255 O3 K0 s* U6 q: B: c; }2 E, l3 d0 z4 i
1800774 APD                STREAM_IF     Only one pad in GDSII when running 'stream out' with the Flatten Geometry option
. ~& U  v4 }5 h5 S1804196 APD                STREAM_IF     Component is mirrored by X-axis instead of Y-axis on enabling mirror geometry
, r1 N# Y; t1 u0 D3 Q& r1 _& p1803375 ASDA               IMPORT_BLOCK  Import HDL Block fails with message regarding Xnet states and DML independence
& X8 N# H6 f% ]2 A1807423 ASDA               NEW_PROJECT   SDA CPM file has erroneous date, w, [! V) K/ g* `& t! n
1789400 CAPTURE            SCHEMATIC_EDI Capture schematic opens unannotated pages on search, s. E" A8 R' H: D/ B- j
1801573 CONCEPT_HDL        CONSTRAINT_MG Upreving release 16.6 design to 17.2-2016 adds NO_XNET_CONNECTION to some components/ f* b$ |; q7 o2 y0 w/ P# a
1810586 CONCEPT_HDL        CONSTRAINT_MG DE-HDL crashes when transferring XNET properties to similar components in a read-only block) y* l: d& I9 g
1794169 CONCEPT_HDL        CORE          _automodel command crashes DE-HDL if PACK_IGNORE is set# [. h! F: @5 v% G- Z5 N% @% U5 _
1798672 CONCEPT_HDL        CORE          Dashes in design name creates an extra design folder in worklib after upreving to release 17.2-2016. `; J$ d2 E6 Z1 o& E
1802258 CONCEPT_HDL        CORE          Locking unlocked components results in a warning (SPCOCN-3403)
3 F( Q$ [9 h( l! m0 |! Q! ]& `1803019 CONCEPT_HDL        CORE          DE-HDL crashes on backannotation
& b9 `* j# e: Y5 \( L1803615 CONCEPT_HDL        CORE          After running 'Mark for Variant', the block cannot be changed to blue
6 R  P( l. A1 l9 x1 Y+ q" Z8 E( I1804029 CONCEPT_HDL        CORE          Visibility issues when using the LOCK functionality; U: P- e, j: C% h: J: r/ o
1806352 CONCEPT_HDL        CORE          Group Mirror is causing design corruption.
( t2 U  G" ?; F* h1 ^9 |7 ^1806978 CONCEPT_HDL        CORE          Cannot mirror a group of  objects
* o0 m# _" s+ |; @7 v1810387 CONCEPT_HDL        CORE          Mirroring groups causes erratic display and may corrupt database if project is saved
0 D! P% v. G9 r& w1812811 CONCEPT_HDL        CORE          Schematic group mirror not working
7 g$ V! a7 e# {. U* V! \, Q- ~' ~1810401 CONCEPT_HDL        INFRA         Add Signal Name: Cannot select suggested net name
5 e5 s6 i9 v$ k/ {; `" r- Q1787409 CONCEPT_HDL        PDF           Minus character at the end of netname causes unexpected string concatenation during PDF Publish
0 }$ X; C* ]. n( h+ b5 u. d! ?% P1800931 CONSTRAINT_MGR     OTHER         Even after removing NO_XNET_CONNECTION on parallel termination, topology extracted has duplicate capacitors0 F9 d, `! E. M1 k  M
1790106 CONSTRAINT_MGR     SCM           Cannot find the constraints file (0) in the schematic project: L6 i5 [9 l: j" ~
1787117 CONSTRAINT_MGR     UI_FORMS      Creating bundle in Constraint Manager crashes PCB Editor
" h$ V* s7 `6 x& r: t, ^2 T1797384 ECW                METRICS       Pop-up metrics value tool tip is translucent, making values hard/impossible to read( d$ Z* W/ J/ h5 v5 m1 c0 _
1803226 ECW                METRICS       Pop-up metrics value tool tip is translucent, making values hard/impossible to read
- D# m" l7 c$ V! G( E' A1664059 ORBITIO            ALLEGRO_SIP_I Incorrect connectivity after .brd import; ]+ E8 _: ~6 @' [; u
1799338 SIP_LAYOUT         DRC_CONSTRAIN Multi-threaded DRC fails with internal memory error even after setting shape_cache_size" E8 o0 {1 p' R, P
1799499 SIP_LAYOUT         DRC_CONSTRAIN Multi-thread DRC fails
/ [% I2 O0 M, u1 q. V1806585 SIP_LAYOUT         DRC_CONSTRAIN Multi-threaded DRC update aborted: internal memory resource depleted; c4 E" N2 Z7 x) l- Q2 _
1809804 SIP_LAYOUT         DRC_CONSTRAIN Error message while updating DRCs in release 17.2-2016 Hotfix 026 regarding shape_cache_size% D; }$ |' _* }4 _
1788770 XTRACTIM           ENG           Translated bump / ball conductivity is wrong (PowerDC and XtractIM)
  B5 k% ~( o8 f+ h8 A
8 @5 o: R" u- ]" l
# J* D- V4 E$ S/ [( ?/ [2 I4 c/ X$ mFixed CCRs: SPB 17.2 HF026- D6 Q* p  M" t( T& b! d, e- Q* ?! v- k8 D
09-15-2017) |- L3 e, q6 _0 N1 m0 O( [2 |4 f
========================================================================================================================================================
7 y) r0 B  G7 B! fCCRID   Product            ProductLevel2 Title( X7 Z) N% R$ D2 U$ y/ m4 D
========================================================================================================================================================& m  z$ o3 d6 K
1765398 ADW                DATAEXCHANGE  Duplicate  MPNs are created when updating MPN classification properties with data exchange
5 ], A" |+ l2 W# v' \; q( K4 i2 T1780147 ADW                DBEDITOR      'Associate Footprint from Tree' does not log the information8 i: O# U% C4 u, s5 V' P. b. Y# K8 s
1790134 ALLEGRO_EDITOR     DATABASE      Correct spelling  in Layer Function definition& T( l; ~8 x, e* x
1792345 ALLEGRO_EDITOR     DATABASE      Pastemask is added to bottom layer on backdrilled pins
; v! A! ^5 L; u& P0 F/ c, i( l1792930 ALLEGRO_EDITOR     DATABASE      Uprev required for all libraries and padstacks to use release 16.6 DRA in release 17.2-2016  e7 F7 ?0 w& r( I8 d
1781203 ALLEGRO_EDITOR     DFA           DFA Spreadsheet Editor not starting from Windows Start menu
# ^4 }6 g1 m* Q* Y3 U1797422 ALLEGRO_EDITOR     DFA           DFA Spreadsheet Editor not starting from Windows Start menu
% R+ J1 O  q8 b3 t1770694 ALLEGRO_EDITOR     INTERFACES    Incremental IDX does not place unplaced components" Q7 O" I0 q/ E8 q4 c! _
1776791 ALLEGRO_EDITOR     INTERFACES    STEP file not displayed in PCB Editor for mapping
& c$ t% ~  H' |, {1783515 ALLEGRO_EDITOR     INTERFACES    PCB Editor reading step model incorrectly
4 ]8 P' ]9 G" d! ^' O1781485 ALLEGRO_EDITOR     MANUFACT      Setting ipc2581attrpath results in error 'E- ipc2581attrpath: Variable not defined'
; n- l' T0 R* ?' P) X3 u1772713 ALLEGRO_EDITOR     MULTI_USER    Allegro Symphony Server rejects group moves
0 M* u. N5 {6 c2 e8 G4 T) x( }7 B1789853 ALLEGRO_EDITOR     MULTI_USER    Symphony Server rejects updates and hangs frequently
" ]' f% l$ y2 J5 z/ A' o, d1725591 ALLEGRO_EDITOR     OTHER         File - Export PDF crashes on the design attached6 t! h. h7 {3 t$ F5 V/ C
1736324 ALLEGRO_EDITOR     OTHER         Export - PDF fails to export PDF. v% [4 p* B/ w/ T: q( K
1794071 ALLEGRO_EDITOR     PLACEMENT     The placement of component is very slow and takes around 3 to 5 minutes per component.+ D  j: k' E/ _; S$ r0 \
1496199 ALLEGRO_EDITOR     SHAPE         Overlapping route keepouts result in a broken shape.5 F! r; j0 Y) l5 |: Z0 y" w
1760146 ALLEGRO_EDITOR     SHAPE         Void offset in Artwork but not in board for a particular instance only, e- ^& Z3 v4 m/ k
1770372 ALLEGRO_EDITOR     SHAPE         Overlapping shapes merged in artwork shifts void causing a manufacturing short
/ c% N9 v: X) Q( q4 X1793419 ALLEGRO_EDITOR     SHAPE         Unexpected shape void in artwork in release 16.6* H$ h3 X0 j* X$ k  {7 m
1796666 ALLEGRO_EDITOR     SHAPE         DRCs for out-of-date shape while placing single via
3 S4 s1 V& |# u& l$ l! Q$ T1786386 APD                EXPORT_DATA   Exported dra and pad files do not have right stackup7 a1 V5 p9 ^- }7 o! c" v
1765673 APD                SHAPE         Shape in Cu1 and Cu3 cannot void correctly3 x/ e( {  W2 G3 Y! i7 r1 s
1782418 APD                SHAPE         Artwork is showing unnecessary horizontal lines
7 f  G4 e9 m! H; K1 D  U1778366 CONCEPT_HDL        CHECKPLUS     CheckPlus not printing logic design name
1 M  l: k" I+ a3 U/ U9 M1723855 CONCEPT_HDL        CORE          Cannot use Rename Signal for unnamed wire segment if the wire has a branch to the same instance- y0 L1 X5 n# }! w( o/ v
1755174 CONCEPT_HDL        CORE          Unable to create XNETs on the read-only blocks( r$ X+ ~: S4 t1 g$ W9 h
1765533 CONCEPT_HDL        CORE          Strokes are slow to respond in release 17.2-20165 u+ Z3 s; L/ f. o0 d- q6 W4 V
1780253 CONCEPT_HDL        CORE          In Windows mode, with copy command still active and symbol on cursor, DE-HDL stops responding on pressing Delete key: d# q7 o' z# |; f- h3 r  ^& h
1785069 CONCEPT_HDL        CORE          Warning box for SPCOCN-2251 needs to be resized and the text formatted correctly) P8 [0 u7 N3 z- }+ p" S
1786030 CONCEPT_HDL        CORE          Packager fails in release 16.6 but runs successfully in release 17.2-20169 U* E: }2 o2 Z2 c7 x& F( g5 S+ V4 N
1788077 CONCEPT_HDL        CORE          Creating new window (new tab) in DE-HDL resets view of original window: ]4 o  N2 L4 S3 @6 W0 ~4 b# e
1788591 CONCEPT_HDL        CORE          Wrong pin number displayed after running packager8 U" l; I% j$ h1 k  a% X
1776774 CONCEPT_HDL        CREFER        CRefer crashes without error entry in log file' ~* x# h" }+ m
1328320 CONCEPT_HDL        PDF           Cannot select/search sig_name in published PDF
6 j( a  [/ F# t  r, C1787409 CONCEPT_HDL        PDF           Minus character at the end of netname causes unexpected string concatenation during PDF Publish
( j3 j$ `& w4 l+ _1758122 CONSTRAINT_MGR     ANALYSIS      Extracted topology for a differential pair is missing a pin-to-pin connection in the top file
3 N+ t+ _6 {% I/ g& s% W- [; [( F1786161 CONSTRAINT_MGR     CONCEPT_HDL   Random crashes in release 17.2-2016 while working on the schematic editor along with Constraint Manager
8 n$ O8 Q8 \: j0 e1788877 CONSTRAINT_MGR     DATABASE      Constraint Manager API cmxlImportFile looks for sub-string during replace mode and not explicit names2 P! B, b) |) |6 s/ P+ x. k  T( D
1800263 CONSTRAINT_MGR     OTHER         DE-HDL and CM crash when deleting regions  k' C; P1 y6 [5 b
1792000 CONSTRAINT_MGR     UI_FORMS      Data type of constraint not shown in GUI2 F5 {* E5 k+ ^5 l
1744828 FSP                CAPTURE_SCHEM Button appears during 'Generate OrCAD Schematics'
0 e: x# m& F6 E0 ]& }* C) E1747568 ORBITIO            OTHER         Import of .oio file in SiP Layout takes a long time) d% s' A: q& t6 V' L' e' b; i+ s
1765229 PSPICE             AA_FLOW       Not able to run PSpice MC after setting Assign Tolerance
  }( q5 T7 f. e. t5 X+ {1770174 PSPICE             MISC          Issues with DMI Template Code Generator" c, C2 y$ G! [

0 M( f7 P# U4 g
- N3 \6 U, m8 aFixed CCRs: SPB 17.2 HF025+ @; v' `; W" t) `6 W4 v
08-25-2017
; B8 i) V  ?$ e# k4 z6 R% L/ u$ R========================================================================================================================================================. Y- E3 ~. P, X) I+ E/ W
CCRID   Product            ProductLevel2 Title
) l, [' W; q  e; A7 Z5 C6 J# B========================================================================================================================================================; g0 f6 A" s# W% I
1258913 ADW                ADWSERVER     Copy project message: Unable to locate tools.jar* p0 p; P  r6 t+ a$ x: h1 W
1760866 ADW                ADWSERVER     Metrics dashboard in Allegro EDM Configuration Manager does not show updated SPB 17.2 hotfix
+ [* b4 u* Y: d. x" @9 t1055946 ADW                ADW_UPREV     Set PTF_SUBTYPE SEARCHABLE to false and default value to exclamation mark
4 F% w/ O3 u; j# K9 Z. g1508163 ADW                COMPONENT_BRO Manufacturers Part tab disappears on clicking anything other than the part number in the left tree
$ l1 R8 w  g2 b. `. {1774164 ADW                COMPONENT_BRO In release 17.2-2016 Hotfix 22, DE-HDL crashes on using Generate View
0 [$ G( f7 [4 ^; g# e. }0 z1345018 ADW                DBEDITOR      Database Editor does not catch empty mandatory properties if no changes are made to the part
$ ~2 {8 i9 I0 i* H# V! P) o1586858 ADW                DBEDITOR      'Access Denied' Error while opening Datasheet Model using Launch Viewer in Database Editor, j0 \7 L+ C( ]
1754185 ADW                DBEDITOR      Max Height value in DBEditor is different from PCB Editor  J% t: K( Z2 W! W
1719260 ADW                FLOW_MGR      Configuration error on a fresh install of EDM in release 17.2-2016 Hotfix 014
: M* X, f  h: S9 k! @1743730 ADW                LIBDISTRIBUTI .lis file error in install_model while using MLR.+ U, ]8 z6 \$ m9 C  D
1757178 ADW                LIBIMPORT     back-end libimport failed, crash and existing flashmodel not found, v9 o+ x" w( c+ z. V
1648609 ADW                SRM           PCB Editor stops responding when launched with -s option in release 16.6-2015 Hotfix 078
% a& ~/ w: E, i7 K! Z4 h; @1731152 ADW                TDA           TDO coredumps after a new object has been checked in as minor and deleted.+ h2 y+ B; c2 d
1766998 ADW                TDA           TDO-ASA: Cannot enable the project for team design until a component is added to the new ASA/SCM design
* {7 x3 e% e) A1695240 ALLEGRO_EDITOR     3D_CANVAS     Interactive 3D View of a package symbol not showing the correct mapped STEP file attached to the package symbol* c" ~  m9 V7 P
1698148 ALLEGRO_EDITOR     3D_CANVAS     Allegro 3D Viewer crashes on Windows 10
6 z) k" I2 S" o5 m5 `# M8 J, U1738655 ALLEGRO_EDITOR     3D_CANVAS     Interactive 3D canvas crashes on Windows 10
2 M$ l3 i* X( I' U% \  m1750001 ALLEGRO_EDITOR     3D_CANVAS     Interactive 3D Canvas crashes on selecting in symbol view
  y$ I  a; S$ f, v2 j! ]1751796 ALLEGRO_EDITOR     3D_CANVAS     3D Canvas shows component placed at wrong layer for Embedded components
4 w$ p1 b0 B+ y! d1768775 ALLEGRO_EDITOR     3D_CANVAS     Allegro 3D canvas closes when Update Symbol is done and cannot be re-invoked" K- f$ |+ W) v  s- ^) J+ J
1695025 ALLEGRO_EDITOR     ARTWORK       Artwork film show shorts.
9 z! t5 v' j/ p0 h  d1708674 ALLEGRO_EDITOR     COLOR         Dehighlight all should disable the check boxes in the color dialog/nets2 I: C7 |2 W, O+ R- X( I
1735522 ALLEGRO_EDITOR     COLOR         In release 17.2-2016, PCB Editor crashes when not being able to write the CVSettings.xml file.0 Y3 u0 U7 {2 ]- L3 u
1764475 ALLEGRO_EDITOR     COLOR         Allegro PCB Editor hangs when selecting OK on the Color Dialog form
4 ]2 v7 D; W# z+ T/ d1718438 ALLEGRO_EDITOR     CROSS_SECTION User interface is inconsistent for the Mask Layer Subclass site file editor.
; ?, L% M% p' K. k1765387 ALLEGRO_EDITOR     CROSS_SECTION Cross Section Editor does not retain or remove layers added/removed from Setup-->Subclasses0 \' c# n6 W! x% g( U3 l7 Z$ U
1714910 ALLEGRO_EDITOR     DATABASE      PCB Editor crashes with blank allegro.jrl file when a release 16.6 board is opened in release 17.2-2016 Hotfix 013
9 \' x9 u) j/ L( ^1769534 ALLEGRO_EDITOR     DATABASE      DBDoctor unable to delete invalid subclass
: Y# u& l4 o) ~2 c4 `& y% C1775705 ALLEGRO_EDITOR     DATABASE      Updating stackup in PCB Editor does not change backdrill status to 'Out-of-Date backdrills'
4 Z9 L" e/ X$ V2 l7 X+ J8 W1778608 ALLEGRO_EDITOR     DATABASE      Rigid Flex design: Components with pads defined on the TOP and BOTTOM layers are not placed on the correct layer' o4 |/ S9 Y9 D$ C. U0 I
1778644 ALLEGRO_EDITOR     DATABASE      Allegro PCB Editor crashes while trying to place dimensions# |, A" v2 ~4 M. |# R
1698695 ALLEGRO_EDITOR     DRC_CONSTR    Line to Mech-Pin DRC not displayed
/ ]8 u' A% s# ?# V* G$ C# _1705214 ALLEGRO_EDITOR     DRC_CONSTR    Shape to drill DRCs not getting void and 'cns_show' does not report constraint value
- o+ J$ ~' Q# ]% E- O( q) j1722841 ALLEGRO_EDITOR     DRC_CONSTR    Inconsistent soldermask to soldermask DRCs on vias as compared to board geometry/soldermask2 M+ A1 E) [& p4 ~8 [
1736116 ALLEGRO_EDITOR     DRC_CONSTR    Shape Voiding and DRC error on layer with no hole or pad definition  F2 ^% w" v7 n4 u" S3 W
1744248 ALLEGRO_EDITOR     DRC_CONSTR    Release 16.6 to 17.2-2016 DML Independent Flow does not resolve differential pair pin pairs Correctly
/ t  M* O2 V) u" _. O+ F1776848 ALLEGRO_EDITOR     DRC_CONSTR    Negative plane island DRC reported in release 17.2-2016 Hotfix 23
7 U; X6 O* U; S7 E7 @1730806 ALLEGRO_EDITOR     EDIT_ETCH     Element 'vias_allowed' is not valid for content model adding high speed via structures, C" y4 {- f; L3 x& O. e
1745332 ALLEGRO_EDITOR     EDIT_ETCH     In release 17.2-2016, PCB Editor crashes when starting Add ZigZag Pattern
; T' q$ \. `7 \+ {( q3 v3 ~+ ]1765555 ALLEGRO_EDITOR     EDIT_ETCH     PCB Editor crashes during contour routing
2 r" D3 F+ n7 ]( w- B; `0 i3 o1644401 ALLEGRO_EDITOR     INTERACTIV    PCB Editor crashes on running the z-copy command
" x; z4 V; E3 G9 K4 _1657621 ALLEGRO_EDITOR     INTERACTIV    Copy cline and via cause redundant vias
) u1 R6 D$ o4 }! }/ \( r- ]1688556 ALLEGRO_EDITOR     INTERACTIV    Limitations with editpad boundary. [* U: {6 J) N) h
1704901 ALLEGRO_EDITOR     INTERACTIV    Changes cannot be done when 'Design outline' is selected
7 i+ S1 n9 F+ c+ E  I1710731 ALLEGRO_EDITOR     INTERACTIV    The Edit > Change command does not select or change the text on a block# s5 X0 m' E! L1 i$ b
1714855 ALLEGRO_EDITOR     INTERACTIV    Placing two objects on the Design_Outline subclass causes PCB Editor to crash
, Q9 M( _  ~8 U4 K1725736 ALLEGRO_EDITOR     INTERACTIV    Edit>Change cannot change silkscreen line to a different class, but works in preselect mode. P9 ]4 D  j2 h9 h: g
1728004 ALLEGRO_EDITOR     INTERACTIV    Text cannot be edited if the Design_Outline subclass is in the selection box
* M$ e2 N: L0 z( K/ u1728794 ALLEGRO_EDITOR     INTERACTIV    The Oops command and the Esc key do not work when moving components in the Temp Group mode
- R/ r+ d1 K" o' v1738070 ALLEGRO_EDITOR     INTERACTIV    Copying shape after Shape Operations results in error 'E- (SPMHDB-72): Current active shape must be filled first'
9 N' p* W+ T4 D  e2 F7 C6 @1750696 ALLEGRO_EDITOR     INTERACTIV    Add notch angle option fails to update if changed while add notch command is active.
) X7 Z- A4 f9 P* ]1 q; @. m9 _7 F6 T1755240 ALLEGRO_EDITOR     INTERACTIV    Copy via does not work
  |+ h& N. |* ^: M# O9 w! r1777416 ALLEGRO_EDITOR     INTERACTIV    Running shape operations results in database corruption, c7 V; a5 Y: t
1715835 ALLEGRO_EDITOR     INTERFACES    When IDX is imported in PCB Editor, all the shapes are created on package keepout on all subclasses. d6 I; \4 ?4 r. T
1744111 ALLEGRO_EDITOR     INTERFACES    Pads rotating 90 degree when exporting DXF file from Allegro PCB Editor2 k8 H5 G/ P( B- z
1736045 ALLEGRO_EDITOR     MENTOR        Third-party import crashes PCB Editor with error stating that .SAV file will be created
8 o/ F) f; o" o* g& U( N# o1751914 ALLEGRO_EDITOR     MULTI_USER    Find Filter options get disabled while creating symbols
4 T! P4 e% `$ J4 I: x! \8 Z1770811 ALLEGRO_EDITOR     MULTI_USER    In release 17.2-2016, axlTriggerSet('exit 'routine) causes a crash while exiting
) g8 H8 S+ n7 T% a1736545 ALLEGRO_EDITOR     OTHER         Spelling mistake in description of no_dynamic_zoom variable in user preferences Editor7 [# l* Y' y8 o* x4 O2 n
1761610 ALLEGRO_EDITOR     OTHER         Dynamic shape is not voiding as expected.5 `5 p& M. O: ?; B
1702535 ALLEGRO_EDITOR     PAD_EDITOR    After modifying a padstack in Pad_Editor, the Update to Design function fails to update the dra file. _! n; `7 M/ W& }4 H% A3 P' Q1 _
1713461 ALLEGRO_EDITOR     PAD_EDITOR    Padstack editor default geometry not working when cell is preselected
2 N0 d4 a( U% t7 H+ l: V9 v: I, _1715702 ALLEGRO_EDITOR     PAD_EDITOR    Donut shape is lost on cutting the pad shape of the donut pad
/ ?3 ?& r$ O% R' V$ ~$ t5 s7 ^1720300 ALLEGRO_EDITOR     PAD_EDITOR    Multi-drill staggered pattern: Different hole placement for first and second rows for releases 16.6 and 17.2-2016. w7 t4 J% O# e+ F4 Q
1724896 ALLEGRO_EDITOR     PAD_EDITOR    Padstack Editor shows flash symbol for regular pad on selecting 'Shape Symbol'6 @4 N2 u1 |% r1 y* e; c
1714839 ALLEGRO_EDITOR     PLACEMENT     Selecting an alternate symbol (alt_symbol) in a group, in the Placement Edit mode, removes the symbol from the group+ f4 R( d" Z7 E: h+ Z: d
1781502 ALLEGRO_EDITOR     PLACEMENT     Quickplace by room crashes Allegro PCB Editor
* z5 t. Y$ S0 I$ l! @1699690 ALLEGRO_EDITOR     SCHEM_FTB     'view_pcb directive' no longer working as expected
' F' t) S% j7 Z- n3 Z* M1758796 ALLEGRO_EDITOR     SCHEM_FTB     PCB Editor launched from Project Manager does not read the relative paths specified in the view_pcb directive, _5 p* d5 R! M4 X( l; R
1761101 ALLEGRO_EDITOR     SCHEM_FTB     On saving a board after import logic in PCB Editor, the file is saved in the cpm location and not in the physical folder$ E8 M# d$ ?) _3 _6 @3 P0 e
1761394 ALLEGRO_EDITOR     SCHEM_FTB     Working directory for PCB Editor changes after import logic& t$ |& h& l% s$ n+ H1 @; [
1714922 ALLEGRO_EDITOR     SCRIPTS       Running script in the non-graphic mode runs the tool graphically: W3 V6 n7 v1 ~! q. n" M+ T, w
1726550 ALLEGRO_EDITOR     SHAPE         Shape failed to connect to pin
6 z4 ~9 a. ~# z* Z/ r; R8 l# q1754945 ALLEGRO_EDITOR     SHAPE         In release 17.2-2016, Delete islands  fails to add DYN_DELETED_ISLAND to voids on Windows 10 systems
8 B* U' Y. D$ @1766280 ALLEGRO_EDITOR     SHAPE         SPMHGE-300 Polygon operation failed because of an internal error
/ C  l/ L0 N5 I9 f% K7 s( ^# W1768307 ALLEGRO_EDITOR     TECHFILE      Properties defined in the technology files are not being imported in a new design
9 {% t/ a. h" s) R$ u5 a4 {. ~7 Z8 s1771584 ALLEGRO_EDITOR     TECHFILE      The tech file import command does not update user-defined property immediately! i: r4 A2 j* M; P4 I* s5 N
1730104 ALLEGRO_EDITOR     UI_FORMS      Change description  of Title bar option variables in User Preferences! \8 B- j. N+ y+ p) L% y$ W& ~
1749272 ALLEGRO_EDITOR     UI_FORMS      etchlen_ignore_pinvia variable needs to be updated
6 {+ C) v- D* z0 u1649254 ALLEGRO_EDITOR     UI_GENERAL    Using wildcard to open padstack file generates error SPMHA1-161 in Padstack Editor in release 17.2-2016
- P9 g6 `- E/ M6 j: v8 n1685985 ALLEGRO_EDITOR     UI_GENERAL    Funckey not working for Display - Measure  z7 @0 E8 |" A4 Y
1687073 ALLEGRO_EDITOR     UI_GENERAL    Show Measure command shifts focus to Search field in result window after selecting first element- R  {' }# z! G* c+ K6 M3 A
1699272 ALLEGRO_EDITOR     UI_GENERAL    File Viewer not displaying HTML files correctly when 'allegro_html_qt' is enabled. U# b, J: D5 |: _0 C& g; n. U
1711321 ALLEGRO_EDITOR     UI_GENERAL    Database settings do not change on changing color settings using the SKILL function axlDBDisplayControl()4 r5 k9 E% ^1 B2 ^1 m3 E+ W4 T* r
1728468 ALLEGRO_EDITOR     UI_GENERAL    The Show Element window takes the focus away from the PCB Editor window9 z" U8 n8 R/ r( {  d( ]5 j8 N, X
1733690 ALLEGRO_EDITOR     UI_GENERAL    Performance issues in Visibility dialog if called repeatedly in release 17.2-2016, Hotfix 017
# K  ?  v- _% |. O- x3 p. \1734176 ALLEGRO_EDITOR     UI_GENERAL    Unable to sort padstacks to open in the padstack editor using wildcards
4 C) d' t" {6 g8 K2 w# k, f1735733 ALLEGRO_EDITOR     UI_GENERAL    RAVEL checks slower in release 17.2-2016, Hotfix 017; s, U- A% W/ t+ v8 [) m5 p5 J2 I
1737545 ALLEGRO_EDITOR     UI_GENERAL    axlVisibleSet is slower in release 17.2-20164 t) a' M3 Z! x' K0 q" _+ W
1744655 ALLEGRO_EDITOR     UI_GENERAL    SKILL code with axlVisibleSet slower in release 17.2-2016 compared to 16.6
9 r/ A6 Y  V% f7 x$ R1759380 ALLEGRO_EDITOR     UI_GENERAL    axlLayerPriority API changes layer visibility and colors
. v: b) B" E' m7 q" h/ L0 g* r1775071 ALLEGRO_EDITOR     UI_GENERAL    In release 17.2-2016, dialog boxes are not displayed in the right order on using SKILL
/ m  G4 Y6 h  {/ }' T  t! H1708554 APD                GRAPHICS      MCM shape lines are almost short and different with DXF and Gerber files4 Y# o2 T3 H2 w% I  g$ @
1678824 APD                SHAPE         Updating dynamic shape fails to void all elements on layer L2.
+ u  u/ x6 D3 |: {2 G( v+ Q1742335 ASDA               COMPONENT_BRO Libraries missing from new Component Browser
) A# h: f+ A5 Y1779777 ASDA               CONNECTIVITY_ SDA: Net name and physical net name are different; _+ P. j) k  S/ G( c
1721919 ASDA               CROSSPROBE    Cross-probing a net from the .brd file highlights the entire bus in the schematic
4 j  X* g/ }8 @5 o* T, A1714313 ASDA               EDIT_OPERATIO Filter does not work correctly in the Change RefDes form4 o$ O0 ]/ f6 d8 v
1730809 ASDA               FORMAT_OBJECT Image transparency slider does not update the number in the combo box correctly, h: K0 v! m2 S9 v
1747397 ASDA               GRAPHICS      Pop-up DRC descriptions are too small and cannot be read0 {  H5 T$ L* z- N5 ^! {6 b+ r/ v( i
1640061 ASDA               HIERARCHY     Incorrect message received when invalid characters are specified for subdesign suffix, X0 d# v0 e2 O$ G
1723535 ASDA               MISCELLANEOUS Clicking in the Command window should place the cursor at the last line to avoid editing previously run commands$ \( _2 d/ @' s' w* K5 @( f
1699936 ASDA               PAGE_MANAGEME Page gaps created while moving pages. c, |7 {+ w: K$ V) k
1737180 ASDA               VARIANT_MANAG Deleted variants are removed from the variant.lst file but displayed in SDA* d$ h" {+ V' Y3 e" l
1763247 ASDA               VARIANT_MANAG Changes in Variant Editor are not reflected on the schematic page.  K9 }: y5 I3 \* v
1733971 CAPTURE            CONNECTIVITY  Auto connect to bus not working in the attached design/ V# t8 O. E# O% e3 K6 \$ l/ _
1236010 CAPTURE            DATABASE      Capture is very slow in processing designs.
7 z& |. n+ }0 p" F) Y1518560 CAPTURE            DATABASE      Large schematics are slow to respond
+ v* _; m2 i8 n- {2 `: A1705592 CAPTURE            DATABASE      Capture hangs when switching between schematics that contain nested netgroups
$ o/ w) w; l: f/ i7 u0 w1770687 CAPTURE            GENERAL       In release 17.2-2016 Hotfix 021 and 022, selecting Help - Learning PSpice throws Java Script error
: z+ y; v. F0 J+ M! p  W1692435 CAPTURE            HELP          Version Info Window is empty
/ I7 m1 }; @/ _5 P1767374 CAPTURE            NETLIST_ALLEG Capture crashes on canceling the netlisting process
+ ]9 q# f) ~# {% |4 B. C) ~# w; e& d1719613 CAPTURE            OTHER         Moving a wire in OrCAD Capture CIS or Allegro Design Entry CIS results in design crash5 B7 N* \' n) C+ o
1746663 CAPTURE            OTHER         Capture slows down significantly in release 17.2-2016 Hotfix 017 and 018% _/ }( L1 G( E. ^4 G
1709179 CAPTURE            PROPERTY_EDIT Unable to delete unwanted properties associated with Ground and VCC nets.
+ c7 H0 b" S% [1714121 CAPTURE            SCHEMATIC_EDI Mirroring and moving a symbol resets the position of a newly added pin property
# F7 [0 J2 {1 ~  I+ M; M2 y$ G1729861 CIS                OTHER         The 'Refresh Part Types' icon is alternated with 'Refresh Symbols From Libs' icon8 y# g+ \) [$ i' d
1333600 CONCEPT_HDL        COMP_BROWSER  Sort the sections numerically in Part Information Manager
4 u6 j: J/ G) i1758761 CONCEPT_HDL        COMP_BROWSER  Incorrect Version showing in Component Browser in 17.2" K0 j6 y& V% l/ s, b. ~7 f' h
1769591 CONCEPT_HDL        COMP_BROWSER  Modify Component / Project Information Manager (PIM), parts take longer to load in EDM
( x7 o  k* F6 u! t# D4 _& i5 U1479711 CONCEPT_HDL        CORE          Mirroring symbols causes alignment issues
. |0 p  k. P: K2 L1696208 CONCEPT_HDL        CORE          Display issue with the grid visibility after a save hierarchy+ e6 S$ h4 K5 L/ Y0 T: J
1698802 CONCEPT_HDL        CORE          Pin number overlap with the pin stub when the component is mirrored.
( W# o: c+ C- g& G1708917 CONCEPT_HDL        CORE          nconcepthdl crashes on a design with a core dump' q" u6 f( N$ z1 J4 a3 D
1744815 CONCEPT_HDL        CORE          Deleting a page crashes DE-HDL# y6 ^7 ^: L* n  V0 U  v
1751863 CONCEPT_HDL        CORE          'Move' does not move body but only properties of selected part
, x" P6 ]) e% k  E( P1763556 CONCEPT_HDL        CORE          Component Alignment and other graphical feature not working in Windows 10* m9 S+ }$ v' q6 b
1725121 CONSTRAINT_MGR     CONCEPT_HDL   Audit report of ECSets reflects some gaps in certain columns4 A1 g- p4 W4 s+ G" e
1758740 CONSTRAINT_MGR     CONCEPT_HDL   Extracted topology does not populate the gather control used in the ECSet( T4 y0 F  Z5 X
1759580 CONSTRAINT_MGR     CONCEPT_HDL   Class to Class assignments are incorrectly displayed in the 'CSet Assignment Matrix'
' m* L6 A3 u- P3 T1759590 CONSTRAINT_MGR     CONCEPT_HDL   Unable to create bookmarks in Constraint Manager
) H1 m9 B1 I( j: n* S- l8 [  c, n1764597 CONSTRAINT_MGR     CONCEPT_HDL   Copying constraints from a SKILL-defined CSet copies the automation flag/attribute ('A' in UI), as well.* U4 I, D6 X% S7 Q
1771427 CONSTRAINT_MGR     CONCEPT_HDL   Decimal units specified in the precision settings are not applied correctly
- M$ a6 ]+ [# F5 {1700402 CONSTRAINT_MGR     DATABASE      Parallelism violation DRC not reported until cline is moved
, {& ~, x7 |3 Y  X4 y9 h1700370 CONSTRAINT_MGR     OTHER         Constraint Manager: Expanded nodes collapse on restart
( @$ U& F& j+ \6 m( {9 k- a1735636 CONSTRAINT_MGR     OTHER         Inductors are extracted as resistors in the topology
$ b7 N. w5 V+ P. B4 n1776917 CONSTRAINT_MGR     OTHER         Creating advanced formula causes the tool to crash0 x# X# b" I9 L7 g: {: E* n; J3 e
1762979 CONSTRAINT_MGR     TECHFILE      Constraint Manager does not retain values after importing tech file
! N0 p/ k! J8 b# Y5 i8 q, V1699275 CONSTRAINT_MGR     UI_FORMS      Constraint Manager: Dialog boxes opened from the File – Import menu show files and folders in incorrect order
5 e* [3 T& k% {' [  _/ J' b1699312 CONSTRAINT_MGR     UI_FORMS      Typing *.* in the File name field does not display all the files in the Import Constraints dialog box4 F8 Y+ k+ m( ]4 l# s
1742134 CONSTRAINT_MGR     UI_FORMS      Editing a cell from any of the constraint set in Constraint manager is filling other cells that should not be selected1 Q, g% _3 o7 B" c( J
1755576 CONSTRAINT_MGR     UI_FORMS      Constraint Manager: Physical CSet filter not working correctly
2 C4 O; s" q" M. o+ ~" o1775333 ECW                DASHBOARD     Activity Log is not accessible to ECAD_Integrators if they are not part of the project team5 }( c" A+ O3 k+ b# l
1749220 ECW                OTHER         Remove 'Role' column from Users web parts* V  u$ Y% a- p2 u- ?/ t% U
1716527 ECW                TDO-SHAREPOIN Allegro Pulse: Mismatch between metrics with components on schematic and components in layout
1 T. m3 {: r: k: u# C' m* \1724195 FSP                SYMBOL_EDITOR Device pins are not correctly aligned after being moved in Schematic Symbol Editor( P0 L* E3 @- u% i  [7 ^2 m. F
1725479 INSTALLATION       DOWNLOAD_MGR  Download Manager error prompts user to close downloadmanager.exe
1 y+ @" l  j2 c2 ?7 |. B! x1738952 PCB_LIBRARIAN      SYMBOL_EDITOR Pin table must allow for Copy/Paste of Rows0 _% j& {0 ^: O; |8 s! h
1638740 PSPICE             FRONTENDPLUGI Set minimum height for the search field in PSpice Part Search; M) _" {; u" u- d
1699822 PSPICE             FRONTENDPLUGI Set minimum height for the search field in PSpice Part Search
! g0 B- C4 {% p3 O3 J$ m* `" m1652265 PSPICE             MODELING_APPS Cannot place PWL source from PSpice Modeling App
3 s4 c9 g2 _% x& C- |# ]0 d( }1685967 PSPICE             MODELING_APPS Getting error when trying to place PWL source from PSpice Modeling App2 z, |$ K# u" r$ [
1716313 PSPICE             MODELING_APPS PSpice PWL Sources not working correctly in release 17.2-2016 Hotfix 014! z& ]" f0 G  a
1738747 PSPICE             MODELING_APPS Inconsistent file type for PWL part in modeling application and source library' t# c2 l( a) x( P* E
1762202 PSPICE             MODELING_APPS PSpice modelling app Tcl issues
3 R1 H8 Y4 z5 {: j# |1736605 PSPICE             SIMMODELS     BSIM4.6 model parameters incorrectly handled by simulator8 m! Y2 U$ S, K" }
1442623 PSPICE             SIMULATOR     Bias points are nor correct in attached circuit
( i! E8 L' o3 B' k1618815 PSPICE             SIMULATOR     Bias Point calculation appears incomplete4 f& u/ v1 q5 |8 z
1723039 PSPICE             SIMULATOR     PSpice crashes when curly braces are specified for the ETABLE parts
" l/ A. j2 v% a6 g6 S! m1782353 SIG_INTEGRITY      SIGWAVE       SigWave crashes when opening .sww file in release 17.2-2016 Hotfix 023
5 R2 n0 k: k1 V1745940 SIP_LAYOUT         DATABASE      Cutting a part of a tapered cline does not remove the connectivity on the dangling cline
4 x" y" j' S7 V  I2 G1780072 SIP_LAYOUT         DIE_ABSTRACT_ Export->Die Abstract File causes a crash3 d8 H7 N% [/ i3 P8 ]
1736396 SIP_LAYOUT         SYMB_EDIT_APP 'No such child' error message when deleting pins in symed( i& u+ ^# Q* t0 `6 B4 }/ ~
1769728 TDA                CORE          Default policy file needs to be fixed0 J, q, J8 E4 D+ R$ g
1735682 XTRACTIM           GUI           XtractIM translation is incorrect: adds anti-pads
/ T, k6 U2 ~+ I0 o" o( Z/ R! O
' s: S) B3 b8 S
( S' s) H+ n3 J! ^4 M2 f9 wFixed CCRs: SPB 17.2 HF024
0 ~3 B3 q, q/ x3 P$ b+ s# P07-28-20174 S' V5 I/ k- ~5 m* F( [
========================================================================================================================================================
- ?0 @+ Y0 S1 n7 T/ B: G) x& _CCRID   Product            ProductLevel2 Title
+ }1 \$ E, o7 w, _4 c: i========================================================================================================================================================! C6 x" N. \( e/ p, K
1762143 ADW                COMPONENT_BRO Part placed using the 'Add' button does not populate 'PART_NAME' property' W+ X. r( z- O' N; P2 R. O
1765790 ADW                PART_BROWSER  Fail to extract component part number and footprint information. n! j7 G4 a4 C9 H% I1 v
1757719 ADW                TDA           TDO and Windchilll Work Group Manager out of sync at times) I# u2 x6 r/ ~# \
1760607 ALLEGRO_EDITOR     DATABASE      Value for number of decimal places changes in Pad Designer in release 17.2-2016$ @5 |5 Q) T) T, S; p# z" R# H
1775160 ALLEGRO_EDITOR     DFA           Loading DFA spreadsheet crashes PCB Editor in release 17.2-2016- ?/ {* G4 ?8 @  h' d; q
1765984 ALLEGRO_EDITOR     OTHER         Cannot view System Info
' h2 U% P! m6 E' Q8 N( h1 O1729350 ALLEGRO_EDITOR     REPORTS       Net loop is not listed in report
7 t2 f3 y0 A/ g: m0 @" X1 {+ \% G1725242 ALLEGRO_EDITOR     SHAPE         'Same net shape to hole spacing' is only detecting the DRC and not voiding the shape
* E* |* Y/ J% h  R# Y5 M5 ~' H1754402 ALLEGRO_EDITOR     SHAPE         Illegal arc radius error (SPMHA1-85)
9 V6 k0 `# Q* d2 w5 a" d$ B1 F1762888 ALLEGRO_EDITOR     SHAPE         Border line missing for some crosshatch (xhatch) shape voids! e8 S' Q4 p, D1 F- W
1769188 ALLEGRO_EDITOR     SHOW_ELEM     'Show Element' with the 'Groups' option used on certain modules crashes PCB Editor
9 J3 B! J% H! B0 a9 I, I& f; z1767690 ALLEGRO_EDITOR     TESTPREP      PCB Editor crashes when running automatic Testprep7 v4 T1 Z% ^" u0 ~9 |& b' q( B* S
1737337 ALLEGRO_EDITOR     UI_FORMS      Pinned Show Element window closes when opening new design in release 17.2-2016
5 X9 p$ ]9 ~" M: N: e1736642 ALLEGRO_PROD_TOOLB INTEGRATION   Cannot change accuracy to 4 for 'Change Width' in Productivity Toolbox: z* \( q( a$ G; K- |
1685216 ALTM_TRANSLATOR    CAPTURE       Third-party translator placing symbols off grid( U* D( n& c) U. ~4 U
1738679 ALTM_TRANSLATOR    CAPTURE       Connectivity loss in imported schematic
) k0 q3 Y6 y( W" s8 ]+ P5 m; ]# N( W1738705 ALTM_TRANSLATOR    CAPTURE       Connectivity loss in imported schematic6 U1 R- f7 C. M& B+ D% n0 r
1748583 ALTM_TRANSLATOR    CAPTURE       Crash on importing design using third-party translator2 j! d* r1 d4 i. I/ g) ?* ]
1679310 ALTM_TRANSLATOR    PCB_EDITOR    Third-party translator should fix off-centered connections/ K) |7 _+ G1 P# i6 r
1686845 ALTM_TRANSLATOR    PCB_EDITOR    Third-party translator does not place parts after successful translation7 A( V& v$ m7 N4 ~0 @
1723141 ALTM_TRANSLATOR    PCB_EDITOR    Placement outlines are rotated in third-party translator
9 d& Z2 }+ Z- j. ?6 z7 w1723164 ALTM_TRANSLATOR    PCB_EDITOR    Third-party translator creates board with missing data: vias, traces, and so on4 g: V& Z) J$ n8 U2 N: _
1723190 ALTM_TRANSLATOR    PCB_EDITOR    Third-party translator changes design origin! u$ S5 l/ c& J' Q5 K6 J* r. Y7 X
1750496 ALTM_TRANSLATOR    PCB_EDITOR    Third-party board with arc tracks not correctly converted to arc clines
. t# s1 Z% Q7 h5 a9 q1769624 APD                DATABASE      Attempted symbol delete crashes APD
0 j$ V1 n1 O( O1727206 APD                SHAPE         Merging two shapes results in an incorrect shape2 q, B$ r1 \. h6 ]; k; Q2 U" D# W
1707756 ASDA               VARIANT_MANAG Scrolling in Create Variant closes tool
8 I* o8 c' ~7 s; b1753699 CM                 RELEASE       installDebugger() does not work in release 17.2-2016 as SKILL kit is not installed: ]# k0 |. u8 z7 F& ~) c1 t
1741534 CONCEPT_HDL        CORE          DE-HDL freezes when selecting a net that contains many connections" f7 _# N9 d6 U/ v- F$ ^
1752687 CONCEPT_HDL        CORE          The move command changes the connectivity of the schematic# F3 F+ d/ [/ C+ h$ X
1763525 CONCEPT_HDL        CORE          Genview crashes when generating split symbols
+ X" F1 J7 P. C8 S7 w- K1766797 CONCEPT_HDL        CORE          Schematic not refreshed after using the clear xnet overrides feature, V' {' _+ F7 h5 C: H
1770852 F2B                PACKAGERXL    ERROR(SPCOPK-1138): A hard location was found on instances of different physical part types
  n# K, O3 k' v1 [) L0 N1754473 FSP                DE-HDL_SCHEMA Provide an option to generate symbols with custom attributes  u, E) |/ K& o% c: z% R
1748106 FSP                OTHER         Create protocol from existing protocol error message needs clarity
* q( N, u8 P* s$ o) o1 y  ~1724201 FSP                SYMBOL_EDITOR Unable to change 'Pin Direction' in symbol editor
  {2 c; S% U, I; s$ `" e1772429 ORBITIO            ALLEGRO_SIP_I Import - OrbitIO: Translator cannot create bundle in PCB Editor2 s5 a/ M0 n, J5 o9 ^
1725759 SIG_INTEGRITY      OTHER         PCB shape/plane capacitance4 R( \. _+ E0 c
1760924 SIP_LAYOUT         DIE_STACK_EDI Package height of die .dra file reset to 110um when placed) Q: S7 _3 E! S: r
1764385 SIP_LAYOUT         MODULES       Embedded components are unplaced in created modules (.mdd)
5 R  |2 I9 h" H7 L1733679 SIP_LAYOUT         OTHER         'metal density scan' does not use select window& j+ F2 c# E! b3 d4 }5 r
1763707 SIP_LAYOUT         OTHER         SiP Layout exits with error message in release 17.2-2016
' w" W) ~) b; W1763515 SIP_RF             DIEEXPORT     Virtuoso writes incorrect width for 45 degree path segments in XDA file5 n8 ]9 M- I4 @& l
1772397 TDA                DEHDL         DE-HDL crashes if license is not available for team design7 m$ X) L+ E* O0 H% L4 o/ i- {

$ [1 E: I. t- @6 x0 V" n
7 r& g! j/ O5 H# hFixed CCRs: SPB 17.2 HF023
1 b) d3 w- u2 D07-7-20173 p1 W$ [1 c/ g2 _  |
========================================================================================================================================================4 O$ q2 ]8 `- j8 b% H
CCRID   Product            ProductLevel2 Title' ?4 b4 H+ g, [
========================================================================================================================================================
- }, I9 U; D, X$ V1703281 ADW                ADW_UPREV     Design_init needs to support the -cb command
  c$ }3 I! h$ i! O! t/ w( x8 _+ z( S1762238 ADW                COMPONENT_BRO DEHDL crashes without reason
* m% {) l: t+ x# P1759467 ADW                DBEDITOR      DBEditor does not recognize that 1.10 is a higher version than 1.93 T& c; H) t$ r$ I2 ^, A9 z( c
1731459 ADW                FLOW_MGR      Cannot open LRM from Flow Manager9 @- L( N+ W0 R& I
1731460 ADW                FLOW_MGR      Cannot open LRM from Flow Manager" i8 {4 n( C: s  I5 A8 Y
1757443 ADW                LIBDISTRIBUTI Blank PHYS_DES_PREFIX in PTF file
- E, ?' ~4 j2 |( u; x$ F  Q1752126 ADW                LRM           cache not getting updated with std models when moving from 16.6 to 17.2
, d" i7 e. J+ e0 n1 v4 f$ H/ f, f$ L1754444 ADW                LRM           Update Standard library in LRM causes an error, "Cannot proceed with update as don't have permission to delete."
3 R% b" F- |2 I& }1715861 ADW                SRM           symbolrevchk.par has incorrect variable name for SRM to ignore the tool version
# t- C( ]: @0 s8 s4 I/ N1628403 ADW                TDO-SHAREPOIN Objects remain checked-out after multiple failed 'check in hierarchy' attempts
6 I! v& j, r2 X2 M( b1759250 ALLEGRO_EDITOR     DATABASE      Flex-rigid placement does not move bottom pads to nearest layer6 P! j9 C7 y1 n, A- i  K6 i
1762782 ALLEGRO_EDITOR     DATABASE      PCB Editor crashes when creating artwork
9 z" D7 V7 V. ]. m& h1746665 ALLEGRO_EDITOR     DFA           Cannot scroll in DFA Constraints Dialog if the DFA constraint file is read only
0 G& W' a! g: t9 _! W6 t1750084 ALLEGRO_EDITOR     DFA           DFA spreadsheet disappears from the DFA library if hyphen is present in the name
) U1 w- w5 L) T4 I  N0 L' S+ j1697155 ALLEGRO_EDITOR     GRAPHICS      Position and size of Show Element and Measurement windows not saved in PCB Editor
$ G! W' x! [7 F3 T1 X1734282 ALLEGRO_EDITOR     GRAPHICS      Placement of reports and pop-ups not retained in PCB Editor
' X; C7 z0 b5 T! F4 q" ?/ a1740863 ALLEGRO_EDITOR     GRAPHICS      Show Element and Measure windows do not retain position$ E) j' ]9 ?+ j4 a1 {# V( h( {9 _9 \
1749687 ALLEGRO_EDITOR     GRAPHICS      Position and size of Show Element and Measure windows are not saved in PCB Editor in release 17.2-2016$ X: A; {) [( L& G+ x; w
1764124 ALLEGRO_EDITOR     SCRIPTS       Replaying recorded script file crashes PCB Editor5 z; X4 g# o- e1 S! s
1762888 ALLEGRO_EDITOR     SHAPE         Border line missing for some crosshatch (xhatch) shape voids4 `. C8 ]. Q" s; P7 [: y
1763619 ALLEGRO_EDITOR     SKILL         Incorrect text block name when extracting text parameters using SKILL6 s% _  d, `* S9 ]
1685826 ALLEGRO_EDITOR     UI_GENERAL    Reports when opened from Status Form disappear behind PCB Editor canvas when clicking on canvas
* w6 l% w5 B* L. |& a5 {1733552 ALLEGRO_EDITOR     UI_GENERAL    Although F1 is defined as an alias for another command, pressing F1 opens help
, i7 V, q0 H3 s1 e% i2 d1735098 ALLEGRO_EDITOR     UI_GENERAL    axlUIYesNo displays garbled text when customized for Chinese in release 17.2-2016
1 i/ `( a5 X8 V1753430 ALLEGRO_EDITOR     UI_GENERAL    'Tools - Quick Reports' opens only one report at a time! `$ i: a4 @" L6 U7 O5 g( P
1754283 ALLEGRO_EDITOR     UI_GENERAL    Call multiple reports from a function key
. s( j" ]0 C+ h2 _( ~1 z5 E4 E. Q1742822 APD                STREAM_IF     Component pins are not mirrored properly when mirror geometry option is checked and component is mirrored at 90/270, i' S2 d0 y  L! e; H% a
1762284 ASDA               COPY_PASTE    Copying testpoint crashes tool and eventually the operating system
: x( V/ a/ J+ y. X1655057 CONCEPT_HDL        COMP_BROWSER  ADW Part Manager and Component Modify hangs- M, s8 V2 X  P9 h/ P) l& I6 g
1689740 CONCEPT_HDL        COMP_BROWSER  Bad response time using Dehdl component browser
" A& l8 d6 t) [" o2 a) G+ l( x1735332 CONCEPT_HDL        COMP_BROWSER  Sort in mathematical order Symbol list in Component Browser, Y' Z- Y; p4 l
1739197 CONCEPT_HDL        COMP_BROWSER  Part Information Manager can`t sorted symbol version
6 I1 W* |. o) K: G" y% X. V1764605 CONCEPT_HDL        CORE          Signal added from the console should be 'Left Aligned' instead of 'Center Aligned'
6 a4 n. Q; B+ H5 X1761706 CONSTRAINT_MGR     CONCEPT_HDL   cmDiffUtility has a typo in the usage statement
  I8 V3 [( l! {+ t  W1758426 ECW                DASHBOARD     Behavior of 'Apply Label' for Dynamic and Status labels should be same in TDO and DE Webpart) T, H3 Q; |9 O( s& G7 j) N: V8 @
1764096 ECW                PROJECT_MANAG Renaming project using the ETD window randomly hangs the edit window, refreshing bring backs the page, p& m: Y+ j, j7 @7 ]. `
1764070 ECW                TDO-SHAREPOIN Join Project: Multiple entries shown for workspace/project with multi-hierarchical structure
$ |: G  V& Q0 j6 S/ I& E9 T1754473 FSP                DE-HDL_SCHEMA Provide an option to generate symbols with custom attributes
6 R) @6 Y) Q2 q  g7 S, ]# Q7 @1724124 FSP                DESIGN_EXPLOR Provide Tcl command to filter data in Design Connectivity Window
$ o9 T/ l! L- a( u& C% |1726548 FSP                OTHER         Unable to open FPGA system planner if username/log file path has Cyrillic letters: H* q" |% r7 [2 z
1719133 SCM                SCHGEN        Voltage symbol not getting placed for some of the voltage nets- S$ Z* c1 o  Z, k9 ^
1680989 SIP_LAYOUT         ARTWORK       Artwork film set-up: Match Display including invisible layer
7 B2 U% x8 i! o9 l$ t9 `3 @1732218 SIP_LAYOUT         DEGASSING     Shape will not degas as needed - not all voids degassed' X& @0 h" l/ Z1 f8 N- p) M/ y, E
1763280 SIP_LAYOUT         DIE_ABSTRACT_ SiP Layout does not recognize width of segment when importing .xda
" l1 Z& V. Y+ T! M1762992 SIP_LAYOUT         OTHER         Saving a design after adding a solder mask layer in the cross-section crashes tool
8 b2 K7 F! M7 _. d4 |; \1 Z4 `7 b8 L) G$ B
( f! n( j( g' r% ~" W" \
Fixed CCRs: SPB 17.2 HF022
" C( v' r  a- O) S$ u+ i% {06-16-2017
. K2 Y( k% D0 R1 v- n========================================================================================================================================================. J+ z4 y% a3 z' U. I
CCRID   Product            ProductLevel2 Title& N' _7 S4 N4 D  S4 {. i' I
========================================================================================================================================================
9 e. e3 B/ L' V; e0 q1 ^: h1755789 ADW                DBEDITOR      Checking in HSS Block returns 'Failed to create archive'
  q6 K$ F2 J! C: |1731459 ADW                FLOW_MGR      Cannot open LRM from Flow Manager
; \: ?. }: _- b1 g1731460 ADW                FLOW_MGR      Cannot open LRM from Flow Manager+ f3 K& e& ^$ c1 R/ Y. d4 H
1744081 ADW                FLOW_MGR      Error regarding configuration file when trying to open Workflow Manager
" D. ^4 A2 C; v1 S; H2 `1756727 ADW                LIBIMPORT     EDM Library Import fails with java exceptions when merging classifications" i/ j4 x: m" Z  i( j8 ]% N0 |: d
1743763 ADW                SRM           Find filter is grayed out when Allegro PCB Editor is opened from EDM Flow Manager' f/ c: [; }: Y+ X$ ]. i
1748399 ALLEGRO_EDITOR     DATABASE      In release 17.2-2016, end caps not visible for certain clines in PCB Editor
) p7 o( K: Q, l. G$ R* D3 V1748522 ALLEGRO_EDITOR     INTERACTIV    A component mirrored using the 'funckey' command jumps to (0,0) position when the 'move' command is used on it
$ c& m- B2 P$ U9 }) P6 L6 j& h1734983 ALLEGRO_EDITOR     INTERFACES    Secondary step model does not stay mapped after drawing is reopened+ x+ m0 }- y+ N) G7 b7 @  N
1753704 ALLEGRO_EDITOR     REFRESH       Refreshing symbols crashes PCB Editor
4 \8 a, L1 h' p1493721 ALLEGRO_EDITOR     SHAPE         Voids on negative planes are not adhering to constraints
5 f8 E0 i: q) i! w1 e# w( u. N: E1711242 ALLEGRO_EDITOR     SHAPE         Route keep out leads to partly unfilled shapes with gaps0 M# V* W* }4 d8 ?
1726865 ALLEGRO_EDITOR     UI_GENERAL    Pop-up Mirror command does not mirror at cursor position7 D9 Z9 s9 c: Q' w& G% R
1752987 ALLEGRO_EDITOR     UI_GENERAL    axlUIViewFileCreate zoom to xy location not working while in user created form.
+ q/ F- d; O$ c  N: X1755638 ALLEGRO_EDITOR     UI_GENERAL    In release 17.2-2016, zoom operations using mouse button not working when axlShellPost() is run4 w6 ]. q' ^- d: J
1719792 ALLEGRO_PROD_TOOLB CORE          Productivity Toolbox Z-DRC hangs or crashes PCB Editor" w3 N/ ]" S2 m0 T: D
1624869 ALTM_TRANSLATOR    CAPTURE       A structure file is required to translate a third-party schematic to OrCAD Capture/ m+ v% b8 P! h& W7 a0 Q/ ?+ T
1707416 ALTM_TRANSLATOR    CAPTURE       Missing components and pins in the OrCAD Capture schematic translated from a third-party tool$ T1 O0 J% U. L. u: ?0 \2 V: }
1708825 ALTM_TRANSLATOR    CAPTURE       The third-party translator fails to translate the schematic
1 L3 h3 R# z$ m1 i1719200 ALTM_TRANSLATOR    CAPTURE       The third-party translator fails to translate all the pages of a schematic7 R& p$ k6 M3 w* _7 v
1546070 ALTM_TRANSLATOR    CORE          Third-party to DE-HDL schematic translation fails3 c9 H. g2 h. r" F# J* D
1700508 ALTM_TRANSLATOR    CORE          Third-party PCB translator does not work in release 17.2-2016
) f! G9 m) l" L  `1699340 ALTM_TRANSLATOR    DE_HDL        Unable to import third-party schematic into DE-HDL using Import menu in PCB Editor
1 O% [5 \* M4 L( R) }1630379 ALTM_TRANSLATOR    PCB_EDITOR    Third-party translator is not importing clines and vias% }7 u) S0 U. q: P7 t
1708615 ALTM_TRANSLATOR    PCB_EDITOR    All items of third-party PCB not imported in release 17.2-2016
5 K$ g. t; i% G9 a3 u' n8 F& U1758296 APD                DXF_IF        DXF OUT: Rounded rectangle pads mirrored incorrectly
; r, C* d  |, _; X& w1 G1 X5 D( i& m5 h1756040 APD                IMPORT_DATA   The 'die text in' command ignores values after the decimal point
: a# O0 V7 ]3 ^1 D# U2 ^1727206 APD                SHAPE         Merging two shapes results in an incorrect shape
& t6 T4 `5 L9 r$ Y- }+ r: v( r- w/ r1753682 CONCEPT_HDL        CONSTRAINT_MG Constraint Manager stops responding while cross probing DE-HDL8 j5 f4 z: ~0 N! p4 x3 c9 x
1721334 CONCEPT_HDL        CORE          dsreportgen not able to resolve gated part on schematic' V% \  ]( n$ \0 s- [. C
1747559 CONCEPT_HDL        CORE          Copying a logic symbol without a part table entry results in ERROR(SPCODD-53)3 d: l7 W) z/ f: r, c
1749644 CONCEPT_HDL        CORE          In release 17.2-2016 Hotfix 019, 'align components' is not working on Windows 8 and DE-HDL crashes. {% T8 ?2 D; z* \
1746910 CONCEPT_HDL        GLOBALCHANGE  Global Component Change unable to identify part data when using schematic pick option9 p7 s2 ^/ F! [3 n, _
1743572 FLOWS              PROJMGR       Project Manager displays incorrect values in Project Setting
) D6 o. T  |+ n5 {1724124 FSP                DESIGN_EXPLOR Provide TCL command to filter design connectivity window
  S+ k4 k; f6 {1719105 FSP                GUI           Tabular sorting not working in FPGA System Planner
* n0 F+ Z+ v  C+ D1755750 PCB_LIBRARIAN      GRAPHICAL_EDI In release 17.2-2016, unable to delete _N pins in PDV Symbol Editor4 e  R8 l1 ?1 y8 C) |: P
1722993 PCB_LIBRARIAN      IMPORT_CSV    Part Developer crashes while importing part information stored in a .csv file
4 g9 `7 ?6 m" z1758856 SIP_LAYOUT         3D_VIEWER     Correct the spelling error in the 3D Viewer Design Configuration window
! G' J# i. b9 v5 M1755179 SIP_LAYOUT         ARTWORK       PCB Editor crashes when creating Gerber files; b1 U8 m, L5 ]( W8 b, y. E
1743511 SIP_LAYOUT         MANUFACTURING Package Design Integrity shows non-redundant padstacks in the Redundant Padstacks check
! e" y% \- Z+ m% o" F7 D! I6 U7 W) [: H4 ]5 ]( @& Q

1 Z2 ~, L0 }$ t& x, ?Fixed CCRs: SPB 17.2 HF0216 C1 ~9 `; M) |0 e& p( j
06-3-2017
" {4 [# [8 J" b0 z+ N: G  [7 i========================================================================================================================================================
6 _7 f- I; u  l$ @- hCCRID   Product            ProductLevel2 Title
4 |: i8 q( ]0 H3 y( G========================================================================================================================================================
1 L  G- y: _. d; [7 Z3 s1401318 ADW                DBEDITOR      Bulk Edit - Previously modified cells do not turn blue when selected( x. z! s/ v, \) @& {& s
1621446 ADW                DBEDITOR      Bulk Edit - sorting highlights incorrect cells to mark them as changed. u$ M+ |5 R6 e) {
1743997 ADW                LIB_FLOW      Match file for standard models is incorrect
. R$ y8 ]6 D/ ^- I# y: _1746052 ALLEGRO_EDITOR     DATABASE      PCB Editor crashes when applying no drc property
/ |' ~- }% X6 s1736067 ALLEGRO_EDITOR     DRC_CONSTR    Interlayer checks not reporting DRCs between cline and mask layer' E7 T% _9 g) E4 M$ i. k0 Y. }
1738587 ALLEGRO_EDITOR     EDIT_ETCH     Line width changing on slide for ETCH - Conductor (Not on a NET)8 J8 R0 c5 N6 u) W  e3 |$ {0 [/ x. t
1745277 ALLEGRO_EDITOR     EDIT_ETCH     PCB Editor crashes on using the slide command
, G! p6 B' S/ {% J/ [: _' }1747942 ALLEGRO_EDITOR     EXTRACT       Fabmaster Out does not export arc in pad_shape
/ }& z% h/ s5 a0 E0 z7 P$ O1737202 ALLEGRO_EDITOR     GRAPHICS      Setting the variable display_raster_ops' e% @0 a# D" w) D* r, j0 H! q
1744042 ALLEGRO_EDITOR     GRAPHICS      Unused pad suppression is not working on few nets
8 y; `0 Q+ M' ]( E; K9 B5 |1703848 ALLEGRO_EDITOR     INTERFACES    IPC 2581 fails with error 'E- (SPMHGE-268)' and the log file is empty* i; v% d4 q+ z$ h
1743899 ALLEGRO_EDITOR     MANUFACT      Glossing dangling vias crashes PCB Editor
- H. m+ B4 w% O4 u9 k, C1744467 ALLEGRO_EDITOR     OTHER         The 'logical_op_new' variable is not displayed in User Preferences Editor% N3 j, U: n% Z' I4 m; `* u
1748520 ALLEGRO_EDITOR     OTHER         TDP fails to load on an empty database! T) f* z! C- g" a
1748581 ALLEGRO_EDITOR     PAD_EDITOR    Padstack Editor crashes when changing default pad geometry
+ i: |" U: q! Z: y1751469 ALLEGRO_EDITOR     PAD_EDITOR    Padstack Editor crashes/freezes when browsing for a shape symbol
5 N  m1 B3 Y3 s5 s# w: A; x! Z1725948 ALLEGRO_EDITOR     SHAPE         Shape differences after conversion from release 16.6 to release 17.2-20160 ?7 t+ s  E6 ]! u1 I* r
1729306 ALLEGRO_EDITOR     SHAPE         Seting shape_rki_autoclip variable causes no void to be generated* s2 c4 g$ d4 L# k
1698876 ALLEGRO_EDITOR     UI_GENERAL    Tabs are large and text is compressed in release 17.2-2016& ~) n: W# T) B( w
1698883 ALLEGRO_EDITOR     UI_GENERAL    In release 17.2-2016, enlarging icons makes selection boxes/text unreadable on 4K monitors6 R- k! J0 `( u/ {$ K
1707933 ALLEGRO_EDITOR     UI_GENERAL    axlUIMenuFind not locating menu as per x_location
- t- x! o  n& d* m& s1741460 ALLEGRO_EDITOR     UI_GENERAL    Right-click, context menu options grayed in some cases after choosing Edit - Copy. O) a* c0 ~0 q0 i
1747588 ALLEGRO_EDITOR     UI_GENERAL    Interacting with PCB Editor by sending messages is not working- p: H5 x" a' v' J
1747488 APD                EDIT_ETCH     Route connect is improperly affecting existing routes in locked high speed via structures
. [0 N- F; W6 k. L; m: F3 v- {1750182 APD                STREAM_IF     The stream out settings are not saved: K) ~1 k- x! ~; R8 r
1752067 ASI_SI             GUI           Links to differential waveforms do not work in Sigrity SI report+ K8 P) @# q  K3 y$ @& w
1752131 CONCEPT_HDL        COMP_BROWSER  Symbol view in part manager doesn't match the symbol version
9 ^4 T; N6 O2 Y$ K1754116 CONCEPT_HDL        COMP_BROWSER  Default Symbol selected is n°2 instead of n°1 in component Browser
( ~8 C1 e3 ]. X' ^# B. p1754949 CONCEPT_HDL        COMP_BROWSER  Part Information Manager displays preview window with the wrong symbol and missing footprint& W! T" b  L4 X2 f4 }
1721334 CONCEPT_HDL        CORE          dsreportgen not able to resolve gated part on schematic
: I6 e  E# j2 \& d0 C1750916 CONCEPT_HDL        CORE          DE-HDL crashes when trying to uprev a project in release 17.2-2016( g9 ^# E5 z0 H. Y
1711487 CONCEPT_HDL        INFRA         Restrict opening of release 16.6 designs from a release 17.2-2016 design using File - View Design7 Q0 _  u& n, w  ]+ _
1746915 CONSTRAINT_MGR     CONCEPT_HDL   Unable to copy a Physical and Spacing CSet generated from the Constraint Automation flow5 K$ E( e6 S* U  @7 x6 f5 Y
1743523 CONSTRAINT_MGR     DATABASE      Suppress warning pop-ups from the constraint automation script
9 {% S! b; U# h9 ]* m1746941 CONSTRAINT_MGR     UI_FORMS      'Go to Source' from DRC tab is not working in release 17.2-2016
/ `; D4 f; J' [$ i! ^) m* r( J/ n1753010 ECW                METRICS       Metrics not getting collected due to old license in use
0 H$ }" i: p; N1 ]: o& E( F  Y9 P1713052 FSP                GUI           Pin/Port Name and Group Name are not aligned properly in FPGA Port and Use Pin Mapping for DeviceInstance
$ p/ x8 s) B$ u( {3 @+ Q3 @3 P1719099 FSP                GUI           Net naming wrong after building block
' `1 ]9 y3 j( g1 Q: @5 i; \4 u1719105 FSP                GUI           Tabular sorting not working in FPGA System Planner
  ?0 L- v& Q3 a5 L1 O1720479 PSPICE             ENVIRONMENT   Probe window does not open consistently on Windows 10 systems
9 M7 t, F, D6 ?) ^0 h5 A" k1723411 PSPICE             ENVIRONMENT   Probe window does not open consistently on Windows 10 systems
: u- Y# w; n! p. `  U) U0 z4 y) W1746628 PSPICE             ENVIRONMENT   PSpice Simulation Manager displays same message for all simulations in release 17.2-2016, Hotfix 016
. h5 z% _9 ^- B: a. t1745976 SIG_INTEGRITY      GEOMETRY_EXTR Arcs with coplanar waveguides are extracted with incorrect spacing) \3 I7 d" P2 k7 i! r
1690820 SIP_LAYOUT         PLATING_BAR   Cannot add fillets to pads with plating bars in release 17.2-2016
+ j3 K6 i' t: Y+ A1725042 SIP_LAYOUT         PLATING_BAR   Creating a plating bar removes dynamic fillets, D! Q  E+ j8 v$ {
1747534 SIP_LAYOUT         SHAPE         Moving fiducial crashes SiP Layout
. s: y9 d, z& e8 _5 I
* A2 q2 b9 b* r2 m
( S3 m; W, C( ^- [4 LFixed CCRs: SPB 17.2 HF020
& x, K9 e1 _; H% `9 j6 _( D2 C) H05-21-2017
+ N" j" m" k! q; T' n/ J# q========================================================================================================================================================
8 s1 y3 L& T8 e) b. ^2 v, cCCRID   Product            ProductLevel2 Title
5 N* N0 I6 E: s8 e' G# X6 M========================================================================================================================================================
8 C% `2 F% h7 \0 V' T$ n1737443 ADW                DBEDITOR      Revising the schematic model classification for one category causes all parts in the library to be revised8 @* ?' p, X1 _* B
1734123 ALLEGRO_EDITOR     3D_CANVAS     Interactive 3D canvas crashes Allegro PCB Designer in 17.2 S016
% }8 V. Z- j/ g/ L/ s1742084 ALLEGRO_EDITOR     DATABASE      Running DB Doctor on DRA files with custom pad shapes resets some of the custom padstack shapes in release 17.2# [4 {, H0 e. f6 k! k# o
1739397 ALLEGRO_EDITOR     INTERACTIV    In release 17.2, running the SKILL function axlImportXmlDBRecords causes Allegro PCB Editor to crash
7 i$ m: v* b$ t1724588 ALLEGRO_EDITOR     MANUFACT      Backdrill Route keepout suppressing existing Route Keepouts1 L( Z0 \. f" J' [- z6 K
1740036 ALLEGRO_EDITOR     MANUFACT      Generating the cross-section chart does not provide information about the overall board thickness) X4 n/ R0 O& S4 S
1743726 ALLEGRO_EDITOR     OTHER         IDF file export: In release 17.2, only one design outline is exported as against multiple board outlines in release 16.6
/ G' S) z1 j5 f: a% E4 j0 q% D1744467 ALLEGRO_EDITOR     OTHER         The 'logical_op_new' variable is not displayed in User Preferences Editor" [+ S- R4 t- s, [8 R7 _7 \3 A" i
1729350 ALLEGRO_EDITOR     REPORTS       Net loop report is not working.' @( z# s1 G- C1 |
1713014 ALLEGRO_EDITOR     SHAPE         Incorrect behavior of donut shaped pads at certain rotations2 g- P' j) @2 w1 E$ q+ X
1739870 ALLEGRO_EDITOR     SHAPE         The artwork is different from the PCB in release 17.2 Hotfix 17
1 e0 V* M, Y, |; S0 s5 e1698869 ALLEGRO_EDITOR     SKILL         PCB Editor crashes when trying to open another .brd file after running SRM on first .brd file
5 Z3 E5 y) E7 ^" U5 a: `. q" P: q1 S* \1739307 ALLEGRO_EDITOR     SKILL         axlCNSDFAExport fails after first run
$ G2 ?+ |7 Y5 W. m( w1743385 ALLEGRO_EDITOR     SKILL         SKILL APIs for STEP model mapping are not available in release 17.2 Hotfix 17 or 18
, q3 L0 z. q+ {0 Q: u1685826 ALLEGRO_EDITOR     UI_GENERAL    Reports when opened from Status Form disappear behind PCB Editor canvas when clicking on canvas
* y* ^! p* }! A) Q) W  G3 B4 P% _1687797 ALLEGRO_EDITOR     UI_GENERAL    Cannot open two HTML windows, one after the other, while using SKILL function
: V5 f6 p, u* V, ~1696229 ALLEGRO_EDITOR     UI_GENERAL    Setting the 'allegro_html' environment variable in User Preferences Editor overwrites existing popup text windows
# Z5 l3 d$ j- `0 I; o$ y3 @6 J' I1708636 ALLEGRO_EDITOR     UI_GENERAL    In SPB 17.2 release, keyboard focus automatically shifts to the newly opened dialog box
0 h, |2 s: V' E; ^1711367 ALLEGRO_EDITOR     UI_GENERAL    Launching two report windows using SKILL is not working in 17.2& e' p7 m2 `. e% p/ w  n  E
1742856 ALLEGRO_EDITOR     UI_GENERAL    Allegro PCB Editor crashes if Project Manager is open for a design in release 17.2 Hotfix 18/ s6 D% n# S5 {) N" R9 L1 K  t6 [
1729519 APD                SHAPE         shape degassing does not generate all voids to cover entire shape
6 \- x5 q4 u, h1711375 CONCEPT_HDL        CORE          Copy-paste of schematic between two instances of DE-HDL is not working as expected
$ Z  d7 ]6 B" m2 N+ `* X6 g1737230 CONCEPT_HDL        CORE          On the Linux platform, copying of schematic objects does not work between designs of releases 16.6 and 17.20 w8 \% u1 _* w/ \  e* }
1741375 CONCEPT_HDL        CORE          Inconsistent behavior of the Move command when moving a symbol
. X4 g6 v% \% G4 k: e1743992 CONCEPT_HDL        CORE          Inconsistent behavior of the Move command when moving a symbol
5 |0 v0 v8 q- ]6 a* c# r4 q1736093 CONSTRAINT_MGR     CONCEPT_HDL   Incorrect topology extraction and mapping errors related to MUX parts
0 Q' K3 s' A2 Q- b% _1743518 CONSTRAINT_MGR     CONCEPT_HDL   Lag observed in expanding and collapsing the net classes in Constraint Manager
! K& v# a" K8 A+ `' O/ n! y1730159 FSP                ALLEGRO_INTEG FSP diff engine does not read PF Thevenin connections in FSP
2 g0 H% s* t. f& u, \9 B1664070 ORBITIO            ALLEGRO_SIP_I Display pads of SMD components on correct layer( b* \0 {' g3 }/ E6 o8 E8 ^: E
1709319 ORBITIO            USABILITY     OrbitIO issues an error about Device template while importing brd with Bundles$ [" Q3 _% O7 E6 q  K  ~8 }7 T
1741150 PSPICE             ENVIRONMENT   Need a way to prevent the 'pspSimSetting.js' file from being overwritten by a hotfix installation in 17.2
% z+ {  O$ E! v) `! E8 C. j1735354 PSPICE             SIMULATOR     Access to custom nom.lib is not working as expected
& N# _; h! |' n# l; _) p1716523 SIP_LAYOUT         COLOR         Tool crashes on using the PageUp, PageDown, and Tab keys in the Color dialog box.) O  m$ W/ H, W" W* a; |1 e

- O' Z0 V* S. }; V6 B5 P6 j1 m6 W% L% c
Fixed CCRs: SPB 17.2 HF019
2 r2 X3 I+ R' p* U3 W1 e05-6-2017# ~: ?' }0 R6 S% {
========================================================================================================================================================
) K* K5 i$ T( w: w. V: h2 ]CCRID   Product            ProductLevel2 Title) h# _% J6 B' b* L5 C; }
========================================================================================================================================================
3 @# {: O5 [4 X% l" Y# @8 W! ], q/ d1701785 ADW                ADWSERVER     Getting 'Unable to locate tools.jar' error while using 'Copy Projects'
$ E3 s) s9 {9 l& ~  B. E1706782 ADW                ADW_UPREV     Design uprev failed with error 'ERROR (FM-107): Failed to run adw_uprev'8 d0 v1 c& V' y+ r: b% Z# s+ m% `
1508159 ADW                FLOW_MGR      Flow Manager 'Open Last Project' option points to a deleted project1 t0 n, }' m2 m/ L" A% d, L' y
1690903 ADW                FLOW_MGR      Flow Manager library project list empty after 'Remove From List'
& p- o) m+ W3 S! i4 L1705224 ADW                LIBDISTRIBUTI Cannot migrate Library Footprint Models having subdirectory to release 17.2-2016
7 o9 j7 q- ?5 [) O1672037 ALLEGRO_EDITOR     EDIT_ETCH     Add ZigZag Pattern crashes PCB Editor
; s* s. Q. B4 s0 G1 A1695711 ALLEGRO_EDITOR     EDIT_ETCH     In release 17.2-2016, Fiber Weave Effect - Add ZigZag Pattern crashes in Windows 10
. q' Z' k6 _( b, Y" M. Y, k. z1706522 ALLEGRO_EDITOR     INTERFACES    DFX import displays error message '*Error* eval: undefined function - cloneID' but imports outline7 g2 j+ x, `3 N5 J+ k; }
1716336 ALLEGRO_EDITOR     INTERFACES    DXF file is not correctly imported into PCB Editor
7 G' l3 [4 n/ Y2 Q1720290 ALLEGRO_EDITOR     INTERFACES    Incorrect rotation of padstack after dxf import9 d! D& E" U7 n4 J
1724683 ALLEGRO_EDITOR     INTERFACES    DXF OUT: incorrect Rounded/Chamfered rectangle pad rotation" x) J! F8 T+ R* D: X) D7 z
1732587 ALLEGRO_EDITOR     INTERFACES    Format/content of ipc356 files exported in release 17.2-2016 different from release 16.6/ G! z3 U; U# A' Z5 h; ?0 N: _3 M" K
1737516 ALLEGRO_EDITOR     INTERFACES    IDX Import works differently for placed and unplaced parts5 h; s& j: C1 _! w$ Z
1715152 ALLEGRO_EDITOR     SCRIPTS       Clicking Layout in Project Manager fails to load PCB Editor and gives message 'Word too long'
& i0 ^4 i$ z6 {- k! v940699  ALLEGRO_EDITOR     SHAPE         Update shape to smooth fails to void a few clines.2 Q& N4 f! Y7 \) m) W' d2 }
1706581 ALLEGRO_EDITOR     SHAPE         Dynamic shape void clearance errors with vias
2 Y: i- t2 s) ]8 V1638300 ALLEGRO_EDITOR     UI_GENERAL    Version information set in $cdsversion truncated on title bar for some tools  \( @/ f+ h2 E9 X6 G
1697732 CONCEPT_HDL        CORE          Pasting a signal name results in warning (SPCOCN-922) if the wire is too close to the edge of the page border
5 O* m2 j/ L. O3 ?1729510 CONCEPT_HDL        CORE          Changing the name of a split block adds pages that are part of the page gaps4 ?& m& v" K2 E: h4 k$ x6 n. q
1721065 CONSTRAINT_MGR     CONCEPT_HDL   Physical import errors on changing plane to conductor in stack-up
4 y. V! Z: q8 x1734875 CONSTRAINT_MGR     OTHER         'Create Spacing CSet' crashes tool from existing CSet context and grayed out in design context- y; a6 A6 G: J% x$ v& z& r
1473104 ECW                PART_LIST_MAN Pulse does not filter capacitor values correctly
  @1 g( f& |  u6 |# l1736580 PCB_LIBRARIAN      SYMBOL_EDITOR Grids are not displayed correctly in Symbol Editor
, h  _4 U; J6 N" D; D  q8 ~& Y1738955 PCB_LIBRARIAN      SYMBOL_EDITOR Need ability to edit Symbol Properties1 q/ D0 }! Y5 q# I( c4 G( v$ d
1735215 PSPICE             FRONTENDPLUGI PSpice part search customization CDN_PSPICE_ODBC_SRC environment variable is not working! Y5 t  G7 X8 r( ]0 o
1733198 PSPICE             PROBE         Probe crashes when exporting trace expressions with multiple plots to CSV files- ~9 T4 P/ o$ s- k( C/ \
1737060 SIG_INTEGRITY      SIGNOISE      signoise fails for the AllegroSigrity_HS_Base_Suite option in release 17.2-2016 and release 16.6-2015; r9 [+ o" X2 k; [8 k0 l2 V/ I2 |
1707443 SIP_LAYOUT         WIREBOND      Moving bondfingers violates spacing constraint2 m6 J. d% a5 `: ?
+ @1 o- C" P0 Q
* Y  P( m) e0 n& Z4 ^; I* @
Fixed CCRs: SPB 17.2 HF018+ O, O4 b, I# z2 n! c3 g6 C
04-23-2017
/ Z5 n( @% O6 s6 q& s* J- B========================================================================================================================================================, @2 w9 |4 V1 w# x" Q
CCRID   Product            ProductLevel2 Title
4 [7 f0 {% ?7 k! L========================================================================================================================================================/ A, X/ [, x3 A( Y% T) q
1721773 ADW                ADW_UPREV     adw_uprev updates all versions in history log to the new version. Should only insert note about uprev.+ \3 a8 g% @: w% K
1684346 ADW                LIBDISTRIBUTI lib_dist_client fails for new release 17.2-2016 design server( S0 M& v+ |2 D9 U
1696632 ADW                LIBDISTRIBUTI lib_dist_client fails on release 17.2 Designer Server having release 16.6 Master Server
2 W3 f) c% r# G6 }( ?1705224 ADW                LIBDISTRIBUTI Cannot migrate Library Footprint Models having subdirectory to release 17.2-2016, m6 e& P; E. G2 |; ^
1721017 ADW                LIBDISTRIBUTI adwserver -install fails intermittently during Master Library Server or MLR distribution
& h. w: v  q2 j  [. z9 Z$ N1711373 ALLEGRO_EDITOR     COLOR         Cannot interact with Allegro PCB Editor when Color dialog is open
5 @. [8 \) v0 K2 ~/ n5 V1710772 ALLEGRO_EDITOR     DATABASE      Mirror command not working on zones
' n1 R( Q5 |: i5 z1725621 ALLEGRO_EDITOR     DATABASE      PCB Editor crashes when moving a group of components or clines
/ W7 `8 N  h! Z. S% r. _1699796 ALLEGRO_EDITOR     EDIT_ETCH     AiDT fails and reports there are no timing constraints even when propagation delay is set
. n% @  {+ d  l1726483 ALLEGRO_EDITOR     EDIT_ETCH     PCB Editor crashing when converting corners to arcs0 H# f! ]% d% }8 I
1726678 ALLEGRO_EDITOR     INTERFACES    IDX copper layer export does not export all pin pads
- k' b$ u5 g" u; d+ \  K1691036 ALLEGRO_EDITOR     MANUFACT      Fillet not centered on trace! s  q& B, [6 l. p9 F# L& I. H( f
1732304 ALLEGRO_EDITOR     MANUFACT      Countersink does not have drill figure on NCCOUNTERDRILL-1 subclass
6 {' i( g! x4 b" e& F0 V1719564 ALLEGRO_EDITOR     OTHER         Cannot open PDF published in release 17.2-2016 in third-party software/ v8 j* ^5 f6 x
1723065 ALLEGRO_EDITOR     OTHER         PDF out does not print the outline correctly3 j( m6 @% F: F, C/ z8 K
1729247 ALLEGRO_EDITOR     OTHER         Cannot delete shape on Route Keepout layer
4 _/ H* x; A6 _9 u% x4 b1722747 ALLEGRO_EDITOR     PAD_EDITOR    Option to enable 'Connect by Touch' in Pad Editor! v* X6 b4 v$ c( }, C! R
1731643 ALLEGRO_EDITOR     PAD_EDITOR    Changes to secondary drill are not saved on padstack update
5 `/ l7 p% `- `3 ]' d1 e* Z1727303 ALLEGRO_EDITOR     REPORTS       The 'Shape Dynamic State' report has changed to 'Shape Dynamic Status' in release 17.2-2016" r! W$ o3 l' w  u) f' n
1695879 ALLEGRO_EDITOR     SHAPE         Dynamic shape priority error creates shorts.# ]# B8 G; r) B$ G4 F1 x
1713014 ALLEGRO_EDITOR     SHAPE         Incorrect behavior of donut shaped pads at certain rotations
0 l( ^, |; m/ H" e+ b3 F# z. x1588769 ALLEGRO_EDITOR     UI_GENERAL    Alt+key shortcuts are not available in release 17.2, E, b& g! }' G0 z
1602563 ALLEGRO_EDITOR     UI_GENERAL    Shortcuts to menu items not working in release 17.2
- J* p0 W+ J& ^- f4 \6 s1603776 ALLEGRO_EDITOR     UI_GENERAL    Alt key not working with menu commands
5 [5 b# n+ J& n. i- O1611516 ALLEGRO_EDITOR     UI_GENERAL    Keyboard shortcuts have no response; u5 t7 [9 B+ r: U' ]4 v" g8 O
1647271 ALLEGRO_EDITOR     UI_GENERAL    Preselection is not working for docked Find window' q' S9 h! w! F* O
1650044 ALLEGRO_EDITOR     UI_GENERAL    Keyboard shortcuts are not working properly in release 17.2
% Z" s( |. |% B- [" l1 Q1651912 ALLEGRO_EDITOR     UI_GENERAL    Inconsistent response when using the Alt key: G: T+ l' F/ |6 i0 ~
1679964 ALLEGRO_EDITOR     UI_GENERAL    Many dialog boxes are blurred in Allegro PCB Editor
  L; |6 I! z+ p& U' J9 ?; }1692416 ALLEGRO_EDITOR     UI_GENERAL    Underscores in menu commands denoting shortcuts are missing in release 17.2  i9 {9 N0 A9 a' f6 b- J0 A; {6 |/ D
1693055 ALLEGRO_EDITOR     UI_GENERAL    Reports with html links end with an extra > at the end
$ w, t& ?4 A1 C1693968 ALLEGRO_EDITOR     UI_GENERAL    Batch process that uses SKILL is taking too long to process files and generate reports
" w5 _4 |1 |' t% s5 X1698840 ALLEGRO_EDITOR     UI_GENERAL    In release 17.2-2016 Waive DRC report, selected coordinates of a Waived DRC remain blue; W! |" T$ O' f+ ^2 h6 Y
1703065 ALLEGRO_EDITOR     UI_GENERAL    Menu shortcuts do not work as expected
4 g9 x  m' S) ~1 ^; J7 n% R1707547 ALLEGRO_EDITOR     UI_GENERAL    Release 17.2: The Alt key function is not working in PCB Editor/ \' k% U' P) i3 k3 j. i# ~5 f
1709280 ALLEGRO_EDITOR     UI_GENERAL    Alt+Function key not working in release 17.2.
" g8 a( o5 Y* J- y1711203 ALLEGRO_EDITOR     UI_GENERAL    Color does not change for selected coordinates in reports and Show Element- r8 C$ }& E8 \; J# Y! `
1711724 ALLEGRO_EDITOR     UI_GENERAL    In release 17.2-2016, custom interactive menus stop responding when invoking another custom command( z* p4 ^; q4 d! I/ i
1715613 ALLEGRO_EDITOR     UI_GENERAL    With undocked Options window there is a mix up of entered text and funckey+ v3 j4 @% p# X9 F: K
1719301 ALLEGRO_EDITOR     UI_GENERAL    Selected coordinates do not change color in reports and Show Element+ l% O1 V( C/ d" r  S* i4 t, d( ^
1724197 ALLEGRO_EDITOR     UI_GENERAL    Short cuts and hot keys not working in PCB Editor in release 17.2-20160 |+ _" N% S4 e% h( c( @1 ]0 y8 v% g
1728724 ALLEGRO_EDITOR     UI_GENERAL    Funckey is not working in release 17.2-2016
4 _. a9 O: X3 S9 S1673703 ALLEGRO_PROD_TOOLB OTHERS        Design compare not reporting the Top and Bottom layer differences& H# I/ F- Z5 C# L& R& R! b
1704474 ALLEGRO_PROD_TOOLB OTHERS        When using Productivity Toolkit - PCB Design Compare, 'Override undefined width' is incorrectly applied, J+ c. @0 F  {
1571035 ALTM_TRANSLATOR    CAPTURE       Circles in third-party schematics not getting translated into Capture
* T: L% S* x8 H& o4 B. o9 J: K4 c- D( p1588911 ALTM_TRANSLATOR    CAPTURE       Capture crashes when translating, project and libraries are empty
5 P6 ]0 Z* l$ {% q) w* h1589394 ALTM_TRANSLATOR    CAPTURE       Schematic getting shifted off the page after translation+ ~) l: p% m7 e; U( {- P7 C3 ^
1631294 ALTM_TRANSLATOR    CAPTURE       Errors while translating third-party design when original design is in metric units7 [4 j) \2 C) Z9 B: Q( O+ M
1663176 ALTM_TRANSLATOR    CAPTURE       Only first sheet of design getting translated from third-party schematic into Capture
+ E9 y8 L: o5 [3 ~1694363 ALTM_TRANSLATOR    CAPTURE       Capture is unable to translate third-party designs
& S. V. q5 N, a2 E/ e6 I* p1539739 ALTM_TRANSLATOR    CORE          Capture crashes on importing a third-party project+ h5 T7 {3 d( }8 o
1542860 ALTM_TRANSLATOR    CORE          Capture crashes on clicking Translate after selecting a third-party design
3 U% R$ _$ A+ w- S  m6 w( J1551642 ALTM_TRANSLATOR    CORE          Unable to import third-party schematics into Capture
, u* w& \! I, X' _1572929 ALTM_TRANSLATOR    CORE          Footprint names getting altered during translation: b8 c) \; Q5 H9 v
1568436 ALTM_TRANSLATOR    PCB_EDITOR    Unable to translate third-party layout data into PCB Editor3 K, T8 @  ~( C2 e, d! u1 @5 l9 B
1629256 ALTM_TRANSLATOR    PCB_EDITOR    Getting empty symbol and devices folders when importing into PCB Editor9 M; Z- J7 Y! j5 K# f, z% E, P7 ]
1664120 ALTM_TRANSLATOR    PCB_EDITOR    Import from third-party to PCB Editor is not translating data correctly
% U; R2 J8 ^; `- L" [2 K3 p5 G1701537 ALTM_TRANSLATOR    PCB_EDITOR    Import does not complete and reports errors8 f: U! y' ]- Z& i& T; ?0 P1 i
1698706 APD                DIE_GENERATOR When using Compose Symbol from Geometry, circle from DXF cannot generate to pin9 H, }% ^; B* a/ m
1714528 APD                DIE_GENERATOR Getting 'illegal pad pointer' warning when creating die from geometry
3 s' h. r" {0 m1714532 APD                DIE_GENERATOR Compose Die from Geometry creates incorrect pad shapes4 H2 w7 h5 X" S' H, d0 R) a
1734310 APD                MULTI_USER    Symphony server mode malfunctions when die layer present.' O* m* B8 q1 M2 T7 D
1725506 APD                SHAPE         In release 17.2-2016 Hotfix 015, void is not generated in Artwork for BC7 layer causing short6 V: ?% u, k+ X( L+ p* I2 U
1724395 APD                WIREBOND      Running axlBondWireDelete returns error message
" p/ v8 b. W( h" J: t$ `1 g1726609 ASDA               CANVAS_EDIT   Paste should not be allowed in the Current Refdes column of the Change Refdes form
: W. i; l1 {1 P6 _. ?& y: J2 [1719754 CONCEPT_HDL        ARCHIVER      Path stored in the compressed file starts from /home instead of the current working directory
0 c. `& B) T" R. p  G9 U8 A$ T1726570 CONCEPT_HDL        CHECKPLUS     Checkplus crashes on Windows 104 \. z$ h; Y* l- I7 m( O' R
1697977 CONCEPT_HDL        CONSTRAINT_MG Differential pair disappears when it is packaged
' [; m7 J% t3 J# H+ A  P1679575 CONCEPT_HDL        CORE          Page numbers are duplicated in Hierarchy Viewer when editing page names
( J! X2 l- q) S! Y3 V6 y1697732 CONCEPT_HDL        CORE          Pasting a signal name results in warning (SPCOCN-922) if the wire is too close to the edge of the page border
" @7 _4 Q: T0 {2 F4 z1711564 CONCEPT_HDL        CREFER        CRefer crashes while processing a hierarchical design containing subdesigns8 [( r! h+ l5 G* ^
1730736 CONCEPT_HDL        OTHER         Crash on generating BOM from design
$ Z0 O! R' {- ]6 m' h* g; ?1608350 CONSTRAINT_MGR     CONCEPT_HDL   Name of buffer model is not passed from Constraint Manager of DE-HDL to SigXplorer$ ^) Q9 N9 ?6 x1 V& B8 }
1715803 CONSTRAINT_MGR     CONCEPT_HDL   Extract a net from constraint manager to SigXplorer, the models assigned are not displayed in SigXplorer
4 [. B8 w& Q# ~  L! P1718073 CONSTRAINT_MGR     CONCEPT_HDL   ECSet mapping errors on an upreved design in release 17.2: Pins in XNet and CSet do not match
5 G$ u7 {3 Y! G: Z4 m, r1720886 CONSTRAINT_MGR     CONCEPT_HDL   SigXplorer does not extract assigned model from the schematic
! ?0 C1 `- h1 A' y1718514 CONSTRAINT_MGR     ECS_APPLY     Extracted topology does not use the PINUSE overrides specified on the canvas) g' o$ Y0 R% F5 p4 c
1722306 GRE                CORE          Boards with Total Etch Length constraint only should not include z-axis when budgeting pin pairs% G5 r4 q. i$ R& Z& h- z
1710049 PSPICE             SIMULATOR     Functions are not taking parameters in correct order
; Q2 V, J2 X( Z! l1693021 SIG_INTEGRITY      OTHER         PINUSE is not updated correctly at model assignment with specific steps: s# e9 _# U- C& v
1730854 SIP_LAYOUT         SYMB_EDIT_APP Cannot delete all the die pin from a symbol using the Symbol Edit application mode" L; E; `3 @( Y" M

6 e3 r* H7 p( C" B1 y+ f
" p9 O/ j0 h# dFixed CCRs: SPB 17.2 HF017
$ I3 o) a, W4 \( l0 N# z4 B04-13-2017
8 D- R4 l4 J# F4 c/ U7 z========================================================================================================================================================+ w& ?5 G; q% ~% Y  u2 P8 S
CCRID   Product            ProductLevel2 Title) k& s8 w( Z  c! t. X
========================================================================================================================================================
) x0 ~+ |" [0 r* N' l1732877 ALLEGRO_EDITOR     SKILL         The 'axlXSectionGet' function fails in release 17.2 Hotfix 0165 z; ~- P8 P6 a/ }

% ]; D5 q  L% ^3 g
% ^3 o$ p& z: x) l4 m* v6 \/ PFixed CCRs: SPB 17.2 HF0163 Z, N: M  [, \2 q3 o- n
04-6-20171 f9 y0 `8 C" A0 _
========================================================================================================================================================1 Y, L9 k, B+ W/ f3 v' t! [5 a5 I
CCRID   Product            ProductLevel2 Title
* p7 v! z; W! @* K. G========================================================================================================================================================0 w4 j$ N+ @9 g
1673128 ADW                COMPONENT_BRO Directive is saved in project CPM) p" q, f& e1 l9 a4 P' c, c/ G7 }3 C
1673510 ADW                COMPONENT_BRO Lifecycle status color column is not sorted correctly in Component Browser search results% K, H6 D  @; N( L! u  v
1604734 ADW                DATABASE      Parts displaying non-key properties and values in the Component Browser in ADW
8 \( H1 j5 w% A" c$ r1142957 ADW                DSN_FLOW      No Help available for schematic design verification
- V# V& x- s% G1609186 ADW                DSN_MIGRATION ADW Design Migration utility should handle ADW board reference projects and manage atdm.ini) F+ `9 U4 U9 q  V; T' v- X
1591757 ADW                GENERIC_UI    Running 'Create Test Schematic' in ADW Flow Manager results in Error SPCOCN-1736
2 b9 m( a0 K# h2 E4 `1588111 ADW                LIBIMPORT     Library Import fails with Java errors while processing .csv files
: [+ K; g8 s) d1642367 ALLEGRO_EDITOR     3D_CANVAS     Component height is not correct in new 3D Viewer; K' i) G1 _. n' r. h
1642668 ALLEGRO_EDITOR     3D_CANVAS     The new 3D canvas does not show STEP model of the drawing (.dra)
( |! }' T" q$ Y1 n+ H! c1653247 ALLEGRO_EDITOR     3D_CANVAS     New interactive 3D Viewer shows wrong placement/ v$ K# V! j" I
1658275 ALLEGRO_EDITOR     3D_CANVAS     Components on the bottom side are shifted in the new 3D view
/ ~, J! z1 T: m* X8 c4 B. g1639244 ALLEGRO_EDITOR     ARTWORK       When importing an artwork, a sub-folder is created with the value of the ads_sdart environment variable' m& n$ ]5 \6 |  {( B' C1 S
1658173 ALLEGRO_EDITOR     ARTWORK       ARTWORK: Value of Scale factor for output.
; B2 i$ g9 T# |* k% }  ^7 j1661760 ALLEGRO_EDITOR     ARTWORK       Import artwork to Design Outline layer does not give error in Allegro prompt.$ a' B# r) n0 f  i
1667778 ALLEGRO_EDITOR     COLOR         Add option to set FORM mini dehl_retain_color to NO- \, {/ A- _: U, a3 l2 f" t
1669462 ALLEGRO_EDITOR     COLOR         Changes made to the Visibility tab are not reflected in the Color Dialog window
9 y/ k2 p8 J& J6 T- c# Q1641265 ALLEGRO_EDITOR     CROSS_SECTION The differential impedance value for a layer is not getting updated8 [* E; K! z' N$ U0 q0 n
1648149 ALLEGRO_EDITOR     CROSS_SECTION Getting warning when calculating impedance in mixed stackup
. _5 J# r$ p) F8 _! O+ Y) t1671441 ALLEGRO_EDITOR     CROSS_SECTION Enhancement request for cross section dialog box1 o# u1 Y- S  }  N  B$ }9 R, U) L
1673320 ALLEGRO_EDITOR     CROSS_SECTION Diff impedance calculation fails+ s- k' |+ V& Q- s
1690021 ALLEGRO_EDITOR     CROSS_SECTION How to keep settings of expanded/compressed columns in the Xsection6 s, N! \) m  b$ L
1703831 ALLEGRO_EDITOR     CROSS_SECTION Calculation of Diff Z0 fails in flex designs5 M" m% Y+ `$ ^
1711484 ALLEGRO_EDITOR     CROSS_SECTION ShowAll Column does not retain its status
/ M8 u  o* v4 q1672841 ALLEGRO_EDITOR     DATABASE      ERROR(SPMHDB-153): Table corrupt; current/maximum mismatch
4 @7 Q$ W0 U+ [) J3 q# k1673613 ALLEGRO_EDITOR     DATABASE      COVERLAY_TOP not present in the Non-conductor section of Color Dialog window
( X3 h. O! a5 n% [1688123 ALLEGRO_EDITOR     DATABASE      Drill Plating Issue
$ G# x7 d% u: \5 e' H3 C3 b6 X  S& d1701995 ALLEGRO_EDITOR     DATABASE      When upreving a 16.6 brd to release 17.2, lines drawn on OUTLINE are translated to CUTOUT and not DESIGN_OUTLINE
* i, C7 N# N/ n/ f% i& ]" ^. p- n1710772 ALLEGRO_EDITOR     DATABASE      Mirror command not working on zones
* E  C0 `% h! o+ D  y* S. j$ \1713335 ALLEGRO_EDITOR     DATABASE      Defining Adjacent_layer_keepout_above and/or Adjacent_layer_keepout_below and then saving the .dra file giving error
" g- ^3 r/ H$ u* c- E1693289 ALLEGRO_EDITOR     DFA           File - Save As script does not save the DFA file
6 M3 h7 f- |; B& W7 s; g+ D1644004 ALLEGRO_EDITOR     DRC_CONSTR    Unreported DRCs from dynamic copper to line and dynamic copper to SMT pin
& Z3 f2 S0 a: V' z! e0 [- c1651425 ALLEGRO_EDITOR     DRC_CONSTR    The .brd file crashes when moving text controlled with minimum metal to metal constraints# ]$ j# n9 u+ o
1663494 ALLEGRO_EDITOR     DRC_CONSTR    Reported Mechanical Pin to conductor spacing DRC constraint value is incorrect leading to false DRCs! t, X; v4 T( ?- n
1687049 ALLEGRO_EDITOR     EDIT_ETCH     Create a Via Structure disconnects nets
, Y, l4 [; S( E  d. n7 ?1704296 ALLEGRO_EDITOR     EDIT_ETCH     Asymmetrical fanout created for BGA Quadrant style$ _0 G2 m" C6 D9 [' y, |, Z
1686873 ALLEGRO_EDITOR     EDIT_SHAPE    Merge static shapes deletes both the shapes selected.
# t0 [/ V4 r0 ^1629925 ALLEGRO_EDITOR     GRAPHICS      Errors reported and no layout data drawn in PCB Editor in release 17.2 Hotfix 003 on Ubuntu 14.041 k( R# J. r+ r& ^1 ?
1628895 ALLEGRO_EDITOR     INTERACTIV    Shape Edit mode: An error message is required when attempting to edit a Shape with the FIXED property; [: b9 E' Q5 c! Q' x0 A! a
1666379 ALLEGRO_EDITOR     INTERACTIV    Place replicate is not working on the attached test case
$ W7 ?( y! P& ~* R1668282 ALLEGRO_EDITOR     INTERACTIV    Grid display incorrect for repeated grids
* ]% B1 n! `6 ^5 h" u% F1675531 ALLEGRO_EDITOR     INTERACTIV    Design Entry CIS: Cross Probing with PCB Editor and Constraint Manager is not working
" P3 f  Q5 z# W8 a5 d* y1694470 ALLEGRO_EDITOR     INTERACTIV    Update description of variable padstack_nowarning_display
' b4 Z: X+ h  E  L3 r! Y& x1696855 ALLEGRO_EDITOR     INTERACTIV    Mixed grid setting is not displayed correctly on Define Grid screen.
7 K( F, Q& i% M1 M1698192 ALLEGRO_EDITOR     INTERACTIV    Deleting and replacing a component causing database corruption in Hotfix 009
$ \0 F! {/ {3 a2 X) g/ A1703671 ALLEGRO_EDITOR     INTERACTIV    An error occurs when defining grids with zero increment value
' Q5 ~+ L# ]3 h4 T; M! Z1703812 ALLEGRO_EDITOR     INTERACTIV    Crash during move when using the 'snap pick to' option set to symbol origin4 I. V8 e6 z5 U6 g4 {# R
1719276 ALLEGRO_EDITOR     INTERACTIV    Setting variable grid for 'All Etch' displays an error in the Define Grid form
6 Q4 L" a( H5 e1663422 ALLEGRO_EDITOR     INTERFACES    Shape loses group membership after importing through sub-drawing# w  h7 I* u4 R
1637959 ALLEGRO_EDITOR     MANUFACT      Thieving uses different clearance values around the route keepin., P2 x6 k; ?4 z! p3 [/ R  _
1716431 ALLEGRO_EDITOR     MANUFACT      Test points generation stops due to an error
+ v4 m  s/ J, z6 N1641994 ALLEGRO_EDITOR     OTHER         DB Doctor: Incorrect spelling of 'eliminated' in the log file messages; @* z  N4 v: F
1660496 ALLEGRO_EDITOR     OTHER         SiP Layout crashes when trying to generate abstract level view by using export chips and connectivity
. h* C$ m4 ~' b/ i  v1685464 ALLEGRO_EDITOR     OTHER         The 'alias ~S save' command is not recognized when set in the local env file
& T- x$ e6 {5 ^+ ]4 U  A8 C' _1696486 ALLEGRO_EDITOR     OTHER         STEP export results vary between releases 16.6 and 17.2
2 f+ H! r6 b0 F; i1706623 ALLEGRO_EDITOR     OTHER         axlBackdrillGet crashes for invalid argument5 ^3 |& p8 i" k- l: i) Y6 I# ]
1586957 ALLEGRO_EDITOR     PAD_EDITOR    In Pad Editor, selecting a pad geometry is not showing up in the Design Layers tab
! m4 {: I  a  r, \+ C1610984 ALLEGRO_EDITOR     PAD_EDITOR    Geometry set in tabs not read, only initial value set in Start page is used
4 x+ F2 E1 V2 ^+ |+ `! P1614015 ALLEGRO_EDITOR     PAD_EDITOR    Padstack Editor in release 17.2 does not auto fill geometry in design layers  A: x, J! L! |( s0 O9 w
1636012 ALLEGRO_EDITOR     PAD_EDITOR    Keepout should not be allowed if antipad is not defined for outer layers
' M% S: ^# g& X' a1641973 ALLEGRO_EDITOR     PAD_EDITOR    Padstack Editor: Path to the previously opened .pad file is not seeded in the File - Open dialog on a fresh launch
* V# a4 @! x! s% D* e1642789 ALLEGRO_EDITOR     PAD_EDITOR    In release 17.2, 'Units' and 'Decimal Places' in Padstack Editor are not updated as per the .pad file7 s% i% P7 s' d) z3 g
1646914 ALLEGRO_EDITOR     PAD_EDITOR    The 'Save' button is grayed out in Padstack Editor
: A) Q7 }  h9 [8 N1 `: n1657553 ALLEGRO_EDITOR     PAD_EDITOR    No possibility to specify Padstack Editor default library path at invocation/ n3 }: Z: k% R, b3 }: |
1657609 ALLEGRO_EDITOR     PAD_EDITOR    Changing Tolerance field in Padstack Editor does not activate the Save button- _2 x7 E. {6 d; {  q
1662225 ALLEGRO_EDITOR     PAD_EDITOR    Padstack editor dialog message doesn't match available options
) R* k1 u3 Q7 ]- c7 ~1667062 ALLEGRO_EDITOR     PAD_EDITOR    Padstack editor does not retain the decimal places from the previous session% U5 r% k3 y7 x5 K9 {0 X
1672774 ALLEGRO_EDITOR     PAD_EDITOR    Pad Editor graphics appear to show offset incorrectly
, s8 ]7 ~$ E/ B' I: I  ]6 f1674157 ALLEGRO_EDITOR     PAD_EDITOR    Update Symbols does not update Pad Type Information' R/ W. E  d" B. B" O# N
1675438 ALLEGRO_EDITOR     PAD_EDITOR    Drill hole size warning for the SMD pad
4 m% a9 s5 [, C* i. y8 u/ ]1684376 ALLEGRO_EDITOR     PAD_EDITOR    Pad Editor issues with settings, such as decimal places, layers, and so on
+ s, Z$ N4 R2 U  Y! k/ Z1690376 ALLEGRO_EDITOR     PAD_EDITOR    Variable padstack_nowarning_display fails to suppress warnings7 o% a3 e4 n  H* M" g% W
1694649 ALLEGRO_EDITOR     PAD_EDITOR    Change&nbsp;Cancel button to No in warning generated when&nbsp;updating padstacks in design layout
# B8 p2 b9 @7 q/ q$ q. I939242  ALLEGRO_EDITOR     PLACEMENT     Cross probing between Capture and PCB Editor is inconsistent! h8 L8 z  ~1 I7 W* x
1103945 ALLEGRO_EDITOR     PLACEMENT     Place Replicate Create does not include the etch connected to pin
+ z; d. U, f- q3 ^  x1233019 ALLEGRO_EDITOR     PLACEMENT     Allow cross probe object selection apart from highlighting during place replicate
7 S* [& Z/ j; V0 u1643078 ALLEGRO_EDITOR     PLACEMENT     PCB Editor flags an error message when a module is placed at a specific angle& [" P8 F% L5 I$ @
1696932 ALLEGRO_EDITOR     PLACEMENT     Inconsistency with Snap pick to when selecting Segment Midpoint
3 O# @3 K  n- C5 W1 o1654500 ALLEGRO_EDITOR     REPORTS       In release 17.2 Hotfix 006, display of Netin (back anno.) report fails when variable ads_sdreport is set
5 }# J6 C; ^' R4 F0 q5 x! D/ s1643992 ALLEGRO_EDITOR     SCHEM_FTB     Export Physical fails with the 'netrev.exe has stopped working' error
; ^! o! l* W7 _1653400 ALLEGRO_EDITOR     SHAPE         Dynamic shape does not void a via.
, Q2 a+ G& e+ Q- }0 M+ u0 A1668262 ALLEGRO_EDITOR     SHAPE         dynamic shape does not void custom route keepout with arc
' B: ^" T3 I& P5 t! K/ c7 v2 E- t, m8 C1682569 ALLEGRO_EDITOR     SHAPE         Variable 'dv_squarecorners' not working correctly.
$ Q7 i3 b. F/ K$ i4 j1696240 ALLEGRO_EDITOR     SHAPE         SKILL error when merging polygons
) K& y# D0 \: ~6 N* k$ W/ A. `1709968 ALLEGRO_EDITOR     SHAPE         In release 17.2, DB Doctor reports error in shape when no error was reported in release 16.6 for the same shape
: Z% x5 U, A; q8 W) k  B% N; ]& f1632505 ALLEGRO_EDITOR     SKILL         In release 17.2 Hotfix 004, PCB Editor crashes after SRM update and save
/ j3 Y# A" x8 L$ A! S8 X* p1651701 ALLEGRO_EDITOR     SKILL         Cannot set the etch factor value in the cross-section using the axlXSectionModify() SKILL command
% B% ~& t6 ?0 b- T% u2 b# i1658419 ALLEGRO_EDITOR     SKILL         PCB Editor crashes after running SRM
  U* J% i2 w8 ]% v1658948 ALLEGRO_EDITOR     SKILL         axlIsLayerNegative() is not working in release 17.2; m3 D5 l! K- R
1670956 ALLEGRO_EDITOR     SKILL         axlIsLayerNegative() always returns nil  I# l) b! U3 Y; _9 ~& U* [( b% C- ^
1687239 ALLEGRO_EDITOR     SKILL         Problem with SKILL function axlCNSGetPhysical - incorrect parse string
2 q! ^9 ?% c# \: o$ l: ^6 q4 ^6 R1692345 ALLEGRO_EDITOR     SKILL         The axlGetParm documentation example for deleting an artwork record is incorrect.
6 g& g  w/ a6 M$ d! e1707878 ALLEGRO_EDITOR     SKILL         Object rat_t does not work with axlDBPinPairLength.7 P1 ^, I: r& g" M0 J! p
1598061 ALLEGRO_EDITOR     UI_GENERAL    Adjust menus to allow side by side view! p% c6 x4 \! h& }8 {, W
1599901 ALLEGRO_EDITOR     UI_GENERAL    Color Dialog box is not updating according to visibility tab.
% d/ q! |: c! n1602563 ALLEGRO_EDITOR     UI_GENERAL    Shortcuts to menu items not working in release 17.25 P" T, }& S, S( y' K6 V
1603776 ALLEGRO_EDITOR     UI_GENERAL    Alt key not working with menu commands
9 I0 \1 n- C- o2 N; Q% J1611516 ALLEGRO_EDITOR     UI_GENERAL    Keyboard shortcuts have no response  b0 {# v2 x- `6 i
1614763 ALLEGRO_EDITOR     UI_GENERAL    Cannot scroll to the bottom of an undocked command window in PCB Editor: f6 Y* P- |  i
1619873 ALLEGRO_EDITOR     UI_GENERAL    Command Window scrollbar does not reach its end
/ J; ~0 O: b! M* T/ w7 P6 i1624617 ALLEGRO_EDITOR     UI_GENERAL    Dialog box title under Setup > Outlines > Design Outline... Design is misspelled as "Desgin"
" w- M) |% ]) z- x1631646 ALLEGRO_EDITOR     UI_GENERAL    Visibility pane not retaining the correct layer view
2 h4 g9 H: T' g9 x. D4 G8 i1637062 ALLEGRO_EDITOR     UI_GENERAL    The last line of the floating command window in release 17.2 is hidden behind the command window frame0 ]$ ^! S# u& [! q$ |0 D! z, F
1642645 ALLEGRO_EDITOR     UI_GENERAL    Cannot scroll to the bottom of an undocked command window in PCB Editor
# V! G% Z, l; O: Z/ B3 P# B1645335 ALLEGRO_EDITOR     UI_GENERAL    PCB Editor crashes in Hotfixes 004 and 005 if ODE and Allegro Manufacturing options are installed/ Y/ A) l6 U- m# V8 M
1647520 ALLEGRO_EDITOR     UI_GENERAL    PCB Editor crashes after installing release 17.2 Hotfix 005; G3 d. X% G# ~) f& C
1647541 ALLEGRO_EDITOR     UI_GENERAL    Release 17.2 Hotfix 005: PCB Editor crashes immediately after launch
# K) \* S) ~! d1650044 ALLEGRO_EDITOR     UI_GENERAL    Keyboard shortcuts are not working properly in release 17.2* V& h. _# T7 U: Y' w$ c; [
1651912 ALLEGRO_EDITOR     UI_GENERAL    Inconsistent response when using the Alt key
' @; t3 h& @: R! p" U0 f. h& F( T1652423 ALLEGRO_EDITOR     UI_GENERAL    Using the F1 key does not display the help document+ Y4 _+ U! o! ~- j4 i
1654600 ALLEGRO_EDITOR     UI_GENERAL    Spelling Mistake in "Design Outline" dialog box, Setup->Outlines->Design Outline, misspelled as "Desgin"6 T* ]4 g" ?3 x6 C. R/ }
1654777 ALLEGRO_EDITOR     UI_GENERAL    Reports UI does not work properly when writing a report file./ D3 S6 t- T/ Q3 ^9 ~: A3 a
1655500 ALLEGRO_EDITOR     UI_GENERAL    Visibility selection ignored after color change/ b3 q" {2 e( ]& a3 ~& Z
1655514 ALLEGRO_EDITOR     UI_GENERAL    Artwork Film is available in the View section only after you restart PCB Editor
$ a0 z4 F/ S) Y3 z4 _1663819 ALLEGRO_EDITOR     UI_GENERAL    In release 17.2, SKILL function, axlOpenDesign(), does not work as expected
6 ^, r! r7 T7 w$ p6 K% f1671334 ALLEGRO_EDITOR     UI_GENERAL    Design outline is not shown in 'World View' window
4 H$ G# S5 f7 D3 y" D" j1672148 ALLEGRO_EDITOR     UI_GENERAL    Add option in release 17.2 to change the placement of the Find, Visibility, and Options tabs similar to earlier release
/ f, h! A; _2 `4 p& ?1679418 ALLEGRO_EDITOR     UI_GENERAL    On choosing Edit - Move, the 'Symbol pin #' box is obfuscated7 o7 c$ B: I% F2 D# w1 j& ^. x  h
1679761 ALLEGRO_EDITOR     UI_GENERAL    Choosing Edit - Spin hides 'Symbol pin #' partially
) c( J+ h* d# ~1686887 ALLEGRO_EDITOR     UI_GENERAL    Hyper Text no longer selects coordinates for easy copy  S! m: n# d5 a) I1 u# }
1687286 ALLEGRO_EDITOR     UI_GENERAL    In 17.2 Hotfix 009, the Static Phase meter shows up in the middle of the screen instead of the lower-right corner; h. Y" U, u( ~+ z
1692416 ALLEGRO_EDITOR     UI_GENERAL    Underscores in menu commands denoting shortcuts are missing in release 17.2
" j9 ~8 E9 f- g" C$ C! ?3 |2 J1693968 ALLEGRO_EDITOR     UI_GENERAL    Batch process that uses SKILL is taking too long to process files and generate reports
( t4 g; F4 j4 I8 Q* t1702420 ALLEGRO_EDITOR     UI_GENERAL    Unable to maximize&nbsp;reports viewer&nbsp;in 17.2" I" Y7 q( u2 k/ O0 d
1703065 ALLEGRO_EDITOR     UI_GENERAL    Menu shortcuts do not work as expected
7 R- b7 B/ q% h1703107 ALLEGRO_EDITOR     UI_GENERAL    Scripting using regional settings for decimal separator
' H/ F% E8 @# T4 W8 y0 W1707547 ALLEGRO_EDITOR     UI_GENERAL    Release 17.2: The Alt key function is not working in PCB Editor* r% i% a' k9 V5 F0 _, l
1709280 ALLEGRO_EDITOR     UI_GENERAL    Alt+Function key not working in release 17.2.* P$ {1 @3 l: ]+ {
1639896 ALLEGRO_PROD_TOOLB CORE          MFG collector does not move files to subdirectories
- h  j  ^7 m4 H1 t( L1608804 ALTM_TRANSLATOR    DE_HDL        Translation issues in symbols with multiple physical pins mapping to a single logical function
: A/ ~7 p8 O# a1658525 ALTM_TRANSLATOR    DE_HDL        Invalid characters in pin names4 Y# b& h! @  [# E' G" v6 ]( b
1658536 ALTM_TRANSLATOR    DE_HDL        All cell names should be generated in lowercase letters/ j0 G/ v; h5 a+ `% d
1609962 ALTM_TRANSLATOR    PCB_EDITOR    Errors reported during design translation* l/ ?& }8 B4 z8 r8 _6 {
1661562 APD                DRC_CONSTRAIN The wrong space calculation on finger to trace# K+ b# T0 H5 Q
1682398 APD                SHAPE         Deleting islands causes out of date shapes- D+ J5 _9 r7 ~) @5 }
1638112 ASDA               CANVAS_EDIT   Unable to rename multiple selected buses using the 'Assign Name' command
/ q( \" c- C7 ^1 z( t1645571 ASDA               CANVAS_EDIT   Various routing inconsistencies with synonym bodies on the canvas
* H$ B* t, f% ?( ~$ m1656336 ASDA               CANVAS_EDIT   Presence of illegal characters in the net name removes the entire net name8 [7 V' [8 b2 r3 ?( y% t  i
1667176 ASDA               CANVAS_EDIT   Unable to add the port symbol in a specific scenario( D. D3 j" }4 T! H4 @3 [
1641473 ASDA               CONSTRAINT_MA Importing a tech file into SDA makes the tool unresponsive
/ h( O# e7 P0 D) J: V# f1 x8 @1661350 ASDA               CONSTRAINT_MA Unable to create physical & spacing class from the docked CM
* \. `" d+ I, `" Z, P% R. Z5 o1645557 ASDA               IMPORT_DEHDL_ Importing a DE-HDL design into SDA adds the COMMENT_BODY attribute to nets/ I+ M$ Z2 [2 T8 H6 h9 j
1652753 ASDA               MISCELLANEOUS Tcl command window should display correct casing for autocompleted command
2 T3 w. I/ H, P/ S& u; B1 W1654973 ASDA               MISCELLANEOUS If there is a casing mismatch in the Tcl command name, correct command is not picked from the list
9 ?/ d: d! Q: b5 U5 a) G$ Z1652718 ASDA               PAGE_MANAGEME Page numbering on the page border does not update correctly when pages are moved, added, deleted
, A4 F, }. A/ w1 a1699454 ASDA               TABLE         In the table object, cursor skips a cell on the first use of the TAB key. L, h7 ?: x$ z$ c( g, l( E
1702702 ASDA               TABLE         Copy-pasting table objects to a new page fills the headers and rows in black
) h% v5 f; o7 b5 U3 [0 L$ J- w1668877 CAPTURE            ANNOTATE      Using Ctrl+drag does not preserve the reference designator value
! F# s0 C" |! e2 M1665454 CAPTURE            NETGROUPS     Incremental copy for alias does not work anymore.
+ ~: h' m, m1 N5 L6 M+ I7 O1634598 CAPTURE            OTHER         The ‘OrCAD_Capture_CIS_option’ license not released even after selecting another product option
2 l- {6 J! N/ x  `& c6 `( @1 P5 k& y1636090 CAPTURE            OTHER         Capture crashes after switching from release 17.2 Hotfix 003 to 004 due to some Tcl files
( ~$ ^: Z% E0 ]. \, f1650029 CAPTURE            OTHER         Crash while archiving a newly created PSpice project without adding simulation profile
% O4 J6 d: ^: M6 R& l' n1659602 CAPTURE            OTHER         Saving CIS BOM via TCL command window
8 |  ^% b4 m# ~3 P1678715 CAPTURE            OTHER         Capture.ini [WebResourcesMenu] is not working in release 17.2
% }6 k  Z8 i. e4 b- \1619449 CAPTURE            PROJECT_MANAG Search not working in a PSpice project- S- {6 ~1 C+ O) K7 x
1670133 CAPTURE            PROJECT_MANAG Start Page showing wrong Software Version2 F# b+ r" ~) y1 G( T
1670766 CAPTURE            PROJECT_MANAG autoreference does not work properly
' O; N0 E# P# S' v# }1676095 CAPTURE            PROJECT_MANAG (SID:22758) OrCAD Capture Start Page reporting wrong hotfix installed! K7 T! \) ?; `2 l6 e
1658315 CAPTURE            TCL_INTERFACE Inserting text with double quotes is not working as expected in PDF created from Capture: h& C7 O7 @2 z& J, G
1642601 CIS                OTHER         Design Entry CIS: SQL server password is required each time the tool is launched
% v2 N6 ]2 `& c1712279 CONCEPT_HDL        CONSTRAINT_MG Differential pairs are dropped from Net Classes when upreved to release 17.2-20166 L( J) Q* o; w
1665449 CONCEPT_HDL        COPY_PROJECT  Copy project fails with error COPYPROJ-777 U( a6 ^. \% n$ _% ^; ^
1661778 CONCEPT_HDL        CORE          Advanced Find will not find pins with the SIG_NAME property attached
7 N: h7 s9 Y- f! h- W+ q1666084 CONCEPT_HDL        CORE          All user-defined properties are not listed in the Customize columns in Variant Editor* Q( h/ i" ]  Q
1667043 CONCEPT_HDL        CORE          Incorrect information in cpm.log file" U& k9 d' a5 ]. m- U+ \# E7 q
1670659 CONCEPT_HDL        CORE          SIGNAME text off grid when pasting copy using ctrl+v.
/ Y5 j3 b: `4 g9 d1697732 CONCEPT_HDL        CORE          Warning (SPCOCN-922): The object is being placed towards the left edge of the schematic. Ensure that the objects are pla: R( O+ H- s, z' w6 j
1697955 CONCEPT_HDL        CORE          Rename Signal places sig_name at an incorrect position for an unnamed net/ C! d$ o$ t' S; t6 d: i9 j  b
1711635 CONCEPT_HDL        CORE          The arrow keys do not work as expected in Windows mode
, z% `3 J# `  S( @: A1713091 CONCEPT_HDL        CORE          Difference in the behavior of 'Add Signal Name' in DE-HDL between releases 16.6 and 17.29 P  I* N7 Q6 D0 m. x+ S
1708820 CONCEPT_HDL        OTHER         In a board cache flow, component bodies are missing when importing another board cached flow project.
0 x' j5 _0 [0 J" F! v1639928 CONSTRAINT_MGR     CONCEPT_HDL   The '-filterFile' argument is not recognized when cmDiffUtility is run as a command line operation
& V& [& e8 @/ J& n$ O1657048 CONSTRAINT_MGR     CONCEPT_HDL   Unable to navigate through the search results in the CM Reports0 ^4 T4 \! z! U8 E- n
1718073 CONSTRAINT_MGR     CONCEPT_HDL   ECSet mapping errors on an upreved design in release 17.2: Pins in XNet and CSet do not match
/ g7 A, G3 Y( A# S& b4 n1717336 CONSTRAINT_MGR     DATABASE      Netclass members change during logic import; it's a toggle switch
1 |- c4 v* O( k8 M; A1 n1718514 CONSTRAINT_MGR     ECS_APPLY     Extracted topology does not use the PINUSE overrides specified on the canvas
# h; q- R1 l' F: N  \$ x1682885 CONSTRAINT_MGR     INTERACTIV    Constraint Manager worksheet switching does not work correctly in Linux! O( Q4 J+ X% |7 Y: s" ?0 p
1669523 CONSTRAINT_MGR     OTHER         Select is disabled in Constraint Manager when a command is active in PCB Editor
7 @# }" L7 p1 X  v1670802 CONSTRAINT_MGR     OTHER         Selecting a list of nets using the shift key does not work in Spacing and Physical domain- j, D+ ?1 e* ^. }8 a% s
1670922 CONSTRAINT_MGR     OTHER         Title of the Layer Remove window is Constraint Manager4 g- {4 ~& t7 N& D- h  ?) b4 T  H
1678235 CONSTRAINT_MGR     OTHER         Select option grayed out in Constraint Manager if a command is active in PCB Editor  b9 z6 @& i3 M( R4 r8 w
1680917 CONSTRAINT_MGR     OTHER         In release 17.2, nets cannot be selected in Constraint Manager when a PCB Editor command is active: w/ Z/ x- }( X' i$ e9 G
1691125 CONSTRAINT_MGR     OTHER         Highlight command no longer selects the net in CM
. U: k1 f( J+ \$ O" n* c1703791 CONSTRAINT_MGR     OTHER         Cross highlighting and assigning color to nets between PCB Editor and CM does not work- t7 V7 w; q( m( `4 i6 W, _4 w
1649603 CONSTRAINT_MGR     UI_FORMS      Expand and Collapse commands do not work when multiple objects are selected: ]0 J6 q' ]! c* o4 x* O
1654931 CONSTRAINT_MGR     UI_FORMS      Expand, collapse only works on one of the multiple selected objects.
* k$ t& g* ?3 I6 p) x$ K1 n9 G7 G! @1668794 CONSTRAINT_MGR     UI_FORMS      Incorrect via name shown when filtering via list/ L  h! Q- `+ G+ ~. X% P5 k
1678305 CONSTRAINT_MGR     UI_FORMS      Unable to use the CM worksheet customization (wcfx) from the CDS_SITE area. B  a* _4 u  I$ A% Q$ w' A9 _
1679909 CONSTRAINT_MGR     UI_FORMS      Incorrect layer order getting saved when defining BB vias in Constraint Manager PCSet: Z$ z  t3 _- o9 b8 E5 v/ p% n
1691906 CONSTRAINT_MGR     UI_FORMS      Display Issue: When you use the filters, the horizontal scroll bars are duplicated
' W$ R' S6 m0 Q: o. H$ |1677893 ECW                INTEGRATION   Integrations list update is not working as per scheduled time% T: o4 [1 T1 b
1652707 ECW                METRICS       Incorrect date and time displayed in mouseover tooltip on the Metric Trend chart8 b5 n2 S; e- M- C  y3 \& \
1654512 ECW                METRICS       Incorrect date and time displayed in mouseover tooltip on the Metric Trend chart
; G4 S& r1 r! A. C/ r* y8 `: r1668953 ECW                METRICS       IE11 Swedish only: Incorrect date and time displayed in mouseover tooltip on the Metric Trend chart
0 ]6 K' c, B1 v  ^( `) u: \$ U5 Y1677443 ECW                METRICS       Queued up metric packets on Pulse server are not processed if there are any packets related to a deleted project; P4 v1 C( ?2 E( N
1663676 F2B                PACKAGERXL    Physical net name (PNN) errors in the log file% k. l  m4 y% }, P+ }# R6 Z
1669583 GRE                DETAIL        AiDT always fails push when there is a connect shape attached to the cline being tuned
* V' k# ]# d# v9 x! i' A1686350 INSTALLATION       SPB           InstallDiagnose fails to repair some errors! m1 m! r8 r5 r% \$ _/ L; }
1672369 PCB_LIBRARIAN      EXPLORER      Cannot create a New library build in Library Explorer.
5 w# e" A. i6 h7 k" Q- G0 u1631034 PSPICE             ENVIRONMENT   When simulating the design in release 17.2, Capture crashes but works with release 16.65 K" q+ h' C: |/ H2 h, s. ?& Q
1648284 PSPICE             ENVIRONMENT   PSpice project crashes when a design is opened in release 17.2, T; l4 b; A. q; x% M5 W
1663336 PSPICE             MODELEDITOR   Ibis translation not supporting paths with spaces" g( Y- G( g, E- _2 b3 \
1679376 SIG_EXPLORER       OTHER         Topology created in OrCAD PCB SI license cannot be reopened with the same license' g7 S% `5 Y5 l
1666484 SIP_LAYOUT         CROSS_SECTION On converting a design from release 16.6 to release 17.2, a Dielectric thickness of ‘0.2032’ is added to another layer.
; {8 E3 Z9 ?9 o0 X. \1687988 SIP_LAYOUT         DIE_GENERATOR 'compose die from geometry' does not retain the user-defined padstack name9 g: q7 J7 k/ s3 x8 S- e0 `
1715016 SIP_LAYOUT         DIE_GENERATOR Using Die Text-In wizard to replace a die reconnects wire bonds to the wrong die in stack-up0 \* C& D: t( [! I
1620601 SIP_LAYOUT         MANUFACTURING Need the ability to create LINES with round end caps in the same way as the LINES appear in the database0 ?; t* l# k4 d6 v/ f
1705963 SIP_LAYOUT         PADSTACK_EDIT Pad Designer: "None" changing spontaneously into "Circle 0.000" in a pad stack definition and unable to save$ w1 r2 E: L6 v0 r# ?5 K( }
1713767 SIP_LAYOUT         REPORTS       Reports in release 17.2 for the Verilog Port Name are adding incorrect data that was not found in release 16.63 M; n; u2 W; Z
1696218 SIP_LAYOUT         SKILL         SiP Layout crashes on reassigning nets
) h  k. l2 k7 R2 {1695885 SIP_LAYOUT         UI_GENERAL    Visibility Tab check box: unchecked "All" disables access to "Shp" check box
3 j& }9 p( F( N- J4 m1639838 SIP_RF             DIEEXPORT     Enhance the error message, SIP-1507, to include that overlapping pins within tolerance are included during die export0 W$ c5 E) t* q3 D5 T
1653894 SIP_RF             DIEEXPORT     Redundant error message for die export, when view name is other than "layout"
; w6 w7 x( H# R0 g$ l1681332 SIP_RF             OTHER         Running die export causes Virtuoso to crash/ ]9 R5 x9 M: Y* P  E* ~7 P
1679336 SPECCTRA           LICENSING     Min/Max Propagation Delay cannot be routed by PCB Router using OrCAD PCB Designer Professional
& R( U, }9 g& r; j0 `( b) B) K& E# R& g
/ h! {6 O1 V. ]* j9 d
Fixed CCRs: SPB 17.2 HF015
2 _2 w3 Z2 |! Z4 o- @6 H5 J03-16-2017
6 B& I1 t' S8 y' e' }========================================================================================================================================================/ Z! e9 p! P5 w1 c
CCRID   Product            ProductLevel2 Title
9 J0 N. ?+ M+ Y; C" W* O========================================================================================================================================================
1 V" L- U1 u" P) J% t! p1653366 ALLEGRO_EDITOR     INTERFACES    Unable to attach step model to symbol) \, Y1 @9 h) {9 N
1671760 ALLEGRO_EDITOR     INTERFACES    Step package mapping window unable to display step model: N) }! Z2 w0 a
1706879 ALLEGRO_EDITOR     MANUFACT      Trace gets moved to dielectric layer after using the Gloss function
7 U  w6 W0 }* R! h" P' [1708685 ALLEGRO_EDITOR     MANUFACT      Incomplete ncdrill holes data in drl file$ G9 O1 t4 u- _4 }% q  I
1712057 ALLEGRO_EDITOR     PAD_EDITOR    Changing text size and restarting Padstack Editor results in incorrectly scaled forms1 V0 P" f2 h9 U& M
1709335 ALLEGRO_EDITOR     SCHEM_FTB     Cannot import netlist from attached design
! w3 Y. V! f* f! R1687329 ALLEGRO_EDITOR     SHAPE         Shape is not voiding uniformly when component is rotated in 30 degrees! |/ T8 n/ |$ M+ ]5 E
1698539 ALLEGRO_EDITOR     SHAPE         A thin shape is left when dv_fixfullcontact is enabled.
4 u* _+ V! [( m1620210 ALLEGRO_EDITOR     UI_GENERAL    Need to run PCB Editor from both 17.2-2016 and 16.6 releases simultaneously
+ g/ a% x% `4 p( D9 H3 {1687819 ALLEGRO_EDITOR     UI_GENERAL    Change in Region and Language settings of Windows impacts decimal character in Padstack Editor; @: |% z) [7 x  `3 U  {
1699326 ALLEGRO_EDITOR     UI_GENERAL    Padstack Editor follows the geographical area rules set in the Control Panel while PCB Editor does not9 D/ e6 }- A/ a1 V6 @
1711341 ALLEGRO_EDITOR     UI_GENERAL    Incorrect pad size in Padstack Editor when the German regional settings are used, V, B- Q1 s8 i8 P3 o
1712496 ALLEGRO_EDITOR     UI_GENERAL    Padstack Editor shows incorrect values when using comma and 3 decimal places
$ I* Y; j3 O6 r2 O/ I2 S* G1714744 ALLEGRO_EDITOR     UI_GENERAL    Using comma instead of dot as integer separator results in incorrect diameter value5 U' G/ b9 ^4 R- B
1715714 ALLEGRO_EDITOR     UI_GENERAL    If the 'Decimal places' field is set to 3, values in PAD Designer change automatically7 z2 F6 y4 q% i# U* n* W# b
1713292 APD                WIREBOND      Allegro Package Designer crashes when adding wire to a die pad
/ @) {" x& C  F+ N: G1710973 ASDA               PACKAGER      Unable to export Allegro SDA project to PCB Layout
7 Y8 k- l! D5 _* r  q9 D6 r4 \5 j3 z1698697 CONCEPT_HDL        COPY_PROJECT  Copy project corrupts the .dcf file
% i" a, A/ M. [) ^8 |3 v2 B, n1705401 CONCEPT_HDL        CORE          Alignment issues while pasting signal names in 16.6 Hotfix 084. I5 f( q7 T' m  i  Z1 \
1707116 CONCEPT_HDL        CORE          SIG_NAME is placed on non-grid position
; a, ^/ L5 s! ^- o1710486 CONCEPT_HDL        CORE          Rename Signal places sig_name at an incorrect position for an unnamed net
  R$ U: k+ ]% S3 M& i2 w# {0 k1667786 CONSTRAINT_MGR     XNET_DIFFPAIR Parts with NO_XNET_CONNECTION getting extracted into SigXplorer! e9 Q; ^$ Q) |
1709508 SIG_INTEGRITY      REPORTS       Allegro Sigrity SI crashes when running a reflection simulation) U7 H. U7 }1 `1 `. m; f) v
1710097 SIP_LAYOUT         DIE_STACK_EDI The IY option of the 'move and stretch wire' command moves the die to incorrect coordinates+ i8 N  c2 u" P6 w4 r
1712964 SIP_LAYOUT         SYMBOL        SiP Layout crashes when using Renumber Pins in Symbol Edit application mode' b8 ~7 f' W8 j- S3 C; y
  L: x* O1 [0 a2 m: |

; U( A6 H3 H4 N/ N/ m8 Q4 rFixed CCRs: SPB 17.2 HF014
5 R6 Y+ \1 T4 y3 }9 ?1 T- s; n03-4-2017
, r$ P, Z; O& b9 o- l========================================================================================================================================================& Q! O' H! ~8 V" h+ X* [* Z
CCRID   Product            ProductLevel2 Title8 N! ~$ R2 t9 Y" X! O
========================================================================================================================================================3 P! P3 c1 J8 e% j' o" M9 b; Z
1691828 ADW                COMPONENT_BRO Part Information Manager displays incorrect data related to attributes on relationships& _, ^2 c+ v1 e
1700963 ALLEGRO_EDITOR     DATABASE      Running the 'slide' command results in the cline segment losing connectivity0 a/ w6 b8 r9 \% |) G( V" [% P- w
1685502 ALLEGRO_EDITOR     INTERFACES    The Export - PDF command fails to export the TOP etch subclass with error code SPMHGE-268  U! M$ U! m) e1 M9 m
1644643 ALLEGRO_EDITOR     MANUFACT      The NC drill legend does not match the drill customization data- L5 \) K( I0 j0 u
1700557 ALLEGRO_EDITOR     MANUFACT      DXF output does not contain drill figure data
  v# ]4 ?6 o& ]5 c3 U3 ^1660252 ALLEGRO_EDITOR     NC            NC Drill file generated with errors
+ k  K( P1 j1 I: Q1677775 ALLEGRO_EDITOR     NC            Merging of drills not retained in database.5 X  n1 t. N+ t3 n9 q; N
1701554 ALLEGRO_EDITOR     SHAPE         Shape spacing clearance is not updated unless the shape vertex is deleted8 R$ E! R+ A+ k( W3 z, @# t
1704669 ALLEGRO_EDITOR     SHAPE         Route Keepin is not getting created at a specific location
2 k+ E9 Y( w" `% ?( V9 @3 d8 V, |" B1685995 ALLEGRO_EDITOR     SKILL         All film sequence numbers are returned as 0 when using the SKILL function axlGetParam
4 X2 ?4 ?8 ~# ~1 R# c) k1621336 ALLEGRO_EDITOR     UI_GENERAL    Changing the color visibility does not refresh the screen color immediately, p5 j1 J8 b/ L0 r& P3 c
1668817 ALLEGRO_EDITOR     UI_GENERAL    Changing the visibility or the color on the canvas in release 17.2-2016 takes longer than release 16.6) i/ p  p; r) |0 [1 N
1671268 ALLEGRO_EDITOR     UI_GENERAL    Visibility Window: There is a noticeable lag when enabling etch, via, and pin on a specific layer one by one7 L9 |- d  ?& j! ~4 o3 x
1690691 ALLEGRO_EDITOR     UI_GENERAL    Reports not generating if the 'allegro_html_qt' environment variable is disabled7 `/ x, e- x, T7 u
1709903 ALLEGRO_EDITOR     UI_GENERAL    Toggling layer visibility does not change the display until the mouse pointer is moved
/ k9 Q' Y$ N& i" d* O1647596 APD                EXPORT_DATA   Allegro Package Designer crashes when trying to export board-level components
8 ~+ P% c3 P5 m$ v4 q. ]/ d" T1688035 APD                OTHER         Significant difference seen in the percentage of metal between the Metal Usage reports of positive and negative layers# v2 B2 t' `& ]( r
1690777 CONCEPT_HDL        CHECKPLUS     Rules Checker returns an error when the value of the PACK_TYPE property is in lowercase
  v) g4 X" u2 |% v! T, k1695987 CONCEPT_HDL        CORE          $PN placement in DE-HDL during part development is not following mouse placement3 t9 C' R3 u6 L4 r7 z  D
1700873 CONCEPT_HDL        CORE          With duplicate part table files, running the Assign Power Pins command crashes DE-HDL without any message7 ~. b" l& A1 G- A7 l0 v
1702703 CONCEPT_HDL        CORE          Location of $PN in DE-HDL Symbol Editor is not as precise as it was in 17.2 Hotfix 011
6 e8 C1 n# v% v! y6 v* q2 z' d* w1705999 CONCEPT_HDL        CORE          Signal naming is not working correctly in SPB 17.2
) n4 N; h7 V5 P' a5 j& L1677489 CONCEPT_HDL        CREFER        CRefer points to incorrect page numbers when there are page mismatches in the logical and physical page numbers
, C' y1 I9 X% A# W( O1698259 CONSTRAINT_MGR     CONCEPT_HDL   Unstable $LOCATION property in release 17.2-2016
5 I! J6 ^. _' D! ~6 n) g1702537 CONSTRAINT_MGR     CONCEPT_HDL   ECSet mapping errors reported after removing the signal models on an upreved design
( h6 \0 k; d; n, u1703981 CONSTRAINT_MGR     TECHFILE      Importing a technology file (.tcf) results in packaging errors
& Z* u/ H% O- n7 e1673115 ECW                INTEGRATION   Import from external data sources (Integrations) truncates input values to 128 characters8 ]% D/ D3 f4 d
1699395 FSP                FPGA_SUPPORT  Selecting a QSF part name in the FPGA Properties window crashes FSP# O# c2 u: n6 u( e: w7 z
1704353 INSTALLATION       DOWNLOAD_MGR  Selecting 'View' in Download Manager results in error, 'Object Reference not set to an instance of an object'
1 R# t: r3 X3 }- G4 }1705265 INSTALLATION       DOWNLOAD_MGR  Problem installing OrCAD Library Builder from Download Manager
, @( Q0 B. P) Q9 O2 W) p. l1646635 PDN_ANALYSIS       PCB_PI        PCB Editor uses 'powerdc.exe' to launch PowerDC instead of the 'powerdc' script
; g  r5 V7 R, ]9 M
* C' I: r1 o( s, b, f9 W, i3 }/ e1 \
Fixed CCRs: SPB 17.2 HF013
3 |# }, y9 x5 ?' Y* a02-17-2017# ~& Y3 ?* Z% |
========================================================================================================================================================& O& O3 g8 g5 q" D  [
CCRID   Product            ProductLevel2 Title) C! F3 ?$ s. D  g6 h9 K
========================================================================================================================================================
4 M: z. s0 L& D9 e* j8 O1567741 ADW                COMPONENT_BRO The PPL_list never gets read when using a saveconf.ctr located in the global site.cpm
: `8 r9 x. |+ h& k+ |4 m2 `- L1697109 ALLEGRO_EDITOR     ARTWORK       Artwork not showing padstacks for the soldermask layer& Z; l3 e7 p1 U& |  w. M
1682297 ALLEGRO_EDITOR     DATABASE      Derived padstack and associated padshapes not updated when design is upreved for compatibility with the current version
# q: }/ V' @6 b1697309 ALLEGRO_EDITOR     DATABASE      PCB Editor 17.2 uprev changes NC pins from non-plated to plated
) Z3 R0 @' W# V/ ~; d+ e1698624 ALLEGRO_EDITOR     DATABASE      Opening 16.6 board in 17.2 converts non-plated holes to plated0 i, r) m, {: f/ r
1697092 ALLEGRO_EDITOR     OTHER         axlDBViaStack crashes PCB Editor session and corrupts the board
+ a# e9 `8 q  a; t3 {# V7 K1687819 ALLEGRO_EDITOR     UI_GENERAL    Change in Region and Language settings of Windows impacts decimal character in Padstack Editor+ \7 Q% X! ~1 S3 P" F$ Z! B& |6 G
1696637 ALLEGRO_EDITOR     UI_GENERAL    Padstack Editor uses Region and Language settings for the decimal symbol) e! w. s8 g- g: {& \
1699326 ALLEGRO_EDITOR     UI_GENERAL    Padstack Editor follows the geographical area rules set in the Control Panel while PCB Editor does not( {+ j' {5 l( O  M( H
1616138 ALTM_TRANSLATOR    PCB_EDITOR    Board file imported from third-party tool to PCB Editor has the shapes but not the components, N- ^+ ]! Y0 n! m4 ]3 q  U
1666020 ALTM_TRANSLATOR    PCB_EDITOR    Board converted from a third-party tool to PCB Editor has missing components
$ |$ [% l1 Y' v3 i0 b: z! M# u$ d1690448 CAPTURE            CORRUPT_DESIG Corrupt design: nets in this design are not displayed when running Edit - Browse - Nets
* ~4 }2 _0 k7 Q) l" S% z8 z1690455 CAPTURE            CORRUPT_DESIG Corrupt design: all the nets in this design are not displayed when running Edit - Browse - Nets
. _( v7 e) z* \1684180 CONCEPT_HDL        CORE          Message should indicate that the user needs to reload the design after setting SET STICKY_OFF( \$ ~. ^/ T+ S. Z
1695987 CONCEPT_HDL        CORE          $PN placement in DE-HDL during part development is not following mouse placement
* D3 n3 {# Z3 K9 h4 q1688287 CONSTRAINT_MGR     DATABASE      PCB Editor crashing while adding a net to a net group.
" z# V& {4 M# z1675013 ORBITIO            ALLEGRO_SIP_I Failed to import brd file
! ]$ U  r0 C& H8 v5 R1698968 SIP_LAYOUT         3D_VIEWER     3D viewer shows keepin and not design outline.
4 [2 k7 T% @* X" I; r1699884 SIP_LAYOUT         ASSY_RULE_CHE SiP Layout crashes on using Assembly Rules Checker
2 ?- C5 o& y2 I( }: m1689969 SIP_LAYOUT         DIE_EDITOR    SiP Layout crashes when moving dies using relative coordinates/ u! E% {8 t9 [( x* O2 q
1696239 SIP_LAYOUT         DIE_EDITOR    When using the Die-stack Editor to move and stretch wires, SiP Layout crashes0 C8 n$ p1 G  i8 h9 Y* e
1695372 SIP_LAYOUT         REPORTS       Running the Metal Usage reports fails on the Primary side.
+ o" f( @" k" n, B, y
. E+ E$ q) F$ w5 `9 {% y2 d5 k0 q: Y" ?" F4 a
Fixed CCRs: SPB 17.2 HF012
0 U: b" r: y; J. `: V1 e02-3-2017: h% Z: z& K8 @2 s% y4 g' O
===================================================================================================================================
* W# x2 p# g) y- e$ U2 O' yCCRID   PRODUCT        PRODUCTLEVEL2   TITLE4 w; \2 d. C7 M: C+ C2 E0 m4 m+ e
===================================================================================================================================
9 ^; i' q# m' T, C1659641 ADW            FLOW_MGR         Documentation Editor does not invoke when a .brd file is opened from EDM Flow Manager
) g4 r' `+ x/ S9 c- `1661632 CONCEPT_HDL    OTHER            Page skipped in DE-HDL when navigating using the Page Up and Page Down keys2 r- T3 o+ Y$ s' v& t; H. }" o
1668325 ALLEGRO_EDITOR SHAPE            Updating shapes to smooth creates erratic voids.
. ^5 w2 e* L7 }' O) H% D' f1670082 CONSTRAINT_MGR ANALYSIS         Inconsistency in Constraint Analysis Modes - Electrical in OrCAD PCB Designer Professional 17.25 T. `5 y; q1 Z7 R4 K" t
1674231 ECW            METRICS          Re-upload for local metric packets that failed on first attempt is not working when Pulse server name contains dots' t0 d$ i/ [; z( J
1674338 APD            SHAPE            Shape is not clearing slivers that are smaller than the 'Minimum aperture for gap width' of '18 um'& V' ?3 a. O3 [3 o$ O; u3 d
1675677 ADW            DBEDITOR         DBeditor Issue-Searching by using the Properties method" F2 Z; Z8 x7 g  P, g
1677489 CONCEPT_HDL    CREFER           CRefer points to incorrect page numbers when there are page mismatches in the logical and physical page numbers
8 U, a# Q* E2 z: p1679351 ALLEGRO_EDITOR REPORTS          Missing Fillets Report is not showing missing fillets on the bottom layer
: Y1 W: ^+ Y. J: K6 w1681002 ALLEGRO_EDITOR OTHER            17.2 STEP output fails to produce an output similar to 16.66 N+ i& _/ b3 N: B: n6 L
1682287 ALLEGRO_EDITOR EDIT_ETCH        Auto-interactive Delay tune (AiDT) rips lines that have been routed" T! `$ t; v; K1 Y; I) I0 Y2 }
1682900 ALLEGRO_EDITOR PLACEMENT        Moving a symbol by snapping to segment vertex with 17.2 Hotfix 009 crashes PCB Editor
0 c. M$ E6 l7 [  H! q1684117 CONCEPT_HDL    CONSTRAINT_MGR   Property deleted from Constraint Manager is not getting updated in the DE-HDL canvas3 z  X* O1 O. V# d+ K
1686803 ALLEGRO_EDITOR INTERFACES       PCB Editor crashes if the 'ipc2581_group_drills' variable is set.2 }3 Y% Q" ~7 i/ x# }
1687816 ALLEGRO_EDITOR PLOTTING         Export PDF Vector text option does not work
" Q# B; V4 O" |1688287 CONSTRAINT_MGR DATABASE         PCB Editor crashing while adding a net to a net group.
2 E4 `- T6 }; z1689881 ALLEGRO_EDITOR DFA              Record and replay script for loading DFA spreadsheet not working+ @; C: ~8 F/ }3 q/ P; k
1690958 ALLEGRO_EDITOR SKILL            SKILL command axlDBDelLock is not working as explained in the documentation0 Z0 D% O5 ?# o$ @! `
1692166 APD            DATABASE         DB Doctor returns 'ERROR(SPMHDB-252): A corrupt database pointer was detected' for a specific design
4 Y9 O) b4 e, z: P1693431 ALLEGRO_EDITOR SKILL            Running axlXSectionModify and axlXSectionSet results in warnings and corrupts multi-zone cross-section
% [/ A6 J+ B2 G4 _1693719 ALLEGRO_EDITOR MANUFACT         Incorrect suppressed holes information in the drill file created
! C; B# Z/ g! ]' r( L1693846 ALLEGRO_EDITOR MANUFACT         PCB Editor crashes when running the gloss command: ], p6 V0 ^  ]% N2 [
1694151 CONCEPT_HDL    CORE             Rename Signal for unnamed net added the sig_name at the incorrect position with small text size.
6 u; L% T/ c9 _: i1694867 ALLEGRO_EDITOR SHAPE            Void is deleted by the shape merge command
5 K+ Y8 I  Z% @* A1695131 ALLEGRO_EDITOR SKILL            PCB Editor crashes when using the axlSpreadsheetDefineCell SKILL function3 F2 I  V5 ^$ w4 |* J

3 ^! B0 n! S" F, M( U2 b1 I/ z  S/ E  d( x' a! v
Fixed CCRs: SPB 17.2 HF011
3 w: {5 |0 V  v; ~01-20-2017* f% ?/ i0 w7 p6 E
===================================================================================================================================
: N" L2 t0 l9 G2 l* dCCRID   PRODUCT        PRODUCTLEVEL2   TITLE
! u$ c2 t" P5 G3 i3 V===================================================================================================================================
- d, X% K# p3 @9 L( |. L' Z2 |1618986 CONCEPT_HDL    CORE             Information required about the DONT_FORCE_ORIGIN_ONGRID directive& H: @2 g( ^$ e8 l4 I5 k
1629696 PSPICE         PROBE            After successfully exporting traces to csv, PSpice crashes on a subsequent attempt to export traces( _# b. X2 `8 }6 I- Z
1667213 CAPTURE        NETLIST_ALLEGRO  Tools - Create Netlist stops responding on Windows10
# S7 K4 P0 K8 T% o& [8 e$ L1667599 APD            OTHER            Wire Bond operations taking longer than expected to complete: y( @) B9 U3 e2 Y
1667678 MODEL_EDITOR   PARSE            Signal model assignment creates ESpice models that do not pass Model Integrity checks) x$ _' h2 A2 D# [4 J
1670120 ALLEGRO_EDITOR UI_GENERAL       In 17.2, the Static Phase meter shows up in the middle of the screen instead of the lower right corner
. o0 z9 Q7 z, _" r2 L8 g9 \1670927 ALLEGRO_EDITOR DRAFTING         Using zcopy to create a Route Keepin results in database errors) n$ G& z! y# d  H
1675359 ALLEGRO_EDITOR ARTWORK          Subclass ETCH/WIRE is added to artwork definition though the visibility of 'ALL Layers' is turned off/ l4 O4 @& W6 p9 F( I% Q; g- ~4 Z  R
1675619 ALLEGRO_EDITOR MANUFACT         Differences observed in IPC-D-356A between releases 16.6 and 17.2
7 {0 \  U) m2 l7 x, [1676161 ADW            FLOW_MGR         Opening a project in SPB 17.2 flags the 'Operation load JNI code failed' error4 t6 d$ Y7 I/ ]: z1 N% ^& \  B
1677405 CONCEPT_HDL    OTHER            When moving a wire with a dot, the dot is not removed directly! G2 l& ^2 v# ^$ y, a+ s3 x
1678061 PSPICE         SLPS             Simulating an SLPS co-simulation with a Fixed-step solver with a value smaller than 1E-4 results in a crash
2 o, j0 @% |8 @1679347 PSPICE         SLPS             SLPS crashes when co-simulating without opening OrCAD Capture or PSpice
# \! a2 k8 R* D5 {" j4 A1680113 ALLEGRO_EDITOR SHAPE            Irregular void created on dynamic shapes
, Y9 O+ L, @+ [( v& q7 R/ n! ?" A1680802 ALLEGRO_EDITOR DATABASE         A 16.3 database locked with disabled export of design data should be view only in 16.6
% y- u* k5 H- L  y, l1681129 ALLEGRO_EDITOR DATABASE         Match Groups in the DE-HDL design are not getting transferred to the board file  w- e/ J4 m8 y1 |4 n2 ]+ p
1681514 ALLEGRO_EDITOR UI_GENERAL       Opening the Dynamic Shapes State report hangs PCB Editor in 17.2 Hotfix 009# e% u& _* \, m0 g
1681727 CAPTURE        NETGROUPS        In 17.2, Capture crashes when closing a design that has assigned Netgroups# \2 i' |( w; e7 q8 G
1682297 ALLEGRO_EDITOR DATABASE         Derived padstack and associated padshapes not updated when design is upreved for compatibility with the current version
' t( B% U, y) ^1682447 CONSTRAINT_MGR CONCEPT_HDL      Extraction issue on differential pairs in the given design  d2 |# }& o" y6 N3 _
1682454 CONSTRAINT_MGR CONCEPT_HDL      Design with NO_XNET_CONNECTION property on parts is exported to PCB Editor; many other components get the property; [) c8 p! r0 [/ X2 R. {
1682469 CONSTRAINT_MGR CONCEPT_HDL      Creating a CSet from an existing CSet leads to invalid CSet names in Constraint Manager connected to DE-HDL
& ]" G% e  n; J+ N7 l1 t5 r# {1683919 ECW            TDO-SHAREPOINT   Site Minder integration for login from TDA not working after SSL certificate update3 l. T2 F  }+ g- ]
1684111 ALLEGRO_EDITOR SHAPE            Dynamic Shape not voiding overlapped static shape
( A; M7 @6 M3 W1684508 ALLEGRO_EDITOR AUTOVOID         Allegro PCB Editor stops responding when deleting a via
: ?, ~( s) ^% T4 y5 x1685540 ALLEGRO_EDITOR OTHER            If text is attached to an object, the object is also printed in the PDF
5 c7 W! L5 @: _0 F- M8 ]+ y9 ?! U1685810 ALLEGRO_EDITOR PAD_EDITOR       In 17.2, Padstack Editor does not save adjacent layer information for BOTTOM pads
' U0 ^, X' r/ D% \/ ?1685986 ALLEGRO_EDITOR PADS_IN          PADS Translator-generated output shows incorrect unit for the soldermask oversize option
9 g; @  |0 F# A! q3 h2 j1686127 ALLEGRO_EDITOR SHAPE            The void of shape missed in artwork.. `, `# o- p* u
1686791 ALLEGRO_EDITOR OTHER            Searchable property unavailable on bottom layer pins in the generated PDF7 g( \9 M9 n& ]+ t$ M

" r0 ?2 P/ S5 R& r# k$ [( t, m( {4 ^9 F  x+ y! b
Fixed CCRs: SPB 17.2 HF010
5 D# \( p4 s# Y2 |01-6-2017
/ }( E) F: c* I* e4 @" X% m===================================================================================================================================4 _$ W; H; Z1 M/ u- I' b; ~
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
8 I- ?3 k8 Z4 w, Z" j, h===================================================================================================================================( w3 F. Q7 d% i1 P6 _
1524700 F2B            DESIGNVARI       Variant file cannot be loaded
, Y1 ^1 ]) P8 R% }1597787 CONCEPT_HDL    MARKERS          Save As in Marker dialog causes DE-HDL to crash( }5 H! P# b: R7 u3 W7 ?
1599843 CONCEPT_HDL    INTERFACE_DESIGN Moving NG causes extra elements added to it to move
% V9 A# X; s% o8 v  |6 I: ^& z1620017 F2B            PACKAGERXL       Packager Fails with ERROR(SPCOPK-1053) when $PART_NUMBER property for components has a value
2 s! O! U1 R7 N5 w& q" q8 |6 w" J! b1632977 CONCEPT_HDL    INTERFACE_DESIGN Connectivity error when moving NG members) i, F  D/ O: Y: i  ?
1635941 ALLEGRO_EDITOR INTERFACES       Shape created by IPC 2581 for negative film is not same as the shape on board$ n# S2 b+ \) W  F6 n
1656357 CONCEPT_HDL    CORE             Pasting a signal name across pages causes the name to overlap with the wire segment+ G/ x( S7 v/ v- ?7 d, J* p
1657346 CONCEPT_HDL    PDF              Wire Pattern set to two-dot chain line in a schematic appears as a solid line in the PDF output3 U* e; {" t* ^0 w# P2 d; B: J& F- M
1658048 ALLEGRO_EDITOR COLOR            color_lastgroup is not working in SPB 17.2# q9 n7 Q; d6 h; ?
1658874 CONCEPT_HDL    CORE             'Insert (n) Pages' command does not work when the CONFIRM_WRITE directive is ON$ d$ d2 ^! S. m+ A
1659030 RF_PCB         LIBRARY          Offset is not calculated from the center if using negative values for input pins when placing MSOP symbols
. t+ c0 Z" e. N5 M) b  c8 L1659097 CONCEPT_HDL    CORE             Mouse stroke fails to be enabled on startup with left mouse button (LMB)  b! A' z6 V- W  b" b
1659532 CONCEPT_HDL    CORE             About Import Design command with the CONFIRM_WRITE directive
- m, J4 m4 G- ~! X% }1659929 CONSTRAINT_MGR UI_FORMS         Using wildcards in filename for Import Constraints does not work in 17.2) c2 G# g* I6 k2 H
1660200 ALLEGRO_EDITOR UI_GENERAL       Move by Sym Pin # edit box is obfuscated
. F% I' [* R% i' `4 |5 N1662821 ALLEGRO_EDITOR OTHER            Cross section chart does not show stack vias in 17.23 R8 T( `9 w6 C' X1 Q% y0 c5 _
1663641 CONCEPT_HDL    COPY_PROJECT     File - Copy Project in Project Manager creates two designs if there are dashes in the design name8 b- t# ]+ p9 d7 n' C
1665652 ALLEGRO_EDITOR SHAPE            Critical fillet and shape issues in 17.2
2 ~3 _# N* N8 _: ^& V$ Q1665918 CONCEPT_HDL    CHECKPLUS        Error (100) Program Internal Error 'Create_flat_node' with checkplus run
* j/ L( E0 L0 g' j$ Q, p* L1667056 ASI_PI         GUI              Power Feasibility Editor does not list capacitors connected to selected nets/parts
  r. r" }/ l( b' |7 n" H1668137 ALLEGRO_EDITOR SCRIPTS          PCB Editor crashing when running Script Replay( N- w3 |( y+ ~+ R- [* a7 ~: O
1669651 CONCEPT_HDL    CREFER           CreferHDL values are invisible6 J- i* G/ |2 ?% U4 i
1669707 CONCEPT_HDL    CORE             Pin numbers not visible on the canvas after replacing a part with the same symbol but a different part property' S# E) _1 |7 e  u. T4 [- s) H
1670339 ALLEGRO_EDITOR OTHER            Small shapes defined on the mechanical symbol Board Geometry - Outline are not converted to the Cutout subclass.$ c. c' ^3 W3 d) y
1670564 ALLEGRO_EDITOR MANUFACT         Exported Gerber file cannot be imported in brd
& E  ~7 t" [* K* D* }" p" [' j9 y( l1670687 ALLEGRO_EDITOR NC               nclegend.log reports missing columns which are present in the NC Legend
0 X/ H5 ~( e# D7 n) C& b1670811 PSPICE         AA_MC            AA MC Plot settings options
+ p- u. G6 a( p6 c# E/ G1671428 ALLEGRO_EDITOR UI_FORMS         Display origin checkbox position changes in Step Mapping dialog
" y- k0 S; w2 P' \, ~. i: t4 {; {0 y1671728 CONCEPT_HDL    CORE             Option requested to reload preferred_projects.txt without re-opening DE-HDL3 O1 o3 o- Y6 {" U
1671901 ALLEGRO_EDITOR UI_GENERAL       Toolbar and menus are locked or greyed out
$ Y* d2 L- O2 u1672477 ALLEGRO_EDITOR DRC_CONSTR       DRC generated by Dynamic fillets0 Z! p$ r& }/ Z& |+ V  w
1673499 ALLEGRO_EDITOR DATABASE         Drill table title issues of backdrill designs in 17.29 n" N/ a7 S5 z
1673681 ALLEGRO_EDITOR UI_GENERAL       F1 for Help not working in PCB Editor 17.2
1 U3 C3 j$ ]( d& p+ I1675499 ALLEGRO_EDITOR DATABASE         Running the Gloss command causes PCB Editor to crash...
1 O( N; ]+ o9 h2 `+ I1676480 ALLEGRO_EDITOR MANUFACT         Creating Variant Assy_Bot Drawing showing Variant Assy Top Drawing2 @. d6 A1 W7 n, Y( L* U
1677431 ALLEGRO_EDITOR DATABASE         Get ERROR(SPMHA1-141): Invalid sector row. Contact cadence customer support when opening DRA File' b' ?' F  K  F* f
1677651 CONSTRAINT_MGR CONCEPT_HDL      DE-HDL crash on design after successful packaging2 _0 X/ v/ [6 A, S( `! _" m! A  p2 p
1677672 CONCEPT_HDL    CORE             Whitespaces in URL links are not resolved correctly on Linux with Firefox
( P) \/ o/ D- C# j; Z' c7 D1680837 ALLEGRO_EDITOR SHAPE            Updating the shape makes the shape disconnect from Thru pins of same net" m8 b- E' l* ^' A
1681059 ALLEGRO_EDITOR SHAPE            Shape Voiding using DV_SQUARECORNERS environmental variable does not always produce voids with square corners.0 T- e3 N& w2 T, ~4 j
1682312 SIG_INTEGRITY  LICENSING        Allegro Sigrity SI/PI Product Choices window is blank after installing 17.2-s009 hotfix+ Z- K7 u+ |" U( _
! P! S+ W- [! r  O- V
  I* W3 n( x$ M* m. G( G
Fixed CCRs: SPB 17.2 HF009
1 {, C* ~7 M7 l' J. |/ ^! |- O12-8-2016
6 @7 c! I, N# F' s; m2 y===================================================================================================================================9 y( l. y8 _$ R2 m' F' K( h' Y
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE6 s% ?* a7 ~6 E" |4 c
===================================================================================================================================& h) |% ~/ |0 e" ]  E5 [' ^
1212577 PSPICE         MODELEDITOR      IBIS translation fails without any information in log file$ Z! ?% j! }) u+ y: L! p
1311687 PSPICE         MODELEDITOR      Timeout error while translating IBIS model
' s) {; O- n" _- w1327174 PSPICE         MODELEDITOR      Log file should list error details during IBIS Translation: s% F9 j- l, U1 o2 I
1499665 ALLEGRO_EDITOR INTERACTIV       Offset Move depends on move setting.
0 _' X; V1 ^1 x  W1516093 ALLEGRO_EDITOR PADS_IN          Pads library translator does not translate slot orientation
3 R2 W' k" S1 }7 b& d- t$ F1565795 ALLEGRO_EDITOR UI_GENERAL       Search does not work in the Defined Variables window; {- ?8 g3 l+ `
1568817 ALLEGRO_EDITOR UI_GENERAL       Padstack editor not accepting comma as decimal separator with system locale set as LANG ru_RU.UTF-8* ]8 S( b% X4 k* D- F2 B4 q# l$ c( q
1569272 ALLEGRO_EDITOR PLACEMENT        Get the error message 'E- (SPMHDB-394): Placement cannot be completed ... 'after creating Place Replicate circuit
$ t, m' P) V! \0 H0 K9 c" {' M# o1577379 CONCEPT_HDL    CORE             Packager-XL gives different results when run from DE-HDL and ADW Flow Manager
# Y" n( u( b! G1578523 ALLEGRO_EDITOR PAD_EDITOR       Library Padstack Browser does not refresh preview8 \9 M0 f8 |' y* o
1578533 ALLEGRO_EDITOR PAD_EDITOR       New Padstack Editor does not automatically update the geometry
+ `3 D0 C" g: i+ x$ N1581129 CONSTRAINT_MGR UI_FORMS         Unable to dock the Electrical worksheet in Constraint Manager! B. H( [& p6 r7 g
1582103 ALLEGRO_EDITOR PADS_IN          PADS Library Import creates additional filled shape not present in source data3 J; Q9 `8 A4 Y7 [5 V: F8 I  K4 U& `
1591027 ADW            LIBDISTRIBUTION  Library Distribution redistributes previously distributed models. v; }! F' V& R% {! z5 C
1592026 CIS            VIEW_DATABASE_PA View database part does not work from schematic pages of an externally referenced design
3 Q  `5 u: `9 z4 s% a, h1593389 CAPTURE        GEN_BOM          Include files in Tools - BOM not working: {( ]; ~$ {" J, d0 Y
1593404 SIP_LAYOUT     EDIT_ETCH        Slide command moves via toward the object1 _$ e" y! m+ j# D1 T" j
1595872 CIS            PART_MANAGER     Capture CIS Part Manager PCB Footprint update case-sensitivity issue
1 u3 o8 z! T2 [" \1596955 ALLEGRO_EDITOR EDIT_ETCH        Scribble mode is not working as per expectation.& U' w7 ~" k! r6 {& o  O
1600936 ALLEGRO_EDITOR INTERACTIV       Pin DataTips differ between 16.6 and 17.29 `2 B" V7 z: p
1605961 ALLEGRO_EDITOR COLOR            Wildcards not working in the Filter Nets field of the Color Dialog window5 a1 T) P/ ]' ^) x  h7 i7 j
1606392 ALLEGRO_EDITOR PLACEMENT        Filmmask not shown when component is attached to cursor
5 F$ h8 H4 T. e1607016 ADW            TDA              TDO crashes after LRM update during check-in hierarchy) A! ?- G/ k6 L+ ?2 B. J+ u
1608059 CONCEPT_HDL    CREFER           Removing crefs from top-level design also removes .csb files from lower-level blocks
; @8 `. m& S/ w7 k# O$ Z1608278 CAPTURE        OTHER            Crystal Reports: User is prompted for ODBC password to create a BOM report
1 t+ R2 i( ~! c9 `1610377 CAPTURE        PROPERTY_EDITOR  Discrepancies between the NET_SPACING_TYPE property (or any other property) text and the actual property/ _) J- ^( x$ @* [1 g
1610456 ALLEGRO_EDITOR DATABASE         Strip design and selecting user defined subclasses results in database corruption.7 G0 X) }! H9 F1 E2 a* y
1612793 CONCEPT_HDL    OTHER            Pattern-based auto-distribution of split symbols not working if there are spaces before commas
* P; `0 T8 ^4 J; ~( z1613442 CONCEPT_HDL    CORE             Signal names are not horizontally centered when the wires are added using different methods9 e9 y$ P6 t' ]  H& {& K
1613559 ASDA           IMPORT_DEHDL_SHE custom variables from the BOM Tables are not getting imported% J: F2 y! T2 a3 |/ {: m0 t% A
1614093 CONCEPT_HDL    CORE             Import Design window has artificial 64 char limit for path - prevents access to some locations$ k& p5 [2 j4 D" V! m4 V
1614372 CONCEPT_HDL    EDIF300          OFFPAGE symbol is exported as PageBorder in EDIF300 schematic$ V, B9 C+ N1 L7 a
1615075 APD            LOGIC            Netlist-In wizard fails to import the net names, but gives a successful completion Info message0 t# v& S6 y3 |9 v1 R# @( @' k
1616131 ALLEGRO_EDITOR PLACEMENT        While placing a module, the Mirror command in the right-click pop-up menu is not working) `6 R; w7 P! T# O* ]9 Q
1617377 ALLEGRO_EDITOR UI_GENERAL       Visibility pane does not retain the correct layer view( }5 R5 f1 y# S8 {" z
1617404 ALLEGRO_EDITOR UI_GENERAL       axlUIMenuChange does not work as expected in 17.2. V! ^/ R! n& W5 z# Q1 z
1619412 ALLEGRO_EDITOR INTERACTIV       Script to create new padstacks from existing padstack is putting in wrong values for a regular pad
4 Q1 s. _& \+ |: T) f; }3 `0 {: [8 ^3 ]1621842 ALLEGRO_EDITOR PLACEMENT        mechanical symbol without placebound will not place in QuickPlace
3 h  p7 q5 p/ U6 M8 t1621874 ASDA           PRINT            Print - Save as PDF uses the default printer options only1 w( `6 h$ A' S9 W9 `& O
1621887 ALLEGRO_EDITOR INTERACTIV       Getting a 'Could not satisfy the snap condition' message when using the Snap pick to option0 f, K+ r4 Z5 \4 w5 n
1622680 ALLEGRO_EDITOR PADS_IN          Import PADS fails with the 'ERROR: *NET* section found. Translation of netlist is not allowed.' message
" ?5 G' d! n5 P. F5 S6 s) p' v8 w1623832 ADW            COMPONENT_BROWSE Incorrect part placement on schematic in Design Entry HDL 16.6-S073
5 a9 H) f0 D. f/ n: _1624813 CAPTURE        GENERAL          The Value property is always left aligned when placing a symbol on the schematic
4 E2 D& s3 q- a* r4 F/ r1624953 ALLEGRO_EDITOR UI_GENERAL       Custom views in 17.2 do not return to original, w3 r: _* A1 }" m2 L/ |
1625000 ASDA           CANVAS_EDIT      File - Save Project does not provide any indication of saving or progress bar
( Q2 H) P" k$ o2 Q7 d! W! u1625163 CONSTRAINT_MGR OTHER            There is no status for the analyze command in the Constraint Manager in 17.2
  l& c9 L1 Z+ r$ p+ W$ z% D! v1626647 PSPICE         ENVIRONMENT      Capture crashes when loading a design with two hyphens in sim profile name
2 e) j& J8 q4 o  N9 ~1628357 CONSTRAINT_MGR OTHER            Constraint Manager shows differences if exporting and importing constraints on the same board.
, n# _, R) Q( u( x9 e" f2 g1628409 ALLEGRO_EDITOR PAD_EDITOR       Pad Stack Editor does not remember last used directory
# P+ X0 g. H- M( m1631443 CONCEPT_HDL    ERCDX            ERC reports warning due to lower-case value of some properties in chips.prt- I: z) D$ Z0 r
1632195 SCM            OTHER            'No known page border found' error in cref.log
1 R0 C& L, ]7 O% J" o" Z' X0 s1632365 CONSTRAINT_MGR OTHER            Select command is disabled in the right-click pop-up menu from Constraint Manager in SPB 17.2
8 G' m, q) k/ B! v- o, E; u  y7 N1632462 ALLEGRO_EDITOR 3D_CANVAS        3D View (new) and PCB Editor crash when checking collisions
- r, u  }8 h" [- {- z9 C1632590 ALLEGRO_EDITOR 3D_CANVAS        PCB Editor crashes when 3D View is open and more 16.6 boards are opened
" N$ I( I# _4 M  w* F$ W' l- F6 R1633433 CONSTRAINT_MGR UI_FORMS         Expand - Collapse feature for multiple objects not working correctly
" M5 c: b( N- _% n1633454 ADW            TDA              TDO crashes if DAO throws an exception; |3 i" E& v8 K* |7 W- u$ i/ J
1633526 PSPICE         AA_PPLOT         Spaces in Simulation Profile cause error in Parametric Plotter; P+ i# [: r3 U0 x
1633608 ALLEGRO_EDITOR COLOR            'Retain objects custom color' should not enabled as default.- v4 h( ]8 w) O/ q
1636216 ALLEGRO_EDITOR 3D_CANVAS        Interactive 3D canvas (Unsupported prototype) is not mapping step model when assigned to device% f) Y, x3 P$ i. m6 h
1636899 ALLEGRO_EDITOR 3D_CANVAS        The new 3D Viewer is not taking the Package Height set on the PLACE_BOUND layer into account when displaying it.
7 {) n& I; E4 }6 _9 S! c7 t2 V1638185 CAPTURE        DATABASE         Opening CIS database locks all part libraries none of which are open
1 A* o! X: a  H' F4 l0 {& d8 G1639409 ASDA           CANVAS_EDIT      Handling of MAKE_BASE property from DE-HDL designs imported into SDA
/ @& k, I, `8 M2 z- r1639541 CONSTRAINT_MGR OTHER            PCB Editor 17.2 crashes when making changes in Constraint Manager4 L; d5 }, F% @0 I4 B' I& o. f; M0 y9 |
1639613 APD            STREAM_IF        The stream out command has created sharp angles in the GDSII output file- x1 X* m. g, N" @
1640061 ASDA           HIERARCHY        Incorrect message received when invalid characters are specified for subdesign suffix& z- |+ a/ d/ Y* O3 h; b( ~
1641118 F2B            DESIGNVARI       Some DNI parts are not identified in the variant view due to the BLOCK4 l6 J6 x7 }4 I& R$ j0 R0 p: s
1641410 ASDA           CONSTRAINT_MANAG No errors or issues reported when incorrect topology is applied to a net or an Xnet+ q) d$ _0 M2 V- G8 \
1642891 CONSTRAINT_MGR CONCEPT_HDL      DE-HDL crashes randomly while working on Constraint Manager
! x, U5 D2 N1 m' S+ }( w! w2 l' K1643003 CAPTURE        PROJECT_MANAGER  Start page shows latest as S004 after installing S005
" E+ A3 \) i: `& |1643532 ALLEGRO_EDITOR OTHER            Strip design command fails to delete symbol text in the attached design
$ C# L2 S6 x2 X( t/ s1645529 ASDA           CONSTRAINT_MANAG Unable to delete the diff pair from the nets
3 Y0 C; e9 h. K1645639 CONSTRAINT_MGR CONCEPT_HDL      DE-HDL crashes when the XNET_PINS property value has a trailing comma character
# H& `3 A$ y0 T* D2 _. }, C" Q1646354 CONSTRAINT_MGR CONCEPT_HDL      Cannot select Design Instance/Block Filter from the View menu in Constraint Manager0 Y# u8 d1 @( g1 o3 ]) t5 a
1646612 PCB_LIBRARIAN  CORE             Generate Symbol option crashes Part Developer# i- `, u& Q# ?/ u. _$ L( v
1646932 ALLEGRO_EDITOR MANUFACT         Manufacture - Auto Rename Refdes keeps defaulting to Use Default Grid even if another is chosen
8 L$ R3 I, L% f; i* K& V, M1647190 APD            REPORTS          'Sorted by Bond Finger' report shows incorrect wire bond connection
$ S" |5 G" ^, h: \# u2 f1647673 ASDA           EXPORT_PCB       Two Physical folders are seen after installation of QIR( l, ~  Q* Y3 r  N, v* V
1647729 ALLEGRO_EDITOR SKILL            axlFillet returns t when fillet is not added.2 K+ r, v- t2 ]+ }
1647779 CONSTRAINT_MGR OTHER            'Software Version' in the cmDiffUtility viewer does not show the correct version
# G) \9 [) Z; n" a' J1647843 ALLEGRO_EDITOR ARTWORK          Misleading information in command window when artwork import fails
0 j. H( m! y7 I9 _/ h. c1648575 CAPTURE        OTHER            Suppress warning setting must be written in capture.ini file/ R" I& L: e2 g( O: K
1649060 CONSTRAINT_MGR CONCEPT_HDL      Rename dcfx to dcf process results in error in log file and dcf not updated2 d: Z3 k& ^8 o3 }( I5 z
1650106 ALLEGRO_EDITOR 3D_CANVAS        3D canvas rotates mirrored components in unmirrored angle$ j# n, [  B$ P# G0 M9 U
1650238 SIP_LAYOUT     WIREBOND         When performing 'Adjust Min DRC', the reference bond finger should not move.6 V1 t2 h5 V4 x4 m5 D+ U1 b
1650734 APD            SHAPE            Shape on L1 does not flood properly
' v9 U6 ?& ~1 J8 ^1650793 CONSTRAINT_MGR CONCEPT_HDL      Conflict of XNET_PINS definition between the chips and the SIGNAL_MODEL is not handled correctly5 x! i0 H/ n: D( s+ H
1650801 ALLEGRO_EDITOR SCHEM_FTB        Running Export Physical with Update PCB enabled in Project Manager crashes netrev.exe, G& U- ^7 a3 L2 O! ]
1651011 ALLEGRO_EDITOR 3D_CANVAS        Interactive 3D viewer shows mechanical symbol mirrored
$ A' j+ p5 h4 U; O8 j1651063 ALLEGRO_EDITOR CROSS_SECTION    Cross-section preview is incorrect
* g+ R) O+ g' }5 X! H, w6 a7 z$ o- a1651066 ALLEGRO_EDITOR DATABASE         Pins not connecting even after running the Tools - Derive Connectivity command. A" R% J1 ], z- n5 C) O) Z
1651700 ALLEGRO_EDITOR SKILL            Running axlXSectionModify() on a layer removes the value of the material
6 I2 I, a, q9 ]3 A. S1651925 ALLEGRO_EDITOR ARTWORK          Searching for a macro in the artwork data file: Count for the macro does not match the actual count in the output6 ]; _  |3 N. T
1652230 CONCEPT_HDL    CORE             The master.tag and vlog004u.sir files are not created in the entity directory on saving symbols
% i1 |: K# I( c+ i% o1 }1653080 CONCEPT_HDL    ERCDX            Difference in results from SPB16.6 in 'erc.rpt' when logic_data is renamed as worklib in SPB17.2 on RHEL6.5
2 p( o5 |+ t$ ~4 Q2 D+ Q1653422 ADW            LIBIMPORT        Classifications not linked to a Part Number or Cell Model are removed during Library Import2 x4 m8 K; t. g5 C7 k9 G* v
1653526 ALLEGRO_EDITOR DATABASE         Via padstack keepout is not displayed on the canvas when pads suppression is enabled.1 Y' w* g1 G5 F, R: o
1653951 ALLEGRO_EDITOR CROSS_SECTION    Cross Section Editor changes lost despite selecting No to the 'All changes will be lost ...' message
# a5 x# ?6 `3 c1656224 ADW            FLOW_MGR         Copy Project wizard no longer allows dashes in the 'Name of new project folder' field
$ x1 R! Z1 {0 f7 [- N8 @1656581 ALLEGRO_EDITOR OTHER            PDF generated for layer with shape shows undesired voids if film is mirrored and Filled Shape is not selected/ H$ c  N" [+ X" \
1656608 APD            REPORTS          Incorrect calculation in the metal usage report
! V" w. K( E; q! v* u' z1656726 CONCEPT_HDL    CORE             Interface command always disabled in the Wire menu6 b, [! _9 C% j% ~0 I* b% f' B# m
1656841 CONSTRAINT_MGR UI_FORMS         Incorrect layer information is displayed in the Edit Via List dialog when a filter is applied
8 [: t" U5 r) a( b' P; s+ @$ E1657220 ALLEGRO_EDITOR SKILL            axlXSectionGet() returns Primary list of layers and not All stackups; U% G, ?4 M/ J% L5 {1 h
1657257 SIP_LAYOUT     EXTRACT          When using extracta, custom layer names not getting retained
9 J- C6 g  i6 N6 S6 B8 D+ u2 n6 Z1658440 ALLEGRO_EDITOR PAD_EDITOR       The location of a drill in the .pad file is different from the .dra file4 Z$ r3 z( X0 `/ w* O
1658445 CONSTRAINT_MGR CONCEPT_HDL      When DCF file is converted to ASCII, no further updates are allowed.8 J1 Q* O- x/ V  |
1659473 SIP_LAYOUT     WIREBOND         When moving wirebonds they are jumping instead of sliding; C* d+ ^3 O" w. j% b. q& }  N6 b
1659498 ALLEGRO_EDITOR INTERACTIV       Unable to turn off line on Etch Wire for Jumpers# s5 T0 o2 z. i$ ?8 n& l
1659644 CONCEPT_HDL    OTHER            Predefined nets are not listed if 16.6 design is being opened in 17.2
2 e1 r# u$ ]1 i* ]1 \: K$ r1660475 CONSTRAINT_MGR UI_FORMS         The CTRL+V shortcut is not working in the Export Constraints window in Constraint Manager 17.2
3 Y6 w# R1 J  y$ M  T& l1660492 ALLEGRO_EDITOR UI_GENERAL       PCB Editor crashes when using multiple desktops on Windows 10# t. G5 ^3 ^  O: B9 }6 l- G
1661133 CONSTRAINT_MGR ANALYSIS         PCB Editor crashes if comma is used in the Value field for Analysis Mode
6 ~0 i9 \- F+ X: r% [1661307 CONSTRAINT_MGR CONCEPT_HDL      Prevent creation of diff pairs on VOLTAGE nets; {7 R3 o6 ~7 W1 h
1661357 ALLEGRO_EDITOR EDIT_ETCH        PCB Editor crashes when using Route - Connect3 x! V$ [' |2 t2 O+ a+ R
1661874 ASDA           DESIGN_CORRUPTIO Unable to delete the ZERO part from the schematic page: F% f, [4 @2 E5 X' e7 Y$ Y+ r4 c
1662799 ADW            SRM              Mechanical symbols are not being displayed in the Mechanical tab of Symbol Rollback Manager% c, g# ?1 h. ?( a3 F; b- R
1664797 SIG_INTEGRITY  GUI              Unnecessary coupled interconnect models were generated during View Waveform.
- x0 d0 I( P! s6 S1664858 ALLEGRO_EDITOR EDIT_ETCH        PCB Editor crashes during Auto Interactive trunk route.! r" f7 |) D, |5 d5 a6 U
1664911 ALLEGRO_EDITOR OTHER            PCB Editor freezes after DRC Update is performed" W1 C; D/ V4 J2 v  k) J
1666329 CONSTRAINT_MGR OTHER            SCM Import Physical process crashes cmfeedback; H; j8 ?$ P' O9 u
1666551 ALLEGRO_EDITOR ARTWORK          Import Artwork, Mirror option separates imported artwork to different XY locations
3 n/ u" _- i! q) E1666723 ECW            TDO-SHAREPOINT   TDO login is not working with Site Minder because of incorrect characters in the Site Minder login form HTML
1 Q: C2 ^. @7 i# L1667068 ALLEGRO_EDITOR SHAPE            Update shape removing the shape voiding: f1 }/ U) f, E, h) [. j
1669828 F2B            DESIGNVARI       Variant Editor crashes on Windows 10 T540 P laptops but works fine on Windows 10 desktops4 C' _5 X( ~8 O$ _, q
1670221 ALLEGRO_EDITOR DATABASE         Non-recoverable corruption error is reported when saving the board after adding a layer% ?- S: a% I% k% X. U/ x' `% |
1672134 ALLEGRO_EDITOR ZONES            TDP needs FIXED component override
8 M, P8 b$ [+ t
' S/ M6 ~& A+ B! E; v2 Z, U" y- {, z# _( n
Fixed CCRs: SPB 17.2 HF0087 |7 h& O/ c" h2 ~* o; _
10-29-2016) Q; E8 G! A. @, ^" p4 s  I2 p) j
===================================================================================================================================
& E. X& B9 K! g; B3 @+ J4 ^CCRID   PRODUCT        PRODUCTLEVEL2   TITLE3 o% v! B! k+ J& [& M1 e/ u) W
===================================================================================================================================8 y+ s" j" m1 z
1644406 ALLEGRO_EDITOR SHAPE            Alternate symbol placement results in illegal parent identifier error
: U8 o  ^% `7 m. R/ s5 S1647098 SIP_LAYOUT     OTHER            SiP crashes on symbol copy and rotate
, P, [+ Z; r( h$ |, J! Y9 o1647154 APD            OTHER            Disconnected Clines not working
/ i+ L5 @0 S8 z7 N# r1648817 GRE            IFP_INTERACTIVE  Allegro PCB Editor stops responding on adding netgroups to a nested netgroup
" k5 D0 w5 h( a' U  {: Z+ ~, `1649829 CONCEPT_HDL    CORE              A delay is observed before the sub menus of the File and Tools menus appear* D& A  @- j  O
1652930 ALLEGRO_EDITOR OTHER            Command-line version of switchversion not working
; R( G% B% ^$ O& U- F0 X1653109 ASDA           DESIGN_CORRUPTIO SDA not pulling latest library information for part5 a, }; V" c/ ]$ `
1655377 FLOWS          PROJMGR          Project Manager crashes on Windows 10  \3 z- a" @% r& x

$ h) |( v* \) i, [9 @
0 R; _2 x# G1 hFixed CCRs: SPB 17.2 HF007- j+ h  S5 g/ w8 [1 P1 p7 q1 n
10-20-2016
1 {  ^. K! P! l4 _/ f7 u: N' ^===================================================================================================================================
5 V) j  j8 i- p! Z3 M9 kCCRID   PRODUCT        PRODUCTLEVEL2   TITLE
8 ~9 U* [' g4 |1 ?0 [. M% ^===================================================================================================================================
! }/ c. h" Q8 ]% |9 t: Q" a  ]; C1582276 CONCEPT_HDL    CORE             Need the ability to delete an image placed on the DE-HDL canvas
3 x- ?; _6 r4 Q; ^1 N7 d1594101 CONCEPT_HDL    CORE             No error or warning issued on specifying an incorrect unit for voltage
3 x$ R8 y# L: S/ V6 I1611293 ALLEGRO_EDITOR UI_GENERAL       If the Command window is floating, it cuts off text from the bottom half of the last line.& g9 d1 o8 d: k$ Q3 I
1611652 ALLEGRO_EDITOR UI_GENERAL       New artwork film not appearing in the drop-down list for Visibility Tab  u; @& Q' c0 G. o7 A' t& j
1618205 ALLEGRO_EDITOR UI_GENERAL       New Artwork film added is not updated in Visibility - View
+ \0 Y: S$ J! B3 L; U1631114 CONSTRAINT_MGR OTHER            SKILL functions axlCnsPurgeAll and axlCNSDelete delete spacing constraint sets but not deleting names# `1 S1 e5 J/ Q$ J( m
1633726 ALLEGRO_EDITOR UI_GENERAL       Visibility tab not dynamically updating the view list when artwork film changes1 n5 ^8 i! W. A# \
1636404 CONSTRAINT_MGR CONCEPT_HDL      In 17.2 QIR1, DE-HDL Constraint Manager allows users to enter invalid voltage units
/ e4 {  Z, k/ [1636864 ALLEGRO_EDITOR UI_GENERAL       Domain Selection for Visibility does not work with Hotfix 004 unless you save and reopen the board file
' N0 A$ R2 N( c: |* t* v( [9 S1638251 ALLEGRO_EDITOR DATABASE         Unplated hole changed to plated hole after uprev from 16.6 to 17.2 version
  l. s0 T+ p5 H1 e; o1639483 ALLEGRO_EDITOR EDIT_ETCH        Manually routing discrete components with incorrect constraints causes PCB Editor to crash
7 b4 K; X$ o! w9 X- L1641435 SIP_LAYOUT     IMPORT_DATA      Need SiP Stream mapping layer count to match Virtuoso stream layer mapping count
' d5 W, V3 W1 e0 L4 F1641483 SIP_LAYOUT     WIREBOND         SiP Layout - Modify the wirebond report generation for Start and End height when using a DISCRETE class footprint* T8 N0 I* \; q( E& J* X/ v' f
1644131 F2B            PACKAGERXL       Option needed to package a DE-HDL design with ptf errors into a board file# Z$ S' F5 e+ k7 Z) x2 m+ d% |0 d5 q
1644807 CONSTRAINT_MGR ANALYSIS         Unable to set electrical constraints modes with the OrCAD PCB Designer Professional licenses8 ?! z, z* G, c$ u  v) a
1646228 ALLEGRO_EDITOR UI_GENERAL       Running the axlUIMenuInsert command to add a submenu after running the axlUIMenuFind command crashes the tool9 ?" K# T3 Q2 R
1647402 PSPICE         PROBE            Unable to print on Windows 10 as no plots are displayed in the Probe window
0 r+ z, k/ P9 F( a6 ^  ?1648183 ALLEGRO_EDITOR INTERFACES       Allegro STEP Export: Using the 'step_3D_copper' variable, pads not exported in the same plane as traces and shapes
2 e6 S- s* @% P- L4 m" g& |& ]1649222 APD            ASSY_RULE_CHECK  Allegro Package Designer stops responding on running the Acute Angle Metal DRC% F3 S/ b6 w% h/ E
; D& i1 ^8 O8 q. a0 J* n& G4 v6 `

0 t; v; Z; ^6 Y3 Y0 t' BFixed CCRs: SPB 17.2 HF006
% p* |- r/ e1 F2 n  @10-7-2016/ `9 T0 C* ]3 u  }$ x" n% D
===================================================================================================================================
6 F& W0 `- q) y& [0 X% m, ~( PCCRID   PRODUCT        PRODUCTLEVEL2   TITLE2 C7 n) v$ B; O% c
===================================================================================================================================+ T* ]2 w) `2 _% i; R: ?. V
1585203 ADW            DBEDITOR         Optimize check-in of footprints with multiple padstacks
2 ]: R$ E8 c; \: q+ e1607954 ALLEGRO_EDITOR SHAPE            Dynamic Shape not updating correctly. S9 N  ^& I) z+ ?* {
1618173 ADW            SRM              SRM does not automatically run when a .brd file is opened from EDM Flow Manager in 17.2 Hotfix 0037 N. ?* d8 D2 h5 Z" ~3 ]+ R
1618832 ADW            SRM              SRM marks parts as updated even when they are not updated
. W$ O, j( m  f( E4 R: D1623823 SIP_LAYOUT     WIREBOND         NO_WIREBOND property is ignored by Add/Edit Non-Standard
) b4 B. z4 l; _' M7 n! h9 }0 W1626001 ALLEGRO_EDITOR SHAPE            Shape to route keepout DRCs reported for dynamic shapes in the attached design
7 A0 k0 Y2 S: e2 l+ ~' J- e1626546 SIG_INTEGRITY  FIELD_SOLVERS    Extra RL elements in via spice circuit model generated by Via Model Generator
2 V2 z- e( _# s1631792 SCM            OTHER            The NC net has re-attached itself to another net, RIGHT_LEFT_N, in the design
4 Q9 i+ O4 }6 E3 ^( N/ v2 V) S1632223 ADW            LRM              Checking in a hierarchy causes a crash
- [; N' x5 [2 [' d7 ~1632844 F2B            DESIGNVARI       Part is simultaneously defined as Pref and DNI in Variant Editor with no error
9 r4 j5 d% T$ O! G8 J- y7 [) M1633647 ALLEGRO_EDITOR MANUFACT         Variant issue: Create Assembly Drawing command not creating filled shapes for keying pegs in attached design
" F' N2 d: U" l1633707 ALLEGRO_EDITOR DATABASE         Cannot remove Route_Keepout associated with a pin
# f' Q8 Z( _" x* K1634392 PCB_LIBRARIAN  OTHER            Launching Library Explorer without -proj option crashes the tool
+ V* ?+ _; V+ E9 I' ]. j1635049 CONSTRAINT_MGR CONCEPT_HDL      DE-HDL crashes when trying to create layer set from Constraint Manager' L2 a. _; S* t
1635593 ORBITIO        ALLEGRO_SIP_IF   Importing  .sip file reports undefined argument error while processing shapes
' j( _! t. {& E" n6 ~& t! a9 q1635858 ALLEGRO_EDITOR ARTWORK          Get 'WARNING: Null REGULAR-PAD specified for padstack' messages in log file when generating artwork for all layers
4 S0 g' q' ?1 |: T1636097 ALLEGRO_EDITOR ZONES            Technology Dependent Packaging footprints not updating in the design- ^% d! M$ p+ F" }1 L5 \4 \
1636185 ALLEGRO_EDITOR ZONES            Import Placement not placing TDP footprints in zone' b# p6 o6 [8 d( l9 u  q1 O
1636867 CONSTRAINT_MGR OTHER            Millimeters shown as mils in the Analysis Modes dialog box$ X5 C' G" j8 A, y6 x% Y' ^
1638094 SIP_LAYOUT     OTHER            Cross Section Editor not seeing updated information
( j. P0 J2 a1 d  m8 f) W+ t' f1639845 ALLEGRO_EDITOR INTERFACES       Step file not generated when board is exported to a folder with special characters in name% s& h" X; w/ Q$ \' W0 u
1640611 APD            SKILL            Launching XtractIM from SiP Layout with the attached design crashes both SiP Layout and XtractIM, l: b$ C9 m  ^: _* a$ T" T; D
1641339 ALLEGRO_EDITOR INTERFACES       DXF_IN does not show all the subclasses available in the design8 x. t0 }9 _2 M) K) T  @( a: Z7 ]
1641879 XTRACTIM       GUI              XtractIM crashes on extracting a SiP design if 'SI Ignore' is selected for a die stack layer in Cross Section Editor
; L( M4 _+ f& w1642012 CONCEPT_HDL    CONSTRAINT_MGR   Schematic-defined net groups without any members cannot be deleted in Constraint Manager4 V% g+ l7 L, q& c5 h/ X8 z
1642015 CONCEPT_HDL    CORE             Pin exists on block but no corresponding port exists in the underlying schematic% T8 S& M% @0 T* `; s1 P# c
1642597 ALLEGRO_EDITOR OTHER            Importing .tdp file: Footprints not included in the .tdp file are updated in the design
0 Q; {, u/ g9 I( k3 S6 _" c/ \1643557 SIP_LAYOUT     DIE_GENERATOR    Die Text files will not update the design
5 X. X0 W6 O4 ]6 B2 l1646086 ASDA           IMPORT_BLOCK     Importing a DE-HDL design into SDA results in error 'IMPSHT-42 Alias cannot be created'8 b" j. T4 I7 q& {* j. M8 X
1647580 ASDA           IMPORT_PCB       SDA-File Import from PCB Editor has duplicated RefDes on schematic.
# ^, ^2 l- b0 |' F6 ^! o
8 w" p$ ]8 m' K$ f$ @# f' G- E6 h
Fixed CCRs: SPB 17.2 HF0056 y/ m4 d4 t5 V& u3 H" H9 I4 z1 p
09-10-2016
2 g! V) @& u, `2 g8 V' D===================================================================================================================================5 j. F0 N. C5 k
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
, N3 C/ ?/ \" t7 Z7 C" f7 e===================================================================================================================================4 N. U/ c! @4 i) t2 _" M
1496199 ALLEGRO_EDITOR SHAPE            Overlapping route keepouts result in a broken shape- h* w/ L* t3 V; Z3 O
1519972 ALLEGRO_EDITOR DRC_CONSTR       Dynamic phase DRC at incorrect location
! U5 M' h$ S* w% v, f+ l( k1521940 ALLEGRO_EDITOR DRC_CONSTR       PCB Editor not recognizing the correct pin pairs of the differential pair* [6 Z) r7 \( Z* g
1536713 ALLEGRO_EDITOR INTERFACES       File - Viewlog still checks for brd2odb.log file! f! k8 x) [+ V  y& z) g
1568912 RF_PCB         BE_IFF_IMPORT    Route keepouts can only be imported once
3 H* ^. T. B, E0 ?1586846 RF_PCB         PLACEMENT        Get an error while manually placing RFCOMPIB part" G6 Z3 z! E$ ]' a9 c) `* Y& h
1588769 ALLEGRO_EDITOR UI_GENERAL       ALT+key shortcuts are not available in 17.2$ Z" o2 O* I. U
1589396 ALLEGRO_EDITOR UI_GENERAL       Need option in 17.2 to change the placement of the Find, Visibility, and Options tabs
0 D: M9 |( g1 D) R. D; e/ V1593258 ALLEGRO_EDITOR OTHER            Adding German letters to database diary deletes all the entries
+ \$ d2 c6 R4 O5 E% `1597413 SIG_EXPLORER   SIMULATION       SigXplorer crashes when simulating with a via that was added to the canvas
% g7 A$ r9 b2 C1 ]/ g3 R1599680 ALLEGRO_MFG_OP ALLEGRO_INTEG    Documentation Editor crashes on opening a specific database
! E2 D: r6 r5 _8 [. b1 ]4 O4 {; @1606682 ECW            ADMINISTRATION   ECWBackup and ECWRestore fail when data is 1GB or more
; g, M% [  w, ^: V( _' V1607250 ALLEGRO_EDITOR DATABASE         A board file created in release 16.5 crashes when opened in 16.6 Hotfix 69
+ c, A" K" q! ?9 r6 f5 I1607565 ALLEGRO_EDITOR SYMBOL           Default values are not consistently converted when adding pins after changing units.
! g0 |. a+ w. l& ~, ]( ]' j1607956 ALLEGRO_EDITOR OTHER            Unable to generate the model index file from the command line using mkdeviceindex8 t% s. M+ ~' h+ t) i$ a5 Q2 `
1609794 ALLEGRO_EDITOR UI_GENERAL       PCB Editor: Shortcut keys to menus are not available in 17.2& A' w7 N' n; v2 u' \- ]) x
1609817 CONSTRAINT_MGR CONCEPT_HDL      DE-HDL crashes on opening project; I/ y% {9 J" X
1611446 ALLEGRO_EDITOR SHAPE            Inconsistent break in shape when creating voids in a design in  16.6 Hotfix 69/ r8 X( h8 X" [; L: F& _# C
1613512 ORBITIO        ALLEGRO_SIP_IF   Unable to read the OrbitIO database file (.oio) in SiP Layout  ?3 f6 K0 j  `0 O9 L
1619610 ORBITIO        ALLEGRO_SIP_IF   Some mechanical pins appear rotated by 90 degrees when imported" V! }, @) u3 ]( O9 }% w
1620814 ALLEGRO_EDITOR PARTITION        Etch and Via are not imported with the partition, z2 C8 B7 n, `4 {7 Q) W; B
1621390 GRE            CORE             Design Crashes during the Spatial Planning phase1 x. P0 p7 L+ g$ C
1623112 ALLEGRO_EDITOR OTHER            SPB17.2 switch release is unable to identify 16.6 release when 16.6 is installed in All-Users mode
! V1 ?% o% ?/ t1623113 ASI_SI         GUI              Aggressor waveforms are not displayed in waveform viewer after crosstalk simulation7 c$ ~1 X' P% h
1623231 CONCEPT_HDL    CORE             Unable to make the Attributes form part of the standard display in DE-HDL& I$ ^. m5 L# O" F" `
1623666 APD            OTHER            Incorrect vector pin syntax appears in the chips file written using 'RF Module - Export chips & connectivity'
. z  F$ u- e  Z6 n8 R1623888 CONSTRAINT_MGR CONCEPT_HDL      Ambiguous and inaccurate mapping errors reported when an ECSet is applied to a differential pair object
( q; z1 F: R8 w1623904 ALLEGRO_EDITOR SCHEM_FTB        Logic import fails, but no error mentioned in the netrev.lst file
$ i2 ]+ L! x& w  T0 L# u1623935 ALLEGRO_EDITOR SKILL            On running the SKILL function, axlSectionModify, Shield and Etch Factor are not updated
, V, Y2 p6 @4 v+ ~( F+ \1625610 ALLEGRO_EDITOR SHAPE            Modifying a shape boundary leads to other shapes losing their voids
0 |/ n( ~, Q; U1626716 ALLEGRO_EDITOR UI_FORMS         Z-Copy menu is not available with OrCAD PCB designer Professional license9 i. S$ G8 l/ ~" }, W7 S
1628403 ADW            TDO-SHAREPOINT   Objects remain checked out after multiple failed 'check-in hierarchy' attempts
3 M7 ^& P% Z0 A& `3 Y2 |1 |6 Q1630458 ORBITIO        ALLEGRO_SIP_IF   Import OrbitIO Database file (.oio) in SiP: Bill of Materials report does not include standard dies) [, Z, w# r4 x; D: C8 `' B/ R
1632504 CONCEPT_HDL    CORE             DE-HDL core dumps during Save Hierarchy on Linux
- V; l( B6 C* L$ j2 y  K3 y) t3 E1633581 ALLEGRO_EDITOR PLACEMENT        On mirroring a part, the cursor moves to the origin of the board  ?/ v  {; g4 e* `
1633601 ALLEGRO_EDITOR PLACEMENT        Place - Via Arrays - Boundary command: Via arrangement pattern deteriorated in Hotfix 004
' }# s. ]: m0 D% ?- w' r
, c9 G, c" n% g- d* S& e* C, M& F
, N5 Z/ _3 g" B  l1 @4 UFixed CCRs: SPB 17.2 HF0046 D1 G& M! I' I! f1 r
08-14-20164 D; V7 G2 l; ?9 k! [, Y6 n* C
===================================================================================================================================5 E6 y: F+ j9 r0 |
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE% K$ J* g1 }5 S, Q; V
===================================================================================================================================. s3 e* }7 b- g& S
908816  CAPTURE        SCHEMATIC_EDITOR Few graphical operations are active even when a page has been locked0 a0 M! Z3 B4 ^4 W# l  b8 F
1213923 ADW            LIBIMPORT        Cannot delete parts in the Library Import project (XML), \- z5 m# F) e: q0 {- h2 Q
1250476 PCB_LIBRARIAN  LIBUTIL          con2con does not check for PACK_TYPE value set to question mark
3 c; j. q' A1 _( x. p/ f( K+ ~1306441 APD            OTHER            The Minimum Shape Area option in Layer Compare uses an unspecified value: f8 V9 f2 x& B
1322242 ALLEGRO_EDITOR INTERFACE_DESIGN Using Add Connect with the Replace Etch option causes PCB Editor to slow down for certain constraint nets1 B3 f) n6 Z. T* [! W7 |( E
1326716 ADW            DOCUMENTATION    Dataexchange documentation correction needed! C8 `# j3 T) ~. o; N
1356948 APD            DEGASSING        When using the Degassing tool on shapes the size of the file becomes very large$ Z( d3 M" m/ d& k8 _
1376510 ADW            DBEDITOR         DX output ERROR after Property Display Ordering of Part Classification.
$ c& T2 ^7 y2 N: \1408218 ALLEGRO_EDITOR MANUFACT         Specifying the Offset value results in unexpected value of the NC Route coordinates in the .rou file
& R& `. a8 B) }! v" [1410485 CAPTURE        SCHEMATIC_EDITOR The 'Autowire - Connect to Bus' menu command and the 'W' keyboard shortcut are enabled on a locked design
4 i: X4 c3 z# D% d1413248 CONCEPT_HDL    CORE             Import from another TDO project makes the block read-only% w& B$ R+ C% T! Q
1413287 ADW            LIBIMPORT        Library Import converts all Attributes to uppercase when reading CSV" I& N, `  v6 n: m* {& L5 h, D
1417429 ALLEGRO_EDITOR INTERACTIV       Pick box only accepts 1 set of values. You need to close the box and reopen it to draw a rectangle
2 Z% i, G, m7 Y$ [! y  O8 H7 V1417442 ALLEGRO_EDITOR INTERACTIV       Spin via stack and only part of the stack spins
1 W8 d) X. r" y1 _9 E, n1430251 ALLEGRO_EDITOR PLACEMENT        Quickplace placing symbols outside of a polygon shaped room
9 g' ^8 ^% S+ [& k; X7 L" H. R" B1440509 ALLEGRO_EDITOR PLOTTING         Ratsnest does not follow the RefDes position when plotting the BOTTOM layer with the Mirror option. P% V5 r# ~5 O. x
1441086 PCB_LIBRARIAN  OTHER            Changes made to a package with sizable pins generated from the 'sym1' view are not saved
. ^4 M  t, y! o8 f" b$ _$ o0 Y* }1443339 PCB_LIBRARIAN  PTF_EDITOR       ALT_SYMBOLS syntax in PTF file not checked; m! S4 g+ b0 _
1444144 ALLEGRO_EDITOR DRC_CONSTR       The 'add taper' command generates line to line spacing DRC
! H0 L! |% o2 {5 N1451766 CONCEPT_HDL    COMP_BROWSER     License error message should indicate which license is required( i1 u. X" W% q: k* A8 A
1451977 CONCEPT_HDL    PDF              Origin of PDF mediabox not starting at (0,0) when PDF page_height and page_width are set
  G% G9 b( D& t! s  H. [1457138 CONCEPT_HDL    CONSTRAINT_MGR   devices.dml: difference in content generated by _automodel add command and Constraint Manager launch2 M% H) Y& V! d
1458439 F2B            PACKAGERXL       The Packager pstprop.dat file reports false conflicts in net properties
& I+ }& k$ ^- e* t+ T1464865 CONSTRAINT_MGR ANALYSIS         For identical nets, topology in DE-HDL CM is different from the topology in PCB Editor CM* j( g& ]$ g8 f) g
1464948 PCB_LIBRARIAN  VERIFICATION     The errors/warnings do not match between the various tools
& K4 R+ q* g) R! L* E1467826 CONCEPT_HDL    PDF              PublishPDF from console window creates a long PDF filename
  R; H  z5 O2 a1470106 ALLEGRO_EDITOR MANUFACT         silkscreen program cuts auto-silkscreen lines excessively. f5 X" i% ~) p9 r! B1 P
1471287 CONCEPT_HDL    CONSTRAINT_MGR   Pages imported from other designs with different units should inherit the source constraint units
3 @# \, c6 F) G  h, m" W1472046 ALLEGRO_EDITOR OTHER            Gloss routine, 'Via Eliminate' - 'Eliminate Unused Stacked Vias' is not removing unused microvias from the stack
  G4 W. {. q* O1472414 ALLEGRO_EDITOR SCHEM_FTB        netrev changes pin-shape spacing rule in constraint region* a1 f+ r2 l1 K* i5 G
1472444 ADW            ADWSERVER        Multiple errors in adwserver.out after SPB054/ADW47
! p4 C% d' b0 x3 [" `3 h1473056 ALLEGRO_EDITOR ARTWORK          Gerber export has additional phantom data not on design
/ T8 f/ }" I; I! X# d) {4 U4 {' H  z1473900 CONCEPT_HDL    CORE             DE-HDL stops responding when a hierarchical block with variants defined inside the reuse block is enabled
! O9 f8 R( V: r! t1474020 ADW            DBEDITOR         Unable to modify schematic classification when a part is checked out previously by another librarian# G! }+ f* C. p/ ]
1474066 ADW            DBEDITOR         Bulk edit performance lags when parts included have a large number of properties
0 ]* W, m7 C* C  a2 e  ?1474764 ALLEGRO_EDITOR PLACEMENT        In Hotfix 56, the 'place replicate create' command does not produce desired results if a fanout is marked& ?4 g; n% w$ x+ `" C, G  I' ?
1474894 ALLEGRO_EDITOR PLACEMENT        Place replicate fails to include vias when the module is applied to other circuits.
' J' t! G/ _! t5 c5 [( I. B3 m1475650 ALLEGRO_EDITOR OTHER            Using Outlines - Room Outline gives WARNING (axlRemoveNet): No match for subclass name - 'BOARD GEOMETRY/__EPB_SCRATCH_'
/ c% f( P4 h8 D9 x1476528 ORBITIO        ALLEGRO_SIP_IF   While translating a .mcm to OrbitIO, the error 'allegro2orbit.exe has stopped working' is thrown
# y' Q+ }" r/ E& V! a; q1476920 CONCEPT_HDL    OTHER            Genview consistently fails in some indeterminant manner.7 j6 r, z) ~& i+ U( |
1477369 CONCEPT_HDL    INTERFACE_DESIGN A significant number of problems are reported when running genview with port groups
  K" ^  y- J8 B: J1478111 F2B            DESIGNVARI       Hierarchical block variant not shown in testcase with S57 although it was working with 2015 release3 n. e& D- H* R/ v1 G
1478200 GRE            IFP_INTERACTIVE  PCB Editor displays the 'Low on Available Memory' error when updating shapes and then crashes
: N' W- C( [5 l/ V9 m1478680 CONCEPT_HDL    CORE             Unable to move components in a schematic using the arrow keys
* a2 R9 H+ S' n4 b+ [5 h1479135 F2B            PACKAGERXL       Hierarchical design reports conflicts when signal names change through the hierarchy
  L0 N+ h. X6 |- {7 R% s) Y3 e1479153 CONCEPT_HDL    CORE             File - Save Hierarchy flags an error and does not update subdesign xcon
" T9 o& x/ c3 p+ _2 i( N1479227 CONCEPT_HDL    CHECKPLUS        Custom DE-HDL Rules Checker rule flagging invalid voltage in hierarchy
+ J( r* q& S* s+ T7 J+ _6 w! y. Q1479454 CONCEPT_HDL    OTHER            DE-HDL issue: locked DIFF_PAIR property is editable
6 {! E- i8 \6 \, X3 h3 W/ C1479569 PCB_LIBRARIAN  OTHER            hlibftb fails with error SPCOPK-1053
! b4 ]) a, l, d2 P2 S2 ^0 }* u+ U& t1479785 ORBITIO        ALLEGRO_SIP_IF   BRD file is not loaded in OrbitIO% t  c, b1 i) n( E
1480005 ADW            DBEDITOR         The DBEditor or DBAdmin GUIs do not allow the same characters in Property as LibImport CSV Files: v7 G) g! g4 _' X2 z! D  V0 S
1480367 SIG_INTEGRITY  OTHER            Differential pair extraction SKILL error
0 X% P8 ], u4 m/ `4 B1480499 ALLEGRO_EDITOR PARTITION        Cannot delete partition
2 p, ^3 X' {3 p, X, x7 C1 ^4 n1482544 ADW            DBADMIN          Hierarchical Preferred Parts List (PPL) is not functioning correctly# x9 a9 @1 W; B7 k" y, D0 m8 [$ W
1483136 ADW            COMPONENT_BROWSE Error flagged when searching a property value with parenthesis or comma in Component Browser in the ADW mode0 T( Y+ T! J. [8 c
1483617 ALLEGRO_EDITOR DATABASE         Delete islands command crashes database with filled rectangles- m  e% N) t5 I( Q* b! x
1484100 SIP_LAYOUT     INTERACTIVE      SiP crashes when copying and rotating a symbol
. ~, p6 a+ C; I$ w1 l/ `1484781 CONCEPT_HDL    CORE             Three different Hierarchical Viewer issues
' s7 C3 {8 r4 r6 ~& I, o1485059 PCB_LIBRARIAN  CORE             Part Developer pin attributes are randomly marked as read-only8 @/ t. |$ }! I! o
1485931 ALLEGRO_EDITOR INTERFACES       Errors generated when importing IDF in an existing board file' a8 N; M4 ^5 h/ y2 U
1485960 CONCEPT_HDL    CHECKPLUS        Custom DE-HDL Rules Checker rule is crashing the project5 T8 N& N, s# r- ^2 V
1486086 ALLEGRO_EDITOR ARTWORK          Cannot generate artwork.
* H5 h/ G4 Y' ]5 @8 r9 N1486378 ALLEGRO_EDITOR PARTITION        Unable to delete orphan partition as it is not listed in workflow manager.
: X1 V/ ~. i' |1487085 CONCEPT_HDL    CONSTRAINT_MGR   Import Physical with the Constraints only option reports problems# r$ L% c* D# i1 x1 R' }3 r) O2 z
1487125 ADW            COMPONENT_BROWSE Results not displayed in Component Browser for parts with no associated manufacturer parts! X; ?' C# V- t* X" g! g5 V3 S0 S
1487265 CONCEPT_HDL    CORE             Replace command in Windows mode shows incorrect behavior
5 L% X8 ~) h* L, |; g- L6 e1 c1487496 ADW            DATAEXCHANGE     DX changes checkout ownership when override action is set to remove existing relationships8 u, ~1 U& f4 P+ g8 m
1487656 ADW            LIBIMPORT        Pre-analyzing a project reports false warnings
# K( O4 D$ F2 R+ V. N$ g8 d1487733 CONSTRAINT_MGR OTHER            Export Physical takes more than two hours to update PCB Editor board
) U0 f5 T. o% G3 d: }7 @1488753 CONCEPT_HDL    CORE             Import sheets in a design with no change in models: CM_VALIDATION_ON_SAVE variable is triggered% Z! |& I3 r: O3 A
1488758 CONCEPT_HDL    CONSTRAINT_MGR   Disable Constraint Manager launch if CM_VALIDATION_ON_SAVE is set and the database goes out of sync: i# T7 m0 s$ V; V
1490299 SCM            OTHER            Allegro System Architect does not update revision properly9 i5 C8 h/ ]' d& q
1490744 ALLEGRO_EDITOR SKILL            axlChangeLine2Cline changes line to cline and places it on the TOP layer$ E  k5 D7 M" @( ]
1490924 F2B            PACKAGERXL       Save Design/Export Physical is resetting Via constraints* Z" Q, l0 |: r; `  V0 T- l
1491351 ALLEGRO_EDITOR OTHER            Create Detail for bond fingers on a custom layer not working& C2 c/ R% l1 D1 m
1492013 CONCEPT_HDL    CORE             Stale PNN properties not cleared from schematic on packaging design (backannotation)
, B# O8 M  o. I8 N* n1492595 ALLEGRO_EDITOR MANUFACT         Dimension character substitution help is wrong$ E8 s: H) ]* Q, P( b8 j
1492703 CONCEPT_HDL    OTHER            'Global Property Display' not working for symbol edit8 f0 R. E; O. R. Z
1492777 ORBITIO        ALLEGRO_SIP_IF   OrbitIO crashes on importing MCM
7 W+ K0 V8 z. o( @1 H1492901 CONCEPT_HDL    CORE             Cannot instantiate a multi-sections symbol (> 10 versions) in Design Entry HDL
1 ]+ i% Q6 E! W/ Q1494194 CONCEPT_HDL    CORE             Random display of the 'PHYS_NET_NAME' property in hierarchical designs9 L$ A' F6 B$ H0 Z; d+ m
1497597 ALLEGRO_EDITOR DATABASE         Show Element on pin shows wrong drill size/ v: O4 R: ?& R
1497956 CONCEPT_HDL    CORE             ADW Library Flow test schematic generation crashes DE-HDL while saving the design when using customer adw_conf_root
# y; X0 v; h( @2 C1498234 ALLEGRO_EDITOR ARTWORK          PCB Editor fails to create artwork and no error is listed in the log file
* ]  Z# y% _7 t" A- |3 U6 x" l' l1499363 CONCEPT_HDL    CORE             Custom attributes under variant management stopped working in Hotfix60
9 G5 _, h+ _2 H+ {+ ?4 K1500422 ALLEGRO_EDITOR SKILL            SKILL function, axlTriggerSet, results in PCB Editor crashing at launch
! d& m, Y" W6 G, a1500725 CONSTRAINT_MGR CONCEPT_HDL      Unable to clear pstprop.dat file conflicts+ ]- T9 K4 Y8 R9 L5 o
1501093 SIP_LAYOUT     OTHER            Package design variant shows wirebonds connected to a die which is not part of the variant6 ?# N! v8 e9 H6 o9 L9 Q8 g! r
1501165 F2B            DESIGNVARI       TDO does not manage overlay files and variant_roz1040660_1.ba cannot be created unless variant_merged.dat is checked out9 o* \8 d* v. z/ ?% f
1501294 ADW            COMPONENT_BROWSE Some tabs missing after the migration to ADW ISR 053 with SPB ISR 0602 Z: q0 O) D3 S  I
1501974 F2B            PACKAGERXL       'Feedback has found Illegal pin swap(s)' error although the pin was already swapped and fed back (B2F) to DE-HDL3 V$ m+ X3 h# j
1502282 ADW            CONF             Configuration Manager: Clicking 'Set up or Manage Company & Site' gives an unclear message
, B4 V. T8 J! H9 s& M1502782 ALLEGRO_EDITOR SCHEM_FTB        Allegro System Architect (SCM) - Export Physical stops unexpectedly without any errors or warnings  U- n8 ?4 z, |) D2 i
1504093 ASI_SI         GUI              View Topology and Waveform buttons overlap when Signal Analysis window is resized
3 E- I# e  Z- T8 e1 A1504767 CONSTRAINT_MGR SCHEM_FTB        Constraint Manager generates errors if the 'sNoF2BFlow' property is added to the Constraint Manager Dictionary, B* E8 z( Q( B& f/ z
1506110 ALLEGRO_EDITOR DRC_CONSTR       No DRC shown when a text on etch layer is overlapped on mechanical pin
+ ?* q, D* s1 ~0 A% ~5 A8 m$ Y& h+ `# F1506654 CONCEPT_HDL    INTERFACE_DESIGN On moving, Netgroups break! }  }, X/ y" X: ^" n4 n9 t# l4 v9 Y
1507497 ADW            COMPONENT_BROWSE Switching rows in Component Browser does not change the graphics of the symbol
: f& \' w, D5 [1509184 ALLEGRO_EDITOR DATABASE         BB vias in mirror have terminal pads suppressed by artwork
3 p3 W3 D3 n* u  Q4 `3 B: d1510387 FSP            EXTERNAL_PORTS   Break in extending a net as a deep connection when it is targeted to multiple FPGAs connected in a daisy chain
- h8 L2 f7 Q7 b7 q6 C1510570 ADW            DATABASE         ERROR: Cannot check in block model because the part with instance id used in the model is not available in the database% z, _1 X1 D* f; k8 U" [' ]
1511180 ADW            DBEDITOR         Database Editor: Incorrect message about a schematic mode displays when associating a footprint to a part number8 z: P8 Q3 `- Z( R1 [
1511397 SIP_LAYOUT     TECHFILE         Tech file exported from release 16.5 cannot be reused in SiP Layout in 16.5 or 16.6
9 ?" _; x% R' c: A" s1511744 ALLEGRO_EDITOR OTHER            Allegro PCB Editor removes property from component instance- K& L4 k' E/ a+ ~- E$ x0 {/ @& K
1511761 SIG_INTEGRITY  OTHER            Allegro PCB Editor crashes on running the cns_show command.) z" w% B* J. s- d
1511947 ADW            DSN_MIGRATION    Command line arguments of the 'designmigration' command are not working9 L& q% d1 W& t
1513085 CONCEPT_HDL    CORE             NC symbols in the schematic are being renamed to NC_1 in pstxnet.dat and are routed as one net in Allegro PCB Editor
: [: C/ X3 u, X2 j" m1513092 ADW            DBEDITOR         Create Footprint Model name is not working properly if it already exists in the local flatlib. J5 |* U! n+ \; O
1513737 ADW            CONF             DesignerServer from a different network domain does not show distribution data! v2 E' E+ z- H  ?. |( P
1514469 CONCEPT_HDL    CORE             Unable to get rid of an underscore from the PHYS_NET_NAME property2 M5 q( g9 |8 }- |3 Y4 x  t
1514942 SIP_LAYOUT     CROSS_SECTION    AIR no longer permitted in stackup in 17.0  t+ {* d+ h, Y' j( z
1515318 PCB_LIBRARIAN  IMPORT_EXPORT    Import Pin Table: 'CTRL + C' and 'CTRL + V' not working correctly
9 q8 C6 U9 e! }: ~1517351 CONCEPT_HDL    CORE             Genview does not update an existing split symbol8 g" D" h! K! f+ ?8 ?" I
1517388 ALLEGRO_EDITOR SHAPE            DRC error reported as PCB Editor fails to read the void for a via$ B) ?7 i. H/ @% O. c. P* r
1518032 CONCEPT_HDL    SECTION          Error SPCOCN-2009 displayed even when the user has not manually sectioned the design
- V$ f3 K6 c+ q4 z- \  r3 t2 J5 Z1518724 PCB_LIBRARIAN  PTF_EDITOR       PTF Editor is not saving changes# o$ `. H5 p+ h! b  g& @; b4 S) w
1519040 ALLEGRO_EDITOR DATABASE         Match groups are lost when a board created in SCM is saved in Allegro PCB Designer.7 s8 {3 g5 M6 _0 J* s7 g
1519518 CONCEPT_HDL    OTHER            Genview does not generate split symbols9 M2 y7 J0 C; R2 V( o
1519623 CONCEPT_HDL    CORE             Differential pair added to a NetClass does not display 'NET_PHYSICAL_TYPE' on the canvas5 c" _7 o$ E7 n& b( X
1519910 CONCEPT_HDL    INTERFACE_DESIGN Hotfix 62: Information on manually-remapped port groups is not saved, but reset to default% D, N5 U; ~  ]7 w7 w6 O; ?
1519946 CONCEPT_HDL    CORE             Renaming a net leads to loss of constraints associated with the net
1 I5 E5 k# b0 j8 O& C& J$ w1519987 ALLEGRO_EDITOR SCHEM_FTB        In Hotfix 61, constraints are lost on importing a netlist2 C' d+ s7 t1 ?8 ?, p- W
1520207 CONCEPT_HDL    CORE             Genview crashes after renaming ports
$ Y/ z9 a8 `1 N! m1520727 CONCEPT_HDL    CORE             In Project Manager, the 'Design Sync - Export Physical' command does not automatically update the schematic
% Z' f; o! z, a, W5 d1521174 SIP_LAYOUT     DIE_STACK_EDITOR Padstack shapes not converted correctly to die-stack layer using Die-stack Editor' r) A1 A- J/ y+ w5 c( u; R& g
1521871 CONSTRAINT_MGR CONCEPT_HDL      Constraint Manager launched from DE-HDL allows space in the name of layer sets
( s% ~  E! ]4 b' q; [6 @. z1522831 APD            OTHER            axlSpreadsheetSetColumnProp with 'AUTO_WIDTH' propName does not autofit the contents.
4 w, I* Z/ _- x; b0 K& |# K1522900 ORBITIO        ALLEGRO_SIP_IF   Padstack shape distortion after translation to OrbitIO from SiP Layout design) O% }* [5 V/ P, b( k, W
1523237 ALLEGRO_EDITOR SKILL            SKILL function axlDBGetExtents() causing PCB Editor to crash
0 `, w. v4 V! P1523426 ALLEGRO_EDITOR DRC_CONSTR       Dynamic shape not adjusted based on keepout; DRC generated
  J: O+ f* k  d  I8 {$ `2 c! D) d1524875 F2B            PACKAGERXL       Packaging using csnetlister fails, while manual packaging of individual blocks works fine
; X, Y# y+ e0 x- v' R1525432 CONSTRAINT_MGR OTHER            User-defined property not being transferred from DE-HDL to PCB Editor5 u# `5 g% V/ ^8 x7 l
1525883 ADW            DATABASE         Invoking libimport on an existing DB should verify that the 'libimp_su' variable is set correctly  f# b1 K% ~# A8 ?
1525948 F2B            PACKAGERXL       Reference designators assigned by the Packager tool are not correct
/ n: M& T$ c* l! Y5 c4 d+ |1526914 ADW            LIBIMPORT        Cannot import to new library database- q; p+ f/ V- i, {
1527321 ALLEGRO_EDITOR SCHEM_FTB        Unable to create netlist with the 'Open Board in OrCAD PCB Editor' option in Hotfix 637 I7 r" k; F  T; I, f
1528075 CONCEPT_HDL    OTHER            Auto Generate: DML model assignment fails with error 'There is PHYS_DES_PREFIX property in PTF file.'6 c* R0 Y3 m, B: t1 F
1528235 ADW            DBEDITOR         Running rule 'Validate Classification Property and Property Values' results in property mismatch error! d7 Y+ R# S4 a( E% V3 P/ M% ^
1528254 CONSTRAINT_MGR CONCEPT_HDL      Import Logic with the 'Overwrite current constraints' option is deleting some attributes) u0 |5 x3 n$ c. a
1528398 ALLEGRO_EDITOR SCHEM_FTB        Netlisting of pins with NC property results in error
4 @' r. U/ n2 f" S' y1528479 ADW            LRM              LRM crashes when opened on a lower-level block in a hierarchical design
' w7 C6 w) h7 U' a$ J1528894 ADW            DBEDITOR         Lack of PTF_SUBTYPE in the classification prevents the release of the part0 u& I9 Z& v% V/ @
1529178 SIG_EXPLORER   OTHER            When an ECSet is created from a net, values are not transferred correctly for PinPairs# R( }8 ^, x, s4 B
1529209 CONCEPT_HDL    CORE             When adding a component symbol version, the More option does not show all the versions
' u* v. L! r$ R1 S% x% {3 I1529720 CONCEPT_HDL    COPY_PROJECT     Running ADW copy project does not update the 'master.tag' file- r3 Y- I0 C- b
1530445 ALLEGRO_EDITOR EDIT_ETCH        PCB Editor crashes when 'Add Connect' is used
' U) _4 J3 ~7 D  @% F3 g0 N1530707 CONCEPT_HDL    CORE             Request to recover a 16.6 design after DE-HDL crashes& D! H  L! C+ U! q
1531425 CONCEPT_HDL    CORE             DE-HDL crashing while trying to add a NetGroup* R7 [  M+ M: J! p  c' K# O
1532865 CONCEPT_HDL    CHECKPLUS        Provide the ability for Rules Checker to report a GND symbol from the standard, and not our local library, in .mkr' j& N6 ], w+ ]4 r  a: X! O% [
1533543 ADW            DBEDITOR         Component Browser free text search returns 2 parts when only 1 exists
7 ?! n& p! K  |$ m' r- ?' y  u4 A+ f1536273 CONSTRAINT_MGR CONCEPT_HDL      Model-defined differential pair is removed, and Constraint Manager Design Differences does not report an issue8 V% I) V/ o1 U  }4 y
1537055 CONCEPT_HDL    CHECKPLUS        Rules Checker - POWER_PINS value not obtained when schematic instance has the POWER_PINS and POWER_GROUP properties
/ u- B) ?$ S4 k1 `) S5 _+ N1537339 CONCEPT_HDL    INTERFACE_DESIGN No warning is flagged when moving a Net Group over a net% s6 o8 k2 ^3 l
1537521 FLOWS          PROJMGR          Do not allow project creation if there are spaces in directory or file names on the Linux platform
' A3 t2 _& k3 g1539077 ALLEGRO_EDITOR SYMBOL           PCB Editor crashes when choosing 'Layout - Renumber Pins'  A: L( \0 S4 \6 v
1539227 CONCEPT_HDL    CORE             Renaming a page from the hierarchy browser crashes the schematic editor.' E- f: I. X: d
1539997 ALLEGRO_EDITOR SKILL            PCB Editor crashes when the axlStringRemoveSpaces() command is run8 k& u7 L8 N3 A3 U. J0 B8 L6 r# s/ [
1541532 SCM            SCHGEN           Generate Schematics crashes with 'Out of Memory' error
# n3 m. x0 o5 c8 A1541680 CONCEPT_HDL    DOC              A dot (.) or period in design name created 2 separate design folders in worklib. i( [+ B; N- [8 I8 a% E) }+ Z
1542817 ALLEGRO_EDITOR DATABASE         Import Netlist not getting completed on specific board
! W; k& f; Z3 j* d- ~1542949 ASDA           EXPORT_PCB       The Export to PCB Layout form: The file name specified in the 'Output Layout File' field is not accepted
5 g$ f/ c7 y4 R0 {* z6 _+ g2 \7 B1543537 ASDA           NEW_PROJECT      While creating new projects, the new folder name is not visible clearly in the explorer
$ T% L/ S4 w4 M& j7 Y" ~1544060 SCM            SCHGEN           Generate Schematics causes Allegro System Architect to crash
' J2 f/ G/ @% T: q& o& z1544633 APD            STREAM_IF        The 'stream out' command causes Allegro Package Designer to crash
! p0 v) Q; {/ m" M: `4 m# G1544698 ALLEGRO_EDITOR PLACEMENT        'place replicate' does not add clines and vias to fanouts if fanouts are marked0 W' j# ?9 X- a+ C
1544856 ASDA           CANVAS_EDIT      Edit > Find places the process (UI) behind the SDA tool.
8 }( _" W' m' k" H. E1545136 ALLEGRO_EDITOR PLACEMENT        All fanouts are marked as part of one symbol instead of the symbols they attached with' Y  j0 E- P, S$ v
1546062 ADW            TDO-SHAREPOINT   Failure to launch TDO Dashboard, need to update error message with more useful information
4 s$ S5 k- n  O1 E9 ]1 o! p1549105 APD            OTHER            'Stream out' fails with message: 'Request to terminate detected. Program aborted'. L5 r/ s3 y# B" `9 U+ p, s
1549658 ADW            TDA              An unmapped network folder in the Team Design Authoring option results in an error5 M6 M- }6 x$ m, _: H; Q
1550052 ALLEGRO_EDITOR PLACEMENT        PCB Editor crashes when copying symbols
- |8 r1 {0 O9 B# B; b$ @1551635 CAPTURE        TCL_INTERFACE    GetSelectedPMItems returns error for design cache objects+ D/ [. |4 n  h, m) W/ N- m
1553027 ALLEGRO_EDITOR UI_GENERAL       PCB Editor canvas stops responding for tasks such as resize and workspace switch
* Q' f) ?' C% t9 y2 {1555246 ADW            DBEDITOR         Part Copy As does not copy AML and reliability model relations.$ @" W8 s$ Y" _' ^8 v
1555254 ADW            DBEDITOR         Text in Free Text search box is removed if it loses focus
+ r8 t* R1 g5 \1557542 ALLEGRO_EDITOR OTHER            DXF export creates strange result for donut-shaped polygon  g# p7 N6 Q/ P8 L" T8 t' o
1573039 ALLEGRO_EDITOR INTERFACES       IDX returns control to the general interface prematurely during an incremental IDX export
) _& S, Z1 _1 r1580571 ADW            DBEDITOR         XML files continue to appear in flatlib even after the padstack/footprint models were released
: D- z1 R1 i& X# O1580580 ADW            LIBDISTRIBUTION  The .lis file contains references to old models even after they were purged.
! R9 d/ _* z+ w1582064 ALLEGRO_EDITOR UI_GENERAL       User-defined menus not working in PCB Editor 17.2& I* _& I6 G1 N. V
1582628 ADW            TDA              When one user takes an update of physical object while the other user is still checking in the object, TDO crashes0 X2 u; N% w+ r" Z
1582856 PSPICE         MODELEDITOR      Getting 'ERROR: [S2C3471] Base part library does not exist when Export to Part Library', though olb is created
4 b  g% H" j. A1584719 TDA            CORE             Caching errors are flagged for a board-ref project during block update7 C1 f$ z! q( O5 ^
1587045 CAPTURE        IMPORT/EXPORT    Unable to import PDF file3 R; T3 @# M/ r/ w2 g& \6 |1 Y
1587259 ALLEGRO_EDITOR UI_GENERAL       axlUIMenuFind not working correctly for the 'bottom' option# H- I3 ^3 t) k1 _
1588736 PSPICE         MODELEDITOR      The Model Import wizard displays 'Invalid configuration' message when a .lib file is opened in Model Editor6 D8 e$ t! C1 ^' i; I; q
1588742 PSPICE         PROBE            Browse icon is missing from PSpice File - Export - text; d" i2 y& F+ h; Q5 Y
1590006 ALLEGRO_EDITOR UI_GENERAL       PCB Editor 17.2 crashes when multiple browse windows are opened
2 s) _  P* ]) X5 m& A1590597 PSPICE         PROBE            Problem with the adaption in the Probe Window icons( R. H$ y) [/ }: `
1591264 ALLEGRO_EDITOR UI_GENERAL       Film order in Visibility View is sorted alphabetically and does not match the manufacturing artwork. U& [- ^4 @  h7 z( V
1592089 PSPICE         MODELEDITOR      Cannot get the PSpice DMI Model DLL while using PSpice DMI Template Code Generator
( R5 V8 d" b" n4 A, }0 l$ H9 H7 @1593436 ADW            DBEDITOR         Cursor does not automatically move to the model name cell when creating a new model/ j0 j- b5 A  E
1594076 TDA            CORE             TDO crashes on concurrent check-ins when one of the blocks was not modified.1 `7 ?7 h7 O# J4 Y: l1 |
1595987 ALLEGRO_EDITOR PLACEMENT        Subclasses not getting updated in Placement Edit mode
1 C% ?" Z5 f% M$ U9 I, W( w1596162 ASDA           IMPORT_DEHDL_SHE Importing sheets from DE-HDL imports the block as well3 ^+ h# Q' a4 F
1597000 CONCEPT_HDL    INTERFACE_DESIGN Renaming a NetGroup does not work if several segments of the NetGroup trace have the same netnames assigned.
8 l5 v; H* G+ r1597406 ALLEGRO_EDITOR SHAPE            Dynamic Shape does not void the traces and voids open areas
1 h0 j: U5 G/ G1597957 ALLEGRO_EDITOR PLACEMENT        Quickplace: placed and unplaced counts not getting updated. s, m9 E; L2 U" {& d7 A6 H
1600194 ALLEGRO_EDITOR DRC_CONSTR       'drc update' gives a different DRC count each time the command is given in a multiple-cpu system0 s* ]$ D5 v4 w/ ^  [+ t$ R
1600800 ALLEGRO_EDITOR GRAPHICS         LINUX 17.2 operation of Update DRC is not the same as Windows – graphics not updating+ ~& O/ R1 ]# R; M! I
1602605 CONSTRAINT_MGR OTHER            OrCAD: constraints not getting saved
! g7 G% w( }3 }7 @5 H; L1602801 SIG_INTEGRITY  OTHER            Dielectric Warning message when opening SiP tool.
9 [( T) R+ p# o( [  S1603377 PSPICE         ENVIRONMENT      Running simulation with the 'At Markers Only' option does not generate the .dat file
; o* a0 [" d& s" ?2 F, _1604166 CONSTRAINT_MGR CONCEPT_HDL      Audit ECSets does not work from 'Referenced Electrical CSet' column header
' a1 b$ N% x2 K- S1604741 ASDA           CANVAS_EDIT      Tcl console changes the present working directory when you open Project Preferences and close it.& K4 y% b6 q; W9 m8 e
1605310 TDA            CORE             Join Project wizard: Random crashes in the Team Design Authoring option
9 ~3 J2 X% T6 y! T+ @# F1606861 CONCEPT_HDL    CORE             DE-HDL crashes on Linux during the Generate View operation0 U/ k' I! u" Z6 u! y/ f
1606917 CONSTRAINT_MGR CONCEPT_HDL      Importing tech file in DE-HDL Constraint Manager is creating a duplicate 'DEFAULT' cset, p2 Z0 w/ F( l
1607157 ALLEGRO_EDITOR INTERACTIV       Edit - Change allows lines to be copied to Cutout subclass, but that subclass requires closed polygons
3 ^4 `* C/ F* _0 u3 y1607330 CONCEPT_HDL    CORE             Variant view schematic PDF corrupted with attach_props set4 p' M; m8 _+ j  f5 d3 q7 K7 H
1607568 ALLEGRO_EDITOR NC               PCB Editor shows wrong drill legend for Top-to-Top drill' l/ T& r0 y: f  P: u1 o4 F5 M. O
1607986 CONCEPT_HDL    SKILL            cnGetSetupProjFilePath: The SKILL routine does not deliver the full qualified path and name of the project in 17.2
1 w) w9 C6 u& G( F2 @9 i" u1608524 SIP_LAYOUT     MANUFACTURING    The Display Pin Text tool fails in the 16.6.073 version with a parseString error.
7 x/ n, ]0 e& B1609400 ASDA           CANVAS_EDIT      The 'Assign Differential Pair' right-click pop-up menu command should be grayed out when a single net is selected" F# @3 h- O( |, s  a
1609809 ALLEGRO_EDITOR UI_GENERAL       Crash in Allegro PCB Designer version 17.2-2016 on Linux
7 a/ i7 C" }& _% g1609856 ALLEGRO_EDITOR ARTWORK          Embedded paste and soldermask showing up in both top and bottom gerber files.6 t6 |; W4 P9 s6 ]$ N. A" o
1609922 CONCEPT_HDL    INFRA            Launching Model Assignment crashes DE-HDL when the temp/edbDump.txt is read-only. w3 {! N2 U" _6 ?- e
1611226 ALLEGRO_EDITOR SYMBOL           PCB Editor gives a crash message while saving a flash symbol
) `0 M0 t3 A" a1 T% k; p1612108 ALLEGRO_EDITOR OTHER            Netlist Import is crashing with the .SAV message.9 v5 I+ l7 q7 K: l3 d
1613123 ALLEGRO_EDITOR SKILL            DrillType for Oval Slot should be 'OVAL_SLOT' not 'OVAL SLOT'4 M/ g; i/ K; T
1614000 ADW            LIBDISTRIBUTION  Library distribution (lib_dist) does not complete; lib_dist.lck cannot be deleted when Configuration Manager is running; X* ]7 \9 k$ p
1614667 SIG_INTEGRITY  SIMULATION       Different results from Probe in Allegro Sigrity SI and SigXplorer
9 @2 Z" A) {  s' H# u1615601 GRE            IFP_INTERACTIVE  Delete Bundle then try to delete plan lines results in fatal error
* }( d, B+ G& f6 R6 W- ?- }1616235 ORBITIO        ALLEGRO_SIP_IF   oio2sip import does not map layers correctly
/ [" w; Q" i% l% m1616540 SIP_LAYOUT     DRC_CONSTRAINTS  Same net DRC Line-to-Line reappearing after dyn shape update7 \( w# g! E6 `7 p) u1 C
1616733 ALLEGRO_EDITOR INTERFACES       'genrad output' no longer working in 17.2. Gives the Error 'extracta process failed. Command terminated'
5 h3 b& u. \3 F, _7 E1618751 ASDA           DRC              Zero Node Net errors flagged when DRC checks are run, though RETAIN_ZERONODE_NET is set to 'NO' in Site CPM file) \( U% E: g. `* v
1618797 ADW            FLOW_MGR         Flow Manager cannot execute a specific command in 17.2.4 s- [) z5 v+ e( ]0 P
1618930 CONSTRAINT_MGR INTERACTIV       Hovering over row column cell causes the application to go into a not responding state.
1 F7 i7 H, o( p2 E/ Q1620350 ASDA           EDIT_OPERATIONS  Pin number is lost on updating the version of a connector pin
3 V6 |: O: [+ s- _/ b1621963 ASDA           SELECTION_FILTER Selection filter: Pins in the symbol used in connectors are not selected- H2 ]! ^8 ?0 \! u6 B- ?  I
1622715 CONCEPT_HDL    CONSTRAINT_MGR   Extracting an XNet crashes DE-HDL: z# c" @( u3 R8 l) @0 B  e, i
1625209 ASDA           IMPORT_PCB       File Import from PCB Editor shows board differences
" d% m7 Q0 V1 l
4 I4 P) \$ G4 @
6 G( u+ S0 S+ Y1 o9 ^/ O+ _: w, b/ ?Fixed CCRs: SPB 17.2 HF0031 f; \. @: E6 w7 e+ s8 S
07-28-2016
7 ?) ?& c# i. C===================================================================================================================================+ O% `% n. r/ y0 V
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE- G$ T& Y& z! j
===================================================================================================================================
  `; }; `. V$ V5 {5 {1423889 ALLEGRO_EDITOR EDIT_ETCH        AiDT gets poor routing result" I4 m3 u! [& v. v. L5 ^6 O
1461626 CONCEPT_HDL    CREFER           Cross-references shown to the same pin on different block instances though the signal names differ9 |$ Z' Y% C% p' j) c
1472456 CONCEPT_HDL    CORE             The design connectivity (XCON) file and design data are not in sync0 K" W* w2 ?7 G  f, Q0 U- w
1546151 CONCEPT_HDL    CORE             Add port, Genview, move pin on block - the pin name disappears
/ X8 o- W, O! N8 V2 h1 t3 G6 Y# l1547356 ALLEGRO_EDITOR EDIT_ETCH        AiDT gives different results in ISR S034 and S0663 s& t% B3 ~9 w/ F/ A/ G! @
1560102 ADW            FLOW_MGR         Flow Manager: None of the eval commands working; A2 J8 Z6 w! s) l
1570032 ALLEGRO_EDITOR GRAPHICS         3D Viewer shows flat LED for a specific design
3 o* W1 y% h* J! H1574676 ORBITIO        ALLEGRO_SIP_IF   Updating the OrbitIO database with a modified .sip file gives errors
3 b  t; M- E) C/ {9 C# Q1578876 ADW            ADWSERVER        Component Browser crashes when trying to show details of a part number
8 t: o$ D/ n+ o1 ?- A# v2 b1580744 F2B            PACKAGERXL       Running Export Physical results in error SPCODD-114  u3 }7 M; V& G! k
1582863 CONCEPT_HDL    CORE             Generate View creates non-existent ports! s* |# }! T, [) U) ?& k
1584317 CONCEPT_HDL    CORE             Provide an option to open pxl.log from the Design Sync window when packaging does not complete successfully! h' ?' a% j0 j/ `" l' l
1587018 ADW            FLOW_MGR         User is prompted to specify the flow name each time the project is updated8 r  _/ S5 ^1 p5 s% h* d
1587157 CONCEPT_HDL    CONSTRAINT_MGR   pstprop.net reports conflicts on nets with VOLTAGE properties( T) W1 W# j) A) A9 p  W
1587498 CONCEPT_HDL    INTERFACE_DESIGN Need the ability to tap individual bus bits) }/ a. @+ t& u2 V, Y: G# m4 _+ o4 `
1587718 ADW            LIBIMPORT        Library Import - The Pre-analyze tool does not report errors1 q1 V# V0 Z( f- o; b
1588197 ALLEGRO_EDITOR INTERFACES       STEP export fails when External copper is selected on Windows 10
4 Z- n3 m/ t5 k4 N5 T" F, J5 ]1588786 ALLEGRO_EDITOR OTHER            strip_design reports 'Design has been corrupted'
" M( v' T& {& s9 J; {1589252 CONCEPT_HDL    CORE             Search results zoom into the page origin instead of the selected components
0 U; r# j2 Q1 @, j+ T& [" F1589318 ALLEGRO_EDITOR DRC_CONSTR       Via to SMD Fit DRC reported between embedded pin and via which do not share layers/ ^- I) f- I( @6 b: Z( }
1589979 ADW            FLOW_MGR         Design Name change does not reflect in Flow Manager in the same session of a project0 A( U) r3 I1 [$ X8 `
1590538 CONCEPT_HDL    DOC              Open Archive: Some observations on the random behavior$ v. f) v, r$ p3 W* e
1590639 CONCEPT_HDL    OTHER            Importing a design in DE-HDL results in a crash
1 {( a& M* ]! b8 ^; Y* e1590651 CONCEPT_HDL    INTERFACE_DESIGN DE-HDL: Duplicate NetGroups created in Interface Browser and Constraint Manager
) f4 t' [/ ]# ]. T: Q4 u; v4 D6 |1590720 ALLEGRO_EDITOR INTERFACES       Exported Text Size Parameter file does not load names into the text table
  p3 h: R7 C( r1 @( T1591070 PSPICE         PROBE            PSpice crashes when using the Trace - Measurements - Evaluate command
+ C5 O  U! l* P& s" B1591223 CONCEPT_HDL    CORE             Variant information for lower-level schematic not displayed
$ J1 v' o" C# R2 S! Q) \$ N; b1594240 CONCEPT_HDL    ARCHIVER         Archiver is not able to change the permissions of the cells archived5 E, Y, s" d: d& o& m+ d* y9 u
1594416 ALLEGRO_EDITOR PAD_EDITOR       Padstack Editor crashes when you create a new pad- b; a, b. `. {7 e  Y/ Y. f
1596615 ADW            DBEDITOR         Unable to search parts: Component Browser did not launch; Database Editor did not return search results
9 e9 Z) G7 N2 {* V1596780 ALLEGRO_EDITOR SKILL            PCB Editor crashes after doing SRM update and save- a/ ~( a* e( h
1597153 F2B            DESIGNVARI       ERROR SPCODD-53 in Variant Editor
, V. c, }" w+ n3 f3 {1 n1597385 F2B            DESIGNVARI       Some 16.5 variant DNI parts appear in 16.6 as X-OUT and some without X-OUT or DNI/ r- K# }& u0 i9 [0 i1 J/ `
1598629 F2B            PACKAGERXL       Export Physical crashes after flagging error SPCOPK-1458
( V8 Z+ c; \3 R$ r, J+ k1599452 ALLEGRO_EDITOR ARTWORK          Import Artwork with Mirror option does not import pins or shapes
& G2 p: ?! E9 q1599744 ADW            FLOW_MGR         Flow Manager: Commands associated with some of the buttons not working
& o: S3 m" K% h" d$ z1599950 SCM            OTHER            Adding the GND net to parts/pins takes a long time.
+ f0 T! \% s5 T. Q5 ~7 l0 d1600226 RF_PCB         AUTO_PLACE       Fail to auto-place RF group- S0 z( q% w8 |9 X
1600618 ALLEGRO_EDITOR DRC_CONSTR       Casing of property names is affecting results when working with Physical Constraint Set
/ g/ T1 t: c, G! e7 _% P4 |1600914 ALLEGRO_EDITOR INTERFACES       Exported PDF has unfilled shapes despite enabling the 'Filled Shapes' option0 b. N. j2 s! o. t2 G
1601165 ALLEGRO_EDITOR DATABASE         Thermal Relief is not added for Rounded Rectangle pad8 k  I4 C0 o1 N! W# m
1601281 ALLEGRO_EDITOR OTHER            STEP model link gets corrupted with SKILL axlLoadSymbol
0 B' b; e# U; t! q1 E1601282 ALLEGRO_EDITOR OTHER            Export Libraries will not export device files when there is a space in the folder name.
# C/ r8 t7 }! P  F7 _' g/ ^1602514 PCB_LIBRARIAN  METADATA         References to some primitives missing in block metadata;TDA errors reported for missing parts after joining a project0 R% u1 ]+ t  m( O
1602823 SIP_LAYOUT     WIREBOND         SiP crashes when using the Add Wire command' i7 [5 q* O4 P; o! j) a. d8 t
1602955 ALLEGRO_EDITOR SHAPE            Shape to Route Keepout DRC not reported for attached database  C- \3 [) F4 T* c
1604223 CONCEPT_HDL    CORE             Tool stops responding after error SPCOCD-553: Connectivity Server Error4 M" V  _$ W- ?
1604746 ALLEGRO_EDITOR OTHER            In 17.2, layer data is getting changed when importing extracta files into other thirty-party extraction tools
) @; s5 Q! s/ i( I, J; t1605322 ALLEGRO_EDITOR TECHFILE         Generating tech file in 17.2 takes much longer as compared to 16.6/ J, c# s6 j4 d. ]( @
# G4 ~; A4 k! v4 s& X- M

$ J* D/ D# i0 v: c2 iFixed CCRs: SPB 17.2 HF002. a$ U5 x6 j7 G# M3 m  @& j; x
06-31-20165 N0 J) U3 O$ D. o2 F# p+ J
===================================================================================================================================4 J* V* V/ r) ]0 {; f( Q% W$ `! i
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE8 E# L7 y5 {+ }% q: g0 h
===================================================================================================================================
' L, [! T0 B6 b5 M1452838 CONCEPT_HDL    CORE             Apparent discrepancy between Bus names and other nets
2 C) [% {, v+ |3 X: h& Y# z# T3 m* O1469146 ADW            LRM              Packaging error reported after updating the design using LRM7 C3 D4 F; t/ s2 L* D9 e% K
1481802 ORBITIO        ALLEGRO_SIP_IF   Import of an OrbitIO file to an existing SiP file offsets the results incorrectly9 w$ F* `( x& A: I
1518957 APD            SHAPE            Shape void result incorrect% a' u  m: b' O2 {( x
1519155 ALLEGRO_EDITOR OTHER            IPC-2581-B Negative Plane Error
3 U1 T' c, p3 I& F/ K6 c: q* d5 Y1524947 SIG_INTEGRITY  SIGNOISE         Custom Stimulus is not recognized correctly in Allegro Sigrity SI or PCB SI.& p5 M0 A: g& T3 P8 ?( }
1532162 CONCEPT_HDL    CORE             The Rename Signal command does not update split symbols.
: V) R0 d. _2 P$ v5 _1543997 CONSTRAINT_MGR OTHER            Import Logic is overwriting the constraints in the attached design.
1 x# w( @! `8 z3 x" P) J1544675 ALLEGRO_EDITOR OTHER            Export Libraries corrupts symbols if paths do not include the current directory (.)0 Z* z$ Y- X5 A& w* }
1549097 CONSTRAINT_MGR XNET_DIFFPAIR    Show warning message if differential pairs are created for nets with voltage properties; y8 V8 P# Y/ W% Y* L0 x7 u" C& q. C* r" p
1551934 ALLEGRO_EDITOR SKILL            axlBackDrill command is not analyzing new layer set when application mode is set to 'None'& _. l) z0 c, w% x+ e! C3 Q# `
1554919 ADW            LRM              LRM does not find PTF data for cell 'res' in the reference library
1 y+ }# [7 s. I# l" U0 t1555009 CONCEPT_HDL    INTERFACE_DESIGN Unable to rename a NetGroup.& w6 D# F; m1 H
1559136 ALLEGRO_EDITOR EDIT_ETCH        Cannot connect floating clines to vias with nets
$ o+ N1 T) Z, D+ W3 X8 ^6 ~1559552 SIP_LAYOUT     ORBITIO_IF       device offset in oio2sip translation
, m) C; _& n- J/ l2 R2 P( m& Q1560301 CONCEPT_HDL    CORE             DE-HDL hangs when Edit menu commands are called on Linux if xclip is open
$ A9 [4 w1 `: W/ ~! \) K0 C1560804 ALLEGRO_EDITOR OTHER            Film records order gets reversed when using File - Import - Parameters after File - Export - Parameters6 F: ^8 a9 D% H$ l, O; P
1561501 ORBITIO        OTHER            OrbitIO stops responding when refreshing a design in SiP Layout
- c' j! G) j! S7 t, ~7 y% G* S1564036 CONCEPT_HDL    CORE             User-defined custom variables are not getting populated in the TOC
9 S& n; f  o1 K1 u/ X1564545 CONCEPT_HDL    OTHER            Signal model property deleted from an instance is not deleted from the instance pins. W" ~6 ^0 O$ p" K: H: r5 O
1564552 CONCEPT_HDL    CORE             Find Net should zoom to the nets on schematic canvas; @0 L% b! \- P: R2 e
1566119 CONCEPT_HDL    CORE             Right-clicking the schematic to add a component does not show all the schematic symbol versions( p& M1 {0 e" f) \3 ~7 s
1566848 ALLEGRO_EDITOR ARTWORK          Board Outline artwork is incomplete
6 M/ L: O4 N4 k  a7 A: X9 ?1566942 ASDA           MISCELLANEOUS    Several extra files in the /tmp/ folder on Linux/ e# e2 l( S/ P. b0 u$ j
1567290 ALLEGRO_EDITOR MANUFACT         Import Artwork fails to import a shape.) }7 v! z. Q! v) b6 m6 l9 Y6 @
1567587 ALLEGRO_EDITOR MANUFACT         Extended tool name in header of drill file is not correct
! ~' a& B7 ~1 J1569056 CONCEPT_HDL    CORE             Opening the same drawing in multiple cascading windows view displays non-existent artifacts
. X6 |( N1 _5 k6 s8 b( w+ W8 D1569087 ALLEGRO_EDITOR DRC_CONSTR       Running DRC Update gives the message 'Figure outside of drawing extents. Cannot continue.'
) V1 l" |: d6 [$ `4 L" S) K1569147 CONCEPT_HDL    CORE             The signal name auto-complete drop-down list is not displayed correctly# a& z( |: w* O. l
1569394 ALLEGRO_EDITOR SKILL            axlPadSuppressSet( 'on 1 '(via)) not working on SPB17.2. I4 \. i' g% O5 I3 Y
1569924 CONCEPT_HDL    CHECKPLUS        Checking in a large BGA into ADW results in an error related to negative signals' Y$ g+ D( T3 v' I8 |4 ^! c" F
1570398 SIP_LAYOUT     DATABASE         Diestack layers cannot be deleted if there are unplaced symbols in the design# ]: Y+ W3 y' t9 W5 v! ?
1570419 CONSTRAINT_MGR CONCEPT_HDL      Need to add a customized worksheet custom property weblink in Constraint Manager
' G$ ?- w; b6 {1 c' U' ^% L1570624 APD            ARTWORK          Artwork file has missing voids on a layer and is causing a short0 U! j3 ~- z; t6 W6 e
1570678 F2B            DESIGNVARI       Variant Editor: Error when adding an RSTATE property
+ C, C) ^0 l& n. V1571113 CONSTRAINT_MGR DATABASE         Reports generated from cmDiffUtility show the differences in mm units only
9 j- v) U: }/ G" F4 L1572593 ALLEGRO_EDITOR ARTWORK          ARTWORK: 'Draw holes only' option does not match display
9 _) l$ J$ I# h9 }; W  X& e1573127 CONCEPT_HDL    COPY_PROJECT     The CopyProject functionality creates an incorrect 'view_pcb' directive value
9 T) T3 L2 N7 t$ Y8 Z5 t1573205 CONCEPT_HDL    CORE             dsreportgen is unable to resolve the physical net names (PHYSNET). V& ]0 l6 u6 W/ I9 x. N" T6 Y
1573625 CAPTURE        PROJECT_MANAGER  Toolbar customization is reset when Capture is re-invoked in SPB 17.28 o# E) U, J1 l: M; f2 v5 P
1573755 ALLEGRO_EDITOR CROSS_SECTION    Changing a layer's type is also changing its material in Cross Section Editor1 p2 |! F. \$ g/ T+ S
1573970 CONCEPT_HDL    ARCHIVER         archcore fails to archive the project CPM.arch file
8 H' N6 r0 C8 K, x+ J1574381 CONCEPT_HDL    OTHER            Packager crashes on repackaging a design with RefDes related advanced settings
/ l/ L. V* |9 }: ?2 _1576100 ALLEGRO_EDITOR SYMBOL           Update symbol crashes, creates '.sav' file, but shows update was successful in 'refresh.log'; q( j" E2 u/ G( Z: m4 H. c# U0 M3 `( G
1577381 CONCEPT_HDL    CORE             ERROR(SPCOCN-2128): The NetGroup structure does not match the PortGroup structure: m7 Y- ~4 v. \! t; r4 N0 p5 ^
1580103 ALLEGRO_EDITOR DATABASE         dbstat of 16.6 does not recognize 17.X files
, f6 k+ Y3 i. h0 b' s1580891 SCM            REPORTS          Dsreportgen crashes in different scenarios
+ L, y/ I# n5 n$ P" ^* k8 ]1581254 SIP_LAYOUT     CROSS_SECTION    Cross Section Editor crashes when adding a layer
' e$ f9 f. U( I& _, l" o1584957 ADW            FLOW_MGR         17.2 Flow Manager, JavaScript - Tool Launch Error% ?9 `& S0 M; {3 [1 ]
1588823 ADW            FLOW_MGR         Flow Manager: In 17.2, using back slashes in the UNC path results in problems in working with the tool
/ Y2 z: H1 v$ W, i$ a" ?8 X" N1590064 ADW            LRM              Allegro EDM Flow Manager - An empty LRM dialog opens on design load in 17.2
; w0 R( c, V3 f* R9 K( r4 ]  P8 X: ~  |. |2 o% z( }
( B, U6 t  ?, Q6 [. S9 A& N  _
Fixed CCRs: SPB 17.2 HF0012 X5 r0 r0 X" ^( b* z8 _4 O
05-06-2016
% x: c  I1 ^. @* I& r4 `& x( w0 E: d===================================================================================================================================
: m5 r# |$ ~1 p1 G) h& kCCRID   PRODUCT        PRODUCTLEVEL2   TITLE
. u; |, p( l8 v2 M===================================================================================================================================
2 a3 \. d- A5 E: M) W1272355 F2B            DESIGNVARI       Property changes on replaced component shows incorrect result in BOM output
& g: V0 }% D8 q* a7 a/ c" b/ K1482953 ALLEGRO_EDITOR DATABASE         Part change disassociates parts from Group
; R" \5 D' t- h7 w+ s7 U" H1484075 ALLEGRO_EDITOR PADS_IN          'pads_in' imports ASSEMBLY_TOP  and PLACE_BOUND_TOP outlines that are defined as shapes as lines
. P, v- r2 _- m# r) [) i1488909 ALLEGRO_EDITOR DRC_CONSTR       Test Via causes net scheduling verification to fail) `; p+ q" D5 O* r2 l, \
1498389 SIP_LAYOUT     DIE_GENERATOR    Provide the ability in the 'die in' command to specify flip chip as a DIE symbol8 Z" R' R; _. \% n) L! B+ L
1499515 ADW            COMPONENT_BROWSE The Search Criteria property value is automatically being set in the ADW Component Browser
! H/ `' O. C/ N' T1506672 ALLEGRO_EDITOR INTERACTIV       In the attached board file, when using Replicate Place, some shapes are missing from some layers# @# d" u( Y# C8 b; g4 A0 k
1522411 FLOWS          PROJMGR          License selection should persist on invoking Layout from Project Manager
! n' d& s* ]0 ~& I" C9 `1 k1523532 F2B            PACKAGERXL       Adding subdesign names in the 'Use subdesign' or 'Force subdesign' sections hangs for more than a minute( T- e4 ^& [" B4 \
1525783 CONCEPT_HDL    CORE             '\BASE' scope does not work for SYNONYMed global signals
7 M8 I/ y; \$ x4 L1526729 SPIF           OTHER            Exporting a dsn file causes PCB Editor to crash in the interactive and batch modes
  i+ e" ^: H7 W1529846 ALLEGRO_EDITOR SHAPE            Some shapes are not generated in the artwork
: j0 L+ ~3 }1 V1 m; E9 ]# B1537499 CONCEPT_HDL    CORE             Adding the same version (already placed) with the same split block name should not be allowed4 c: B* }9 u8 h2 g
1541589 ALLEGRO_EDITOR INTERFACES       STEP model incorrectly shown in 3D viewer. Shows pins as angled.! B$ P  a% Q) i5 n0 R' a0 [
1542334 CONCEPT_HDL    CREFER           creferhdl leaving lock files in sch_1 folder. z5 ~, y( c$ ?4 o0 K/ x
1542722 ALLEGRO_EDITOR INTERFACES       IDX export: RefDes and PART_NUMBER missing for mechanical symbols9 {1 K0 R& o1 D" @, O# _  ~! X
1543410 ADW            LRM              LRM shows confusing part status; reports that update is needed but clicking update does not work- m' W$ {8 w8 i* S
1544614 ALLEGRO_EDITOR SKILL            Associative dimension data reaches the 'psm' file despite deleting the layer on which it was set in the 'dra' file
" P& e8 ^* P6 N2 G" x0 ^+ w/ K+ }1545370 APD            OTHER            Pads in .mdd file getting placed on different layers as compared to the design9 V& _: S7 {! S& l- P7 M
1545909 ALLEGRO_EDITOR UI_FORMS         Show 'microvia' checkbox in 'Blind/Buried Vias' form only with the 'Allegro_PCB_Mini' license3 y' Y5 b) ^" n) S( e1 D
1546141 ALLEGRO_EDITOR SHAPE            Shapes missing from Artwork4 c) n0 \5 h+ |* ^! K5 n
1546877 CONCEPT_HDL    CORE             Align Left on wires fails with incorrect error message% Q+ s$ q+ Y: a/ v6 y
1547224 CONCEPT_HDL    CORE             Lock the 'PATH' property once it is assigned by system6 D3 {$ r" \' ^0 A4 ~
1547584 SIP_LAYOUT     OTHER            SiP - Design Variant: Delete embedded layer if not selected
, J! N5 {8 n2 _, ]3 `9 Y1548116 CONCEPT_HDL    CORE             Some versions of Technology Independent Library do not appear when adding a symbol
& O* D9 h6 V1 Y) H( H5 Y1548151 ALLEGRO_EDITOR INTERFACES       Exporting a step file gives a component rotation mismatch in the *.stp file
0 o! B$ G" j( F3 `! j9 }- d1548421 F2B            BOM              Parts with same 'BOM_IGNORE' set do not behave the same way in the BOM report9 }# d# b' V- z" B0 h
1548978 ALLEGRO_EDITOR MANUFACT         Shape not voiding clines
( q; X: W$ S4 [* I) x1549662 ALLEGRO_EDITOR OTHER            Import Parameters Path fails if parampath does not have the current directory (.) set+ _$ ^# ^+ U; L
1549836 CONCEPT_HDL    CORE             Tools - Customize - Keys - Reset does not reset keyboard shortcuts$ l% e, C+ b* a$ l+ {0 T
1550941 PCB_LIBRARIAN  PTF_EDITOR       PDV Part Table Editor new column sorting causing problems- O3 j7 ~% [/ f2 j3 n( b
1551713 ALLEGRO_EDITOR DRC_CONSTR       Hole to Hole DRC between via and pin not shown
! _7 z0 t5 ~" X* ], ?1553950 ALLEGRO_EDITOR SKILL            Executing axlUIControl(pixel2UserUnits) crashes PCB Editor  r0 O9 V  V' u, Y# p4 Q
1554333 CONCEPT_HDL    CORE             Changed connectivity error when aligning ports attached to NetGroups6 E0 b3 c2 C& c2 p9 Q& h- j
1555092 SIP_LAYOUT     DEGASSING        Degas offset is not working with hexagons6 m. _' U* A# W; o& n, T0 \
1556261 ALLEGRO_EDITOR DATABASE         DBDoctor crashes with the error 'Illegal database pointer encountered, Exiting DBDOCTOR.'
# I4 u, G, ^& I1 j: B4 L; `( D1557716 APD            OTHER            Stream out fails with request to terminate detected - Program aborted$ `- b2 k% m( E- y9 h
1559951 SIP_LAYOUT     SYMB_EDIT_APPMOD Wrong bump locations after Symbol Editor - Refresh co-design die8 }1 b* s) t, y3 _6 R
1560197 CONCEPT_HDL    CORE             BOM-HDL adds extra characters to subdesign_suffix when generating hierarchical BOM
9 L6 D$ Y0 e) \3 q3 \  I; \1561077 ALLEGRO_EDITOR INTERFACES       Beta - IDX User Layer export fails on Linux6 u. b" f  d  ~  C2 X% m5 T
1562537 ALLEGRO_EDITOR MENTOR           Using mbs2brd in 16.6 gives a fatal error
8 ?- m  {9 \  h9 s% i1564203 ALLEGRO_EDITOR ARTWORK          Cannot generate negative artwork
1 `# K7 p* Z3 n: y
作者: th2010-gc01    时间: 2019-11-5 15:24
lilacbear 发表于 2019-11-5 14:06
/ G4 A+ ]7 j# V5 W% EReadme for SPB Release version 17.2. K) l8 P( N9 x  J
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Copyright (c) 2019 Cadence Design Systems, Inc.
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牛！不是一般的牛！
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作者: 鲫鱼3525    时间: 2019-11-5 16:01
终于翻到头了
作者: leilei4908    时间: 2019-11-8 16:08
lilacbear 发表于 2019-11-5 14:06) \% }8 D+ t( e5 V- P
Readme for SPB Release version 17.2
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Copyright (c) 2019 Cadence Design Systems, Inc.

+ ^$ y  L2 `/ Q1 }哇塞，大佬都整理过了啊。。。牛牛牛！！！



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