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标题: Hotfix_SPB17.20.054_wint_1of1.exe [打印本页]
作者: yangquan3    时间: 2019-5-3 15:45
标题: Hotfix_SPB17.20.054_wint_1of1.exe
本帖最后由 yangquan3 于 2019-5-4 15:13 编辑
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( Y+ w0 O4 f0 _; X+ ?6 _Hotfix_SPB17.20.054_wint_1of1.exe( b7 f8 X8 {/ O! k4 s
下完了
& E9 W  ?. p' x% a+ ]链接: https://pan.baidu.com/s/1r_llgvrGH_bebfSWaR7_5A 提取码: jpbn 复制这段内容后打开百度网盘手机App，操作更方便哦
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作者: th2010-gc01    时间: 2019-5-3 16:18
更新得真快啊！
作者: ethernet    时间: 2019-5-3 16:37
更新頻率真是令人嘆為觀止。。。
作者: llntech    时间: 2019-5-3 17:16
good
作者: llntech    时间: 2019-5-3 22:06
good
作者: 逸步舞秋风    时间: 2019-5-3 22:06
给个网盘链接把 威望太贵了
作者: kewin_wang    时间: 2019-5-3 23:07
感谢楼主！
作者: 金志峰    时间: 2019-5-4 01:00
楼主貌似下了几天了。。。
作者: 金志峰    时间: 2019-5-4 01:01
麻烦先发个ccr看看吧
作者: Geant168    时间: 2019-5-4 02:13
great
作者: vasylll    时间: 2019-5-4 03:32
thank
作者: Deny    时间: 2019-5-4 03:49
thanks
作者: linguohua    时间: 2019-5-4 05:27
本帖最后由 linguohua 于 2019-5-4 05:29 编辑
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金志峰 发表于 2019-5-4 01:01
% T" h# ~) K8 ~) p9 ?2 y麻烦先发个ccr看看吧
抱歉，本来想复制到回帖里面，发现格式全乱了。因此直接看下面连接比较好：
, P! o- {, s" p# G  F. [https://electronix.ru/forum/index.php?app=forums&module=forums&controller=topic&id=138247&page=5
作者: linguohua    时间: 2019-5-4 05:27
金志峰 发表于 2019-5-4 01:01& P7 B6 G: j( i2 M
麻烦先发个ccr看看吧

- c" g' w% B! t7 |https://electronix.ru/forum/index.php?app=forums&module=forums&controller=topic&id=138247&page=5
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作者: linguohua    时间: 2019-5-4 05:29
Fixed CCRs: SPB 17.2 HF054
% t7 M% }. [5 M; M/ K04-26-20197 |4 U; I2 T# Y  Q* V- U
========================================================================================================================================================
. S) N7 v: F$ a5 n# [/ S" ACCRID   Product            ProductLevel2 Title
( O( q+ Y6 D5 b( }========================================================================================================================================================
3 u. l8 |- k2 {$ d' r2060269 ADW                DBEDITOR      Unable to create ECAD type mixed-case schematic model attributes
3 U, v3 ]% a. g- J4 |2030086 ADW                LRM           Cache part_table.ptf made by LRM Update cannot be read if it has null value in key property. f; l# b9 @5 w$ g  f5 Y$ ^
1975317 ADW                PART_BROWSER  Space at the end of line in CDS.LIB results in zero libraries being shown in new component browser, V9 z4 }  X$ D! z2 U
2076340 ADW                PART_BROWSER  .helix folder needs to be deleted for PTF changes to take effect and to convert a design to cache* M6 U0 x% z/ G" N# ~, n$ _
2025147 ADW                TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name  j$ m7 E9 E7 E: X5 m' v) q: L
2025201 ADW                TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design
9 Q2 q; {5 n7 g# A9 ?6 e; Y2056694 ADW                TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object
( ?4 F9 d% G, y9 R3 Q# Z2054243 ALLEGRO_EDITOR     3D_CANVAS     Plating is not shown on stacked vias in 3D canvas  w& l* t2 Y( ]7 _
2054327 ALLEGRO_EDITOR     3D_CANVAS     3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation! Z) \4 ?7 R, s/ `9 T, l
2044980 ALLEGRO_EDITOR     ARTWORK       'Import - Artwork': PCB Editor stops responding and no artworks are loaded
& p' [+ ?8 }; u: J) A# y2060489 ALLEGRO_EDITOR     COLOR         SKILL axlGlobalVisibility() issue in a partition file: VIA/SOLDERMASK_TOP subclass visibility not turned off
. N7 x- C: J) a% Z2 W3 N2072695 ALLEGRO_EDITOR     COLOR         Clines of colored nets not colored when 'display_nohighlight_priority' is set
% S1 |8 v8 E% y2061203 ALLEGRO_EDITOR     CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone
4 A. G7 B% H4 C0 s" r$ P6 v8 e2010812 ALLEGRO_EDITOR     DATABASE      PCB Editor STEP model offsets should follow origin movements8 k9 d  n3 z; `0 m% ^
2011993 ALLEGRO_EDITOR     DATABASE      Change STEP model mapping when Symbol Origin is changed in DRA using Setup > Change Drawing Origin
! W# N. o% k0 e5 G! T2051596 ALLEGRO_EDITOR     DATABASE      Error for unsupported property in element, ]2 ~4 I9 ~, l* C% S( a$ K, _9 q
2056497 ALLEGRO_EDITOR     DATABASE      Place manual is slow- T7 V2 U2 N  X; ?5 }
2059489 ALLEGRO_EDITOR     DATABASE      DBDOCTOR in batch mode with argument '-check_only' detects text error1 ^1 ^2 x: y( m+ K% \6 p" V9 s+ L
2064268 ALLEGRO_EDITOR     DATABASE      PCB Editor crashes when running SKILL code" j+ H  a( q! o( }3 a3 k9 o
2068588 ALLEGRO_EDITOR     DATABASE      Crash on opening release 16.6 design in 17.2-2016
8 H  `5 X9 U3 x& U5 V' X4 U' z0 C2079131 ALLEGRO_EDITOR     DATABASE      axlChangeNet crashes PCB Editor in fast shape mode with Microsoft Visual C++ Runtime Library Error
" A, @- R/ T7 M3 f  G* [4 \2034759 ALLEGRO_EDITOR     DFM           Importing DFT constraints on board does not assign csets to design but shows the csets
5 C" I3 b! [5 `0 e) L; z7 }" _2039992 ALLEGRO_EDITOR     DFM           Cset is not set in Pastemask element of DFA when importing XML Constraint File.
6 Y# ]  o0 r5 M2 p. s2046824 ALLEGRO_EDITOR     EXTRACT       Extracta ECL_NETWORK View reports incorrect pin layer., f+ ]% H) B1 v  t
2048912 ALLEGRO_EDITOR     IPC           Running PCB Design Compare - Graphic mode reports ERROR (SPMHA1-273) 'Shape intersects with itself'
' Y1 x3 y- }' m- v+ i0 M2066597 ALLEGRO_EDITOR     IPC           Graphical compare not completed because of self-intersecting shape locations
$ b% C5 r. M( [8 z, N/ S. y  ]4 O0 y2079719 ALLEGRO_EDITOR     IPC           IPC2581 import fails with error 'Failed to add (LW)POLYLINE'
3 ]8 P; Y! L' L( ~' v7 C' Y2066229 ALLEGRO_EDITOR     NC            Tool code missing in backdrill NC file on choosing 'Optimize Drill Head Travel' in NC Drill
* |4 x8 d$ f# ~  M2070379 ALLEGRO_EDITOR     NC            After running backdrill some vias are shorted to other nets
' d2 D/ K. r/ ]$ a! U9 Y0 x8 d2041881 ALLEGRO_EDITOR     PAD_EDITOR    Difference in locations of drill in pad editor and symbol editor
) ]$ H2 @0 w8 Z3 N" w2058852 ALLEGRO_EDITOR     PAD_EDITOR    Net associations lost on refreshing vias0 P, n, W5 O" X* ~
2061580 ALLEGRO_EDITOR     PAD_EDITOR    Lock Layer Span settings specified in padstack editor not reflected in PCB Editor8 E3 L$ O( e5 u! S) R
2048116 ALLEGRO_EDITOR     REPORTS       Extracta command files not visible in Tools-->Reports when there is a space present in the textpath variable
. |6 }& W( l; w: Q7 Y2 ?$ P2038949 ALLEGRO_EDITOR     SCHEM_FTB     Netrev is slow if there is an input board file with many modified components* t% e& I7 x5 U' G/ ^3 f3 _
2052758 ALLEGRO_EDITOR     SCHEM_FTB     Connectivity objects are being reported as Added and Deleted in Constraint Differences Report# D0 Y, `4 q  w1 f+ U+ J8 u
2066099 ALLEGRO_EDITOR     SCHEM_FTB     Inconsistent net names on export physical after changing net names in DE-HDL* \" s0 f( N$ X: a! J
2043882 ALLEGRO_EDITOR     SHAPE         Shapes not updated to 'Minimum aperture for gap width' in Global Dynamic Shape Parameters window
' K4 t% t9 A  G' i/ y3 F2048483 ALLEGRO_EDITOR     SHAPE         Shapes not getting updated post backdrill update
+ }4 u! [  R; Q2 G) l2052063 ALLEGRO_EDITOR     SHAPE         Cannot import IPC2581 due to 'Shape intersects with itself'
8 K) G6 b# @) o9 `* ?2056478 ALLEGRO_EDITOR     SHAPE         Editing shape by sliding segment causes PCB Editor to fail due to 0-length segment in shape, u9 ^* A, j' u- u- P8 D( W
2058017 ALLEGRO_EDITOR     SHAPE         Shape not voiding correctly when fillets are present1 Q, Y& v2 w! y. F+ e1 `
2066473 ALLEGRO_EDITOR     SHAPE         Teardrops create strange copper shapes
; m- p5 x/ X( @* e! r1 q2079698 ALLEGRO_EDITOR     SHAPE         IPC2581 import fails with error 'Shapes intersects with itself'! T' ]: b+ a( F: C3 {9 q4 \/ {
2010569 ALLEGRO_EDITOR     SKILL         Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in HotFix 048.
* A$ c! H* l) [# h- o2055055 ALLEGRO_EDITOR     SKILL         Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash" \# \4 x- Q9 L$ {( P& g
2023755 ALLEGRO_EDITOR     STEP          Export STEP includes enclosure even when it is not selected.
- R  s  o* F. x0 x8 i- Y# W9 r; e% \1881233 ALLEGRO_EDITOR     UI_GENERAL    Green/white canvas without grid when creating a board file (File - New)# Q4 Z7 M; z* @& }. r4 n0 M7 J
1900525 ALLEGRO_EDITOR     UI_GENERAL    Resizing the update symbols UI causes the options to overlap and jumble up (refresh issue)
+ t; |  W$ Z( F1 g  a& m2003861 ALLEGRO_EDITOR     UI_GENERAL    Same y-coordinate returned for different vertical positions when creating board outline in HotFix 0481 ^/ s" _" J7 q& p
2033958 ALLEGRO_EDITOR     UI_GENERAL    Incorrect canvas display on creating a design from the Start page and then opening an existing design# _. o8 w2 i- I, [* c: a
2053496 ALLEGRO_EDITOR     UI_GENERAL    Confirmation dialog is behind canvas
' D9 i4 r6 E; ~" ^  e6 ?( p# }2054429 ALLEGRO_EDITOR     UI_GENERAL    Editor stops responding until choosing Done after clicking Zoom by Point twice, D* P2 |1 j, s4 r# k3 K
2059707 ALLEGRO_EDITOR     UI_GENERAL    'HTTPS' links are not shown as hyperlinks when using allegro_html
" L) k$ c3 L, H+ g2 u2063423 ALLEGRO_EDITOR     UI_GENERAL    Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden
8 q* G0 z+ E  j& x+ ~2038105 APD                DRC_CONSTRAIN APD crashes on update DRC in release 16.6- D- V+ L0 j( }0 s
2050674 APD                PARTITION     Cannot remove C-Point from a partitioned design  J3 R* L& D4 L- h& W
2068814 APD                WIREBOND      Bond wires cross on auto-separate
; o- v/ F0 t. k0 O7 s* ]  U, h1967433 CAPTURE            OTHER         Cannot open DSN or OPJ files by double-clicking if Capture is already open
- `$ \( e; A# \; k1 \, ^+ K3 ~! g7 t1967332 CONCEPT_HDL        COMP_BROWSER  Crash in customer environment on clicking on last row border in PIM after filtering. i2 A+ V7 d$ Q4 J# g0 r
2001759 CONCEPT_HDL        COMP_BROWSER  Using Modify Component crashes Design Entry HDL: x. b1 m  N( |" v
2020788 CONCEPT_HDL        COMP_BROWSER  Intermittent crash when clicking bottom edge of part selection table in the Modify Component window: D. o) g( [6 k; _+ U* [% M% d
2053578 CONCEPT_HDL        CONSTRAINT_MG Values specified for custom properties are not preserved3 U2 P$ E0 Q8 o. v2 K$ i+ ]; z
2013002 CONCEPT_HDL        CORE          Ability to regenerate Netgroup names to remove '_1' suffix! A8 i( L' a& |. ]
2026637 CONCEPT_HDL        CORE          DE-HDL crashing often when launched from EDM Flow Manager! v( }+ j/ v$ T# M
2041145 CONCEPT_HDL        CORE          Set font size & color of netgroup names and netgroup taps
3 @2 k' {+ S; q" |0 R1 T/ s2056743 CONCEPT_HDL        CORE          NetGroups appended with _1_1, some are empty, and inconsistent in DE-HDL CM and Allegro PCB Editor CM7 `8 y% R0 R: P. J/ U% w. o
2065889 CONCEPT_HDL        CORE          DE-HDL Modify command moves location of attached symbol properties
2 p1 u; Y! r% |+ ~9 Q2074410 CONCEPT_HDL        CORE          Full net connectivity not shown in Allegro PCB Editor.6 ?  {: w4 }8 L, e2 D2 ]+ z7 R
2045717 CONCEPT_HDL        RF_LAYOUT_DRI The RF PCB Options is greyed out when doing Import Physical on Linux with enterprise licenses! l6 e! X4 m' v* Q
2045274 CONSTRAINT_MGR     CONCEPT_HDL   Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor
; m/ i) e- X) l, g4 C) C# L; F3 t2050521 CONSTRAINT_MGR     OTHER         Unexpected Xnet removal from schematic when Export to PCB Layout is executed.
! r! z" Q( R2 j& p0 ^2066270 PCB_LIBRARIAN      SYMBOL_EDITOR Unable to edit note text containing comma% T) |0 T8 R& Q5 P+ M
2069181 PCB_LIBRARIAN      SYMBOL_EDITOR Pinlist window expand/collapse buttons act weird first time when invoked." l4 D0 o6 A* K6 x; ^" P
2070007 PCB_LIBRARIAN      SYMBOL_EDITOR Project not found error in Symbol Editor when path contains space character  _0 E" F, s0 M. x7 z! g8 D+ l0 ?
2072793 PCB_LIBRARIAN      SYMBOL_EDITOR Right-click menu of formatting text objects is not consistent: second and third options are swapped: `9 z* V4 d$ T9 O. H- h
2073138 PCB_LIBRARIAN      SYMBOL_EDITOR New Symbol Editor: Do not allow duplicate properties
( V  A5 h- }2 t1 l* r0 ]  k: j1957458 PSPICE             FRONTENDPLUGI Refresh issue with Bias Display on a new design: bias value not updated
* z0 J1 H! O/ v8 C  E: E, |2022211 PSPICE             FRONTENDPLUGI Bias Point results are not updated
( p8 \( E! T1 [& y" m2031058 PSPICE             FRONTENDPLUGI PSpice bias values are not getting updated- F+ z+ P% G+ v8 A2 @# w! q6 T. T7 k
2038021 PSPICE             FRONTENDPLUGI Bias display is not updated$ a& b6 r! f) {
2055274 PSPICE             FRONTENDPLUGI Capture crashes on SIMSETUP OK when two projects are open
6 B0 W& a. w: R7 M2053432 RF_PCB             OTHER         Property on RF component not transferred to new design not containing the component
$ d! l; Z8 r/ I5 z$ ~1 D2003341 SCM                SCHGEN        Unable to generate a schematic for hierarchical blocks
% H; s' ^- w# j+ h1 ?; }2069924 SIP_LAYOUT         DIE_ABSTRACT_ Conversion from co-design die to standard die / BGA / anything else must remove floating function pins.8 D% e  d, \1 _9 ?2 q
2067894 SIP_LAYOUT         OTHER         sip database size is enormous for a small component definition used in fdesign2 b3 L- @' q+ H/ U3 r
2067987 SIP_LAYOUT         OTHER         Orphaned die attachment in SiP Layout cannot be removed; O5 [' F& }3 S* Z+ o
2072857 SIP_LAYOUT         OTHER         SiP Layout crashes when using Find by Query and choosing 'Symbols'- V- m" @. {  F$ k- o! s9 G, G" ?
2068973 SIP_LAYOUT         REPORTS       SiP Layout Missing Fillet report not catching a missing fillet in HotFix 051 and 052: C$ y  {2 n# T7 V! N
2059533 SIP_LAYOUT         SYMB_EDIT_APP SiP Layout: Cannot rotate bumps in Symbol Editor application mode
+ @+ P- O- `, Z; b% Y3 l% C" v1981749 SYSTEM_CAPTURE     ARCHIVER      System Capture: Archiving a design from the Tcl command window results in error
& H. @6 O2 `3 h! X. t2054869 SYSTEM_CAPTURE     AUTOMATION    syscapUtils.tcl command cnsAutoCreateDiffPair is broken due to missing acm_code.il and acm_config.txt files
0 d/ t2 k9 P$ e' \1966488 SYSTEM_CAPTURE     CANVAS_EDIT   New folder rename box does not show the text typed.5 N1 t9 @( g! b; l
1814813 SYSTEM_CAPTURE     COMPONENT_BRO System Capture session log should specify the CDSSITE path for the current session
8 e8 ], z" B# m+ E1977673 SYSTEM_CAPTURE     COMPONENT_BRO adding reference blocks through add component error when cell name matches design name8 x( H! M: A4 O2 Z2 l7 u3 k
2027100 SYSTEM_CAPTURE     COMPOSITE_FIL pstdedb.cdsz and netlist preview in System capture is not being updated when individual netlist files are written
' a8 s+ s* e- h6 a# n1 O5 M, ~1961274 SYSTEM_CAPTURE     CONNECTIVITY_ Xnet removed during pin swapping" h4 p! `8 \, n5 \( i& _8 b; G2 c
2041879 SYSTEM_CAPTURE     CONNECTIVITY_ xnets on net with only pull-up resistor
. f5 m' I& W( Y1889238 SYSTEM_CAPTURE     COPY_PASTE    Wire fails to connect during copy and paste
  w2 \+ k+ m1 |! l% Q* A9 |' E1993146 SYSTEM_CAPTURE     DESIGN_EXPLOR Cannot move page up by only one position  B1 ?: N) \0 Q+ d+ W4 i
1910941 SYSTEM_CAPTURE     MISCELLANEOUS Parts that are not in any schematic page appear in netlsit and BOM# S* W1 E5 z2 @" z/ H
1902347 SYSTEM_CAPTURE     PRINT         Prints all sheets if one sheet is specified as the print range
/ I7 s8 d: s- j1 n5 s8 [2041272 SYSTEM_CAPTURE     SMART_PDF     Smart pdf displays component outline when component is not de-highlighted.
9 n6 D9 `5 l/ D* e; f: P$ W2065768 SYSTEM_CAPTURE     SMART_PDF     Custom Variable in Table Object not getting passed to PDF2 S7 T/ @! j, f" Y& {! p
1969243 SYSTEM_CAPTURE     VARIANT_MANAG Export variant does not name file correctly if the filename contains a space
7 z% ~5 w. j2 I5 v0 \5 n. |* |1990258 SYSTEM_CAPTURE     VARIANT_MANAG Cannot paste copied preferred part to multiple parts with the same part number9 p  c8 J+ r3 ^# ]- Q/ m
1992250 SYSTEM_CAPTURE     WORKSPACE     Double-clicking a .CPM file runs System Capture but does not open project
作者: haveok    时间: 2019-5-4 07:58
坐等一个百度网盘啊
作者: th2010-gc01    时间: 2019-5-4 08:07
耐心等待！
作者: bingshuihuo    时间: 2019-5-4 09:15
楼主貌似下了几天了
作者: suiwinder    时间: 2019-5-4 09:27
坐等网盘
作者: yangquan3    时间: 2019-5-4 15:16
反正我还在用16.60 u! z. u' r2 l" P
自行安装验证
作者: steve1234    时间: 2019-5-4 18:19
有下載連結了，看到一定要來更新，謝謝熱心提供分享。
作者: kuka_555    时间: 2019-5-4 19:08
感谢楼主分享
作者: kewin_wang    时间: 2019-5-4 19:41
感谢楼主，楼主神速啊！！！
作者: adolfchen    时间: 2019-5-5 09:50

) n9 P, ~  |: k( o4 W感谢楼主！
作者: amaryllis    时间: 2019-5-5 10:03
感谢楼主热心分享！
作者: longzhiming99    时间: 2019-5-5 12:32
bingshuihuo 发表于 2019-5-4 09:15# `( J7 g' O, H9 V3 k
楼主貌似下了几天了

. q3 H8 U% f6 v1 K4 _5.1休假啊0 x5 L8 `. j& a8 |7 o
作者: sztyzhi    时间: 2019-5-5 12:43
谢谢分享！
作者: bingshuihuo    时间: 2019-5-6 07:46
感谢！！！！！！！！！！！！！！
作者: wolfshiao    时间: 2019-5-6 08:47
感謝樓主大大的分享了...
作者: lgl2466    时间: 2019-5-6 17:24
多谢分享！！！！！！！
作者: cxyfarmer_2    时间: 2019-5-7 08:00
感谢上传
作者: zuoanwind    时间: 2019-5-7 08:56
谢谢分享
作者: bitiwindy    时间: 2019-5-8 09:04
多谢分享
作者: koncc    时间: 2019-5-8 13:15
感謝分享
作者: Deny    时间: 2019-5-17 16:38
thanks
作者: 金志峰    时间: 2019-5-18 11:21
055的可以下载了吗？
作者: yangquan3    时间: 2019-5-20 17:36
金志峰 发表于 2019-5-18 11:21
4 V2 ~. Y5 E, G) ?/ U" M: j* K055的可以下载了吗？

% n) z. [5 R9 z! L7 ^: Z2 w+ R4 v还没有这么快
# S  x$ e' F( S4 z
作者: linsky2000    时间: 2019-5-23 14:56
谢谢楼主的分享！
作者: a199111222    时间: 2019-6-20 09:23
謝謝



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