标题: 仿真报错求解 [打印本页] 作者: 流光、溯雪 时间: 2018-10-18 12:42 标题: 仿真报错求解 Hyperlnyx中仿真，U1芯片为XCZU11EG-2FFVC1760E，. Y P5 e( J2 G W
使用IBIS模型为zynquplus.ibs( x W' y3 h) [; T8 R- | o/ Z
, W+ y8 V2 v3 G6 S3 N) y3 |) H1 C$ u[IBIS ver] 5.13 J! o0 _ C1 I% A6 C
[File name] zynquplus.ibs # x) a, c2 w5 Q: d. A[File Rev] 1.12# ]) m) I$ a" Z1 H' g- k
[Date] 22-MARCH-2018$ ]- V+ o: Y H$ L- U6 D- L
[Source] Derived from spice models, rev1.0, using6 L' ?/ I: ?2 Q* ?
hspice 2014.09-SP1-21 J3 [+ s i" Y( G/ T" Q/ D4 y
[Notes] Xilinx IBIS file for Zynq UltraScale Plus I/O standards. 1 v2 l9 _0 Y+ o: Y All models are preliminary.! |0 I, s4 u/ p) q' ?+ [7 m0 l
The version of IBISCHK used is ibischk5 V6.0.1. " A( l1 M4 B5 ]5 x5 u| 2 j- X, t4 e5 t8 H$ ^+ ]( p/ ^; B[Disclaimer] The data in this file is derived from SPICE simulations using 6 P& B( f7 q& d9 y0 a% u modeling information extracted from the target process. While A* y3 v3 y: x+ c) s
a great deal of care has been taken to provide information 2 f% C/ q- [* J that is accurate, this model is considered preliminary as it4 Q, H' y: @/ e# k- m4 }# D( a5 k0 l- n
has not been verified by actual silicon measurement. Treat the u9 E: x) \% f. R) ?3 K$ }
data in this model as preliminary until actual silicon ; _* T& i0 M0 C; {5 W( h' ^$ I2 G verification is performed. ! _: _% K# a; C8 a6 K5 [! r|- x% ]6 L% ^8 D" u/ n: z/ }; y
[Copyright] Copyright 2016, Xilinx Inc., All rights reserved . l& E2 n, w4 Z9 X' F! }2 @! T/ y# a* k5 r/ A
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仿真的时候报错如图，请问各位朋友这个该怎么解决啊？2 J" ]- i3 \- [! \$ Z% }" Y3 w
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