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( ?# N4 h! E. z7 Z* n9 i Overview 0 O7 f9 N& s* a2 z# ]3 D! HHigh-speed designers must evaluate signal integrity and timing margins while accounting for crosstalk and power integrity in order to ensure reliable system' l. f+ O) T2 C4 g2 Y4 `
operation. Quantum-SI™ enables users to quickly achieve High-Speed Design ClosureTM by integrating static timing, signal integrity and crosstalk analysis in 0 A8 \5 S9 S- A/ D& ma single tool. Comprehensive modeling and simulation capabilities predict system-level noise and timing margins more quickly and accurately than competing signal integrity products.- O: i9 [# P. O7 D5 E/ K) G% l Y
3 r8 J$ g4 u. d# }) {4 M9 y# x* l _Interface-centric Analysis * Q$ g1 {5 V* ?2 [4 uQuantum-SI analyzes entire high-speed interfaces instead of simulating individual nets as traditional signal integrity tools do. Quantum-SI captures all the net types, required timing and signal integrity relationships across an interface during design setup.Quantum-SI runs required SI analyses automatically,and closes timing across the entire interface.Quantum-SI’s interface-centric analysis approach allows engineers to quickly and easily analyze entire interfaces for the composite effects of signal integrity, crosstalk and timing.0 K! H9 x; r. l0 n4 d: a3 F
8 _4 k0 _- _2 s- V Tightly Integrated Flows+ b& M% o3 a# @9 A _2 E3 f0 p& o
Quantum-SI tightly couples pre- and post-layout analysis flows by leveraging net topologies and simulation setups. Pre-route circuit representations are automatically mapped to routed databases using SiSoft’s patented TransferNet™ technology, which minimizes the effort required to run post-route simulations and achieve post-route timing closure. ) |, U! s# _+ G8 G* ~3 K$ E E# H% e: |2 V% @ Powerful Pre-Layout What-If Analysis9 L+ P/ P+ K7 u; |
Quantum-SI allows users to quickly capture interface nets and relationships graphically. The pre-layout editor provides an electrical view of I/O devices and; S3 o1 B7 F' \& b1 m' S2 L
interconnect topologies. Network parameters can be defined as variables and swept across a range of user-defined conditions. Pre-layout analysis allows different termination schemes, I/O buffer selections and routing strategies to be quickly analyzed and assessed for their effect on overall interface margin.8 m0 l- a4 Z( O. `
; K0 I+ W9 V- C4 S. B1 vPost-Layout Verification ( T2 b, {3 l1 qQuantum-SI’s post-layout flow allows PCB databases from different layout systems to be managed using a unified graphical interface. Quantum-SI automatically / ?$ A" d; T6 a/ a, E0 Sextracts network topologies and runs signal integrity simulations, then validates interface waveform quality, timing and crosstalk. Automatic mapping of pre-route topologies into the PCB database ensures designs can be analyzed quickly with a minimum of user intervention. ! o/ W" p. Y( K2 U 7 r* p) E( |) Z% b" \' _5 l- gComprehensive Analysis d- S& q# Z" a3 w7 }8 b
+ Q! Q# P3 Y+ M% [- S+ b, W! h ; w d* o* N4 B9 L# O! d1 tQuantum-SI utilizes SiSoft’s Core-to-Core™: m$ X/ g' V7 J! ?9 _2 k; K1 R0 d9 l7 n
methodology to analyze simulation results at the device pin, pad, or core using the most rigorous processing available in the industry. Every edge of every waveform is analyzed using a comprehensive set of voltage levels for waveform quality, slew rate,4 C( c* ^) N3 O& `0 A
area and timing parameters. Slew rate derating can be employed to adjust interconnect delay measurements. The static timing analysis engine" i! q# Q3 R) P; r ~4 W
automatically determines interface setup and hold margins based on simulation results. * G% i9 t# ^; q$ V* {3 O - a; Z: `. m7 K' {1 lQuantum-SI Interface Analysis Kits - U4 @, y h0 d/ h
1 E- Q. m! @, p4 k+ A& b) uQuantum-SI interface analysis kits provide “ready-torun” : S8 h% [: J' J- {9 {5 Z( `environments for interface standards like DDR2. A central library of interface kits can shave weeks tomonths off a traditional design cycle by reducing oreliminating model development and design capture efforts. Interface analysis kits include topologies for different net classes and timing relationships that must be met across an entire interface. Kits also include technology and design-specific information, such as rules for managing simulation models based on ODT configurations and waveform derating rules. “Legal” data transfers are specified for multi-drop nets to allow elimination of false paths during static timing analysis.7 [' ]" s, c+ W( ^
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Interface kits are ready for use “out of the box”, and can be readily adapted for specific design requirements where required. Users can save updated kits into their own library for future use.1 {1 Z: g! ^, I4 M# m0 P+ A# R+ R
& E) H9 S$ s" u3 c! \# L) AInterface Analysis Kit Components: \; z& K R! f: o0 s
• Component timing models2 o! \$ ]; Y$ F5 ^ M
• IBIS simulation models : t8 p3 O* t v [& I; C6 R• Topologies for all net classes 0 ]. P" l) j+ O" W$ \" q• Design timing requirements 0 B2 K: G# ^# r2 r; d" H• Design-specific analysis setups; x: C. K' @' M8 q2 C/ g" N
• Design-specific results processing rules) k9 f- ` z7 U+ u5 i- O: j$ O' h
Optional Analysis Kit Components ( y8 s: Z4 e5 T$ o9 d! S, T• Spice simulation models# Q0 g( s3 R, y1 v& k
• PCB reference designs% v. B7 Q5 D" H1 L" H' {
* P6 w @) `! A8 x* Q Major Quantum-SITM Features ' d! y4 A/ t+ I/ ]" A/ z- j" \• Integrated signal integrity, crosstalk and timing analysis for pre/post-layout flows V% e7 R% R# _" K+ c/ F+ U5 @- |
• Exhaustive solution space analysis—lengths, terminations, data patterns, coupling, component variants, buffer models, and populations across process, voltage, and temperature corners for etch/silicon / O4 R9 D6 [ N- X |• Floating ground analysis ; N( Y0 K& ~; Z( M+ B" ^8 O" U• Superior post-layout automation and capacity for extraction of very large multiboard databases ; g. n$ {4 |9 _5 _; C M2 v: M* u' c• Rapid post-layout crosstalk screening and crosstalk simulation . O6 T3 D# \; s9 G6 J• Static timing analysis for synchronous, and source-synchronous interfaces ) r/ y' R: j q) _$ \' e4 Y• Industry’s most rigorous waveform/eye diagram processing % g) K+ Q; A) P! p% P& l/ ~• Tiered results viewing—drill-down from high-level summaries to low-level detailed& @% j2 _* {( G" Y
reports + q$ r; W' Q( m8 D. V• Advanced graphical waveform viewer5 s' ^5 o$ h0 }1 R: X
• Design analysis reuse1 G: q. V: H8 ?7 w+ N4 u
• Seamless support for mixed HSPICE/IBIS models 7 W* l& c, V0 y. M• Automatic library validation and consistency checking$ A6 ^ R8 \5 N
• Batch submission to compute farms CAD layout system support S7 q4 f* H. z
• Allegro® - w0 k6 b: J' R- y7 v. \ Y• Expedition PCB™1 A# a. ~2 w4 Y3 Z
• PowerPCB™- r: _* Z# B* ^/ ^6 f1 i
• Board Station® 9 d8 n) Q9 U3 o% j% [2 t• Pantheon®5 `( [. `4 a- g+ p- s
• P-CAD™ ^( i( q( A1 n j5 S% r7 U7 @7 Q
% U' i" n' q o& w5 Y Supported Operating Systems - w6 v# U+ k* y! a• Solaris: 9, 102 _4 n4 g% k% h0 p; _! t9 a
• Linux X86: Kernel version 2.4.26; Libc ) J# m/ S' a/ M- K S, l8 Z3 {version 2.3.31 }; v1 b4 ]; g2 X( P$ `% _6 c( O. A
• Windows: 2000/XP
作者: cjf 时间: 2008-1-21 18:00
提示: 作者被禁止或删除 内容自动屏蔽作者: forevercgh 时间: 2008-1-22 08:19
Comprehensive Analysis看起来很吸引人作者: rjc 时间: 2008-1-26 21:58
看起来是不错~~ 难~~作者: viseng 时间: 2008-1-31 14:29
顶,作者: icerpcb 时间: 2008-2-15 17:56 标题: 不晓得这个软件怎么样啊？ 这个是SIsoft的作者: damaoelc 时间: 2008-2-19 14:41
Libc version 是指哪个东东，请教。作者: slim443 时间: 2008-2-21 20:15
路过，顶下作者: jesims 时间: 2009-5-13 01:38
這是一個有趣的討論。感謝您分享..9 m! n8 X5 ], R simulation rachat de credit作者: kebon22 时间: 2009-10-30 19:40
顶一个
