标题: SPB 16.6 從061到071版的補丁內容 [打印本页] 作者: jacklee_47pn 时间: 2016-6-29 12:21 标题: SPB 16.6 從061到071版的補丁內容 DATE: 05-28-2016 HOTFIX VERSION: 071 ) B- P# e1 W' p=================================================================================================================================== ; t* C( H5 K( O# \CCRID PRODUCT PRODUCTLEVEL2 TITLE3 O) ?0 n; d4 F# U9 w2 X/ G3 ]) A
=================================================================================================================================== 2 t9 n' j# h1 ~5 T: A) m1452838 CONCEPT_HDL CORE Apparent discrepancy between Bus names and other nets$ y7 A: h" {3 v5 I9 p0 f
1469146 ADW LRM ERROR(SPCODD-5): Pin '1<1>' on the following primitive instance cannot be packaged in package & ?9 L6 z1 k# N( R- i! m1 O1499515 ADW COMPONENT_BROWSE The Search Criteria property value is automatically being set in the ADW Component Browser2 }! p* }2 Q9 i, p
1524947 SIG_INTEGRITY SIGNOISE SI Base, PCB SI: Custom Stimulus is not recognized correctly( Q( {& \; J: \
1532162 CONCEPT_HDL CORE The Rename Signal command does not update split symbols. : j8 j9 x# T; M+ e1543997 CONSTRAINT_MGR OTHER Import Logic is overwriting the constraints in attached design.' m% M7 N/ a% s9 V0 ~, f; |$ t
1544675 ALLEGRO_EDITOR OTHER Export libraries corrupts symbols if paths do not include the current directory (.)3 {- u' o6 {# j' `4 ^$ y! F
1549097 CONSTRAINT_MGR XNET_DIFFPAIR Need to warn users creating differential pair(s) in the Physical Tab with nets that have voltage properties set+ M. G" v, [5 V4 [. H" c
1551934 ALLEGRO_EDITOR SKILL axlBackDrill command is not analyzing new layer set when application mode is set to 'None' & g( l& c' J. Z/ K R8 C1554919 ADW LRM LRM does not find PTF data for cell 'res' in the reference library $ J4 ~4 ?# W6 @* [: R1555009 CONCEPT_HDL INTERFACE_DESIGN Not possible to rename NG & w0 c7 e! T2 ]& Z$ d1557542 ALLEGRO_EDITOR OTHER DXF export creates strange result for donut-shaped polygon ! E1 n6 ^! T) H) H; P1559136 ALLEGRO_EDITOR EDIT_ETCH Cannot connect floating clines to vias with nets * w: C8 _3 V. j1 d3 a' x% u& ~8 R3 p9 v1560301 CONCEPT_HDL CORE DE-HDL hangs when Edit menu commands are called on Linux if xclip is open7 o1 b" x; c/ Q3 S' g
1560804 ALLEGRO_EDITOR OTHER Film records order gets reversed when using File - Import - Parameters after File - Export - Parameters 6 w! X. g/ w, {. m1564036 CONCEPT_HDL CORE User-defined custom variables are not getting populated in the TOC ' |2 ~& ]5 |+ ]+ G, F7 I1 \! K1 E9 s: ^1564545 CONCEPT_HDL OTHER Signal model property deleted from an instance is not deleted from the instance pins, J: y/ T7 S0 m. V2 b4 P
1564552 CONCEPT_HDL CORE Find Net should zoom to the nets on schematic canvas - @' B! E" J; N* l- F& A1566119 CONCEPT_HDL CORE Right-clicking the schematic to add a component does not show all the schematic symbol versions I- q5 T4 q& P. }; I" X3 r1566848 ALLEGRO_EDITOR ARTWORK Board Outline artwork is incomplete; i. H3 ?( h2 E/ v9 A2 V2 l1 a. _$ E
1567290 ALLEGRO_EDITOR MANUFACT Import Artwork fails to import a shape. ) g+ z4 ?* D& f; d* |6 M5 E+ w( P5 |1567587 ALLEGRO_EDITOR MANUFACT Extended tool name in header of drill file is not correct4 P- n9 | k( d- d4 g. k
1569056 CONCEPT_HDL CORE Opening New Cascaded Window Causes Graphics Artifacts on Old Window ) W1 W' F. @3 j/ ]8 f2 z1569087 ALLEGRO_EDITOR DRC_CONSTR Running DRC Update gives the message 'Figure outside of drawing extents. Cannot continue.'8 e$ d" q0 z- X* k
1569147 CONCEPT_HDL CORE Signal Name AutoComplete Drop Down List Not Correctly Displayed : c! V; ~4 a# m+ \1 z) f* F1569924 CONCEPT_HDL CHECKPLUS ERROR (body_to_physical_check) - Pin name(s) not found in package : PEX_REFCLK0_N* PEX_REFCLK1_N*...5 p8 N% C& R' b, r
1570419 CONSTRAINT_MGR CONCEPT_HDL How do I add a customized worksheet custom property weblink in Constraint Manager+ A6 [! l; q7 J7 g+ q: D! q A
1570624 APD ARTWORK Artwork file has missing voids on a layer and is causing a short ! x7 Y/ i; g: K A0 b' Y1 q# B1570678 F2B DESIGNVARI Variant Editor error when adding an RSTATE property' S) U6 [0 b0 ]# E/ W, T
1571113 CONSTRAINT_MGR DATABASE Reports generated from cmDiffUtility show the differences in mm units only/ b2 v. k3 L! x
1572593 ALLEGRO_EDITOR ARTWORK ARTWORK: 'Draw holes only' option does not match display 0 D/ N% X; Z9 s Z1573205 CONCEPT_HDL CORE dsreportgen is unable to resolve the physical net names (PHYSNET) & S$ ?$ ?( D2 t1573970 CONCEPT_HDL ARCHIVER archcore fails to archive the <project CPM>.arch file 0 _% K9 ]( D. A! _' x5 c( E! p1574381 CONCEPT_HDL OTHER Packager crashes with some advanced settings* N( i4 `7 Q0 o" @
1576100 ALLEGRO_EDITOR SYMBOL Update symbol crashes, creates '.sav' file, but shows update was successful in 'refresh.log' - _, n, V3 W* d& e2 u1580103 ALLEGRO_EDITOR DATABASE dbstat of 16.6 does not recognize 17.X files - c- c! I3 Q) G: ]2 G" C0 R8 j, f7 t 9 T( `& f. w% r3 EDATE: 04-22-2016 HOTFIX VERSION: 069, y% V) E3 C) d
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1272355 F2B DESIGNVARI Property changes on replaced component shows incorrect result in BOM output/ f+ T& ~* \8 K, c
1483136 ADW COMPONENT_BROWSE About searching the parenthesis or comma in Component Browser of ADW Mode / A" G r1 i3 X4 Q i4 y0 u/ v$ ?1488909 ALLEGRO_EDITOR DRC_CONSTR Test Via causes net scheduling verification to fail : ]# V3 M! r0 m1498389 SIP_LAYOUT DIE_GENERATOR Provide the ability in the 'die in' command to specify flip chip as a DIE symbol ' G5 Q# n( u+ f/ m8 }; I( T, q( g1 ^1506672 ALLEGRO_EDITOR INTERACTIV Replicate Place - Shapes are missing 1 p+ \! ]1 N! l( `( g1523532 F2B PACKAGERXL Adding subdesign names in the "Use subdesign” or “Force subdesign" sections hangs for more than a minute& G; G, q, C; N4 w: ^% S- [3 @
1525783 CONCEPT_HDL CORE \BASE scope does not work for SYNONYMed global signals1 E( Q0 U' e8 b$ D) g8 S0 Z% p
1529846 ALLEGRO_EDITOR SHAPE Some shapes are not generated in the artwork 9 {3 z9 s: B8 k! x) m- K4 X/ `1537499 CONCEPT_HDL CORE Adding the same version (already placed) with the same split block name should not be allowed" c. z6 T$ X6 J- z8 o" @+ P( W
1542334 CONCEPT_HDL CREFER creferhdl leaving lock files in sch_1 folder! L; d, H! U, S
1543410 ADW LRM LRM shows confusing pat status. It reports that update is needed but clicking update doesn't work8 [9 ~9 X% Y+ X* d5 d7 G
1546141 ALLEGRO_EDITOR SHAPE Shapes missing from Artwork6 n% u3 ~/ }/ @2 J
1546877 CONCEPT_HDL CORE Align Left on Wires Fails With Incorrect Error Message 7 {2 x& u; _2 @$ D6 z0 { M' p! S! B1548953 CONCEPT_HDL CORE Genview generates a symbol with strange graphics - lines going to a single point: q( c) j0 X F5 O8 s( [* B* R1 y7 y
1548978 ALLEGRO_EDITOR MANUFACT Shape not voiding clines2 ^* Z4 b2 n. M' S3 N- Z
1550941 PCB_LIBRARIAN PTF_EDITOR PDV Part Table Editor new column sorting causing problems' D8 }, b) M# x$ w2 Q! {
1553950 ALLEGRO_EDITOR SKILL Executing axlUIControl('pixel2UserUnits) crashes Allegro " f5 N; b$ \$ B; S1554333 CONCEPT_HDL CORE Changed connectivity error when aligning ports attached to netgroups* _' y5 Y1 T$ ~* l
1555092 SIP_LAYOUT DEGASSING Degass offset is not working with hexagons $ a3 D+ L) s- A5 b$ K: A3 p$ C1556261 ALLEGRO_EDITOR DATABASE Running DBDoctor on board file gives an error"Illegal database pointer encountered, Exiting DBDOCTOR." and crashes* i8 M* m3 |+ \9 o7 I' M
1557716 APD OTHER Stream out fails with request to terminate detected - Program aborted ( _$ z, ~; p5 x7 S: z3 p; y! r1559951 SIP_LAYOUT SYMB_EDIT_APPMOD Wrong bump locations after Symbol Editor -> Refresh co-design die' G8 u1 |/ }* j2 B
1560197 CONCEPT_HDL CORE bomhdl adds extra charcters to subdesign_suffix when generating hierarchical BOM- M' i. ]# N+ a
1562537 ALLEGRO_EDITOR MENTOR Mentor BS to Allegro 16.6 results in Fatal Error$ E8 A; h& b0 x2 T& ^
1564203 ALLEGRO_EDITOR ARTWORK ARTWORK : Can't generate negative film. 9 s$ A2 n G( W3 b& s) O6 V$ r- V3 O( O6 \5 v" j
DATE: 03-23-2016 HOTFIX VERSION: 068 1 X& K. y( S+ Z===================================================================================================================================# Y' H" q: j: R8 ^+ G ^4 c
CCRID PRODUCT PRODUCTLEVEL2 TITLE % F3 z/ y" O7 T8 U, P7 U2 [=================================================================================================================================== 4 E7 v S' b4 d! c& {) T& X+ ~1522411 FLOWS PROJMGR License selection should persist on invoking Layout from Project Manager& }+ [# {; s$ e- m+ r. q1 S; `3 I2 R
1544614 ALLEGRO_EDITOR SKILL Associative dimension data reaches the 'psm' file despite deleting the layer on which it was set in the 'dra' file 8 W" E W. v( M5 p2 n3 ~# \1545909 ALLEGRO_EDITOR UI_FORMS Show 'microvia' checkbox in 'Blind/Buried Vias' form only with the 'Allegro_PCB_Mini' license$ V8 [0 l- a' K2 N @3 ^
1546842 ALLEGRO_EDITOR OTHER Unsupported characters: Not being reported by 'netrev' and causing nets to short . q3 P6 i% F0 t- F1547224 CONCEPT_HDL CORE Lock the 'PATH' property once it is assigned by system * c% h8 G3 s5 E& d1547584 SIP_LAYOUT OTHER SiP - Design Variant - delete embedded layer if not selected.3 `" v& V5 C$ s8 E! C+ e
1548116 CONCEPT_HDL CORE Some versions of Technology Independent Library do not appear when adding a symbol" b) o* k& }6 k; h! X7 T
1548151 ALLEGRO_EDITOR INTERFACES Exporting a step file gives a component rotation mismatch in the *.stp file( _1 W( l! T6 l
1548421 F2B BOM Parts with same 'BOM_IGNORE' set do not behave the same way in the BOM report ! T4 O5 n) v: J. X1549105 APD OTHER 'Stream out' fails with message: 'Request to terminate detected. Program aborted' ! w' P5 P! Z3 ~2 F1549662 ALLEGRO_EDITOR OTHER Import parameters fails if your parampath does not have .( Q5 U% Y4 ~8 J4 m# i0 n
1549836 CONCEPT_HDL CORE Tools -> Customize -> Keys -> Reset does not actually reset keyboard shortcuts 2 ^& P, r3 a v- O7 a1550052 ALLEGRO_EDITOR PLACEMENT PCB Editor crashes when copying symbols+ v/ O4 E, @+ z/ P2 t; b7 M
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DATE: 03-11-2016 HOTFIX VERSION: 067 2 N* M( `$ x/ K# N( z=================================================================================================================================== " }% f0 ^/ Y+ SCCRID PRODUCT PRODUCTLEVEL2 TITLE 4 t2 |+ `) i4 I% q& ]=================================================================================================================================== ' V* E/ N: i( J! i! ~1482953 ALLEGRO_EDITOR DATABASE Part change disassociates parts from Group # r" ~" k2 ^9 ^9 A1484075 ALLEGRO_EDITOR PADS_IN 'pads_in' imports ASSEMBLY_TOP and PLACE_BOUND_TOP outlines that are defined as shapes as lines2 x) q$ M Y9 X+ m
1519155 ALLEGRO_EDITOR OTHER IPC-2581-B Negative Plane Error1 _3 f! a0 E& |. Q# \
1528075 CONCEPT_HDL OTHER Auto Generate: DML model assignment fails with error 'There is PHYS_DES_PREFIX property in PTF file.'- A' X* L1 I. N! u, h3 E- E% K
1528398 ALLEGRO_EDITOR SCHEM_FTB Problem with pin number format used in NC property/ V% U ?: X# h3 J
1529178 SIG_EXPLORER OTHER Values not transferred correctly for PinPairs when created ECSET from a net% ~3 ^ R; E! s3 r% y
1529720 CONCEPT_HDL COPY_PROJECT Running ADW copy project does not update the 'master.tag' file l( {1 r' I% q2 G v1530707 CONCEPT_HDL CORE Request to recover a 16.6 design after DE-HDL crashes# `: Y; S# X9 W; R
1532124 CONSTRAINT_MGR SCM 'File - Export - Technology file' in Constraint Manager crashes SCM if .tcf file is missing1 o& A# F* ?7 O8 Z
1532788 CONSTRAINT_MGR OTHER Pin pair is hidden when Highlight Filter is ON in Constraint Manager / p: s0 c% @8 H1536912 CONCEPT_HDL CORE Customizing keys in DE-HDL - Disallow mapping a command to alphanumeric characters( S& f1 @+ q, Z9 o
1537055 CONCEPT_HDL CHECKPLUS Rules Checker - POWER_PINS value not obtained when schematic instance has the POWER_PINS and POWER_GROUP properties 5 E; p7 W [) O' [* M( K# g1 e `1537278 SIG_EXPLORER SIMULATION SigXplorer (Allegro Sigrity SI) crashes when simulation is viewed in SystemSI Waveform Viewer - ^: d7 q9 ^% }5 i* z. s5 R7 E3 ?9 m1537339 CONCEPT_HDL INTERFACE_DESIGN No warning is flagged when moving a Net Group over a net 6 \4 Z M3 {) c$ Y& h1 u; j) d: m! d1537521 FLOWS PROJMGR Do not allow project creation if there are spaces in directory or file names on the Linux platform 6 e0 A8 V6 e4 |" F8 k1539227 CONCEPT_HDL CORE Renaming a page from the hierarchy browser crashes the schematic editor. ! c9 Z: ^+ a! B _* x- ^, Q1541532 SCM SCHGEN Generate Schematics crashes with 'Out of Memory' error. D7 h3 F. @3 M6 I
1541589 ALLEGRO_EDITOR INTERFACES STEP model incorrectly shown in 3D viewer. Shows pins as angled.$ }% J% k! h& u: I6 E
1541680 CONCEPT_HDL DOC A dot (.) or period in design name created 2 separate design folders in worklib# M$ `' e& o5 `9 ?# K
1541687 ALLEGRO_EDITOR PADS_IN PADS closed polygons are imported as lines - x, K5 |; w' M- ] j, j8 R, [1542722 ALLEGRO_EDITOR INTERFACES IDX export: RefDes and PART_NUMBER missing for mechanical symbols+ E1 A4 F3 v$ E
1542817 ALLEGRO_EDITOR DATABASE Import Netlist not getting completed on specific board & X$ n$ v, @3 c" a6 d. c, [1544060 SCM SCHGEN Generate Schematics causes Allegro System Architect to crash; j/ h" m; [4 G0 z
1544633 APD STREAM_IF The 'stream out' command causes Allegro Package Designer to crash & E+ Z" K+ a/ E7 W8 y1544698 ALLEGRO_EDITOR PLACEMENT 'place replicate' does not add clines and vias to fanouts if fanouts are marked2 Q' z' W9 G. L( O% U
1544859 APD PARTITION Timing vision menu is missing in APD/SIP partitions. & M$ J! @* R+ M; B( b! s1545136 ALLEGRO_EDITOR PLACEMENT All fanouts are marked as part of one symbol instead of the symbols they attached with/ t/ \& b" ^/ ]+ }, [
1545370 APD OTHER Pads in .mdd file getting placed on different layers as compared to the design ~9 Y8 A9 [1 V- R9 q8 j$ T- ]% ?* o* o9 f
DATE: 02-26-2016 HOTFIX VERSION: 066 ( g8 \1 q4 H" ~* D: j9 N===================================================================================================================================8 D7 I9 _3 b7 |( e, \
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=================================================================================================================================== " i9 ~" j8 @7 ^" w0 b1523426 ALLEGRO_EDITOR DRC_CONSTR Dynamic shape not adjusted based on keepout; DRC generated $ w1 \# J4 @" v o1526729 SPIF OTHER Exporting a dsn file causes PCB Editor to crash - in the interactive and batch modes * ~/ H9 s' y* O+ B1529209 CONCEPT_HDL CORE When adding a component symbol version, the More option does not show all the versions $ X5 W" Y' G# B8 t9 w+ `# E+ x1530888 ALLEGRO_EDITOR INTERFACES IPC2581 does not generate production files and fails with a segmentation fault message' v0 p0 y- N: G
1532865 CONCEPT_HDL CHECKPLUS Provide the ability for Rules Checker to report a GND symbol from the standard, and not our local library, in .mkr % p3 k5 p: [3 g1 g, e) P8 W, {1536273 CONSTRAINT_MGR CONCEPT_HDL Model-defined differential pair is removed, and Constraint Manager Design Differences does not report an issue / t( B! d H6 \1 b1538343 APD OTHER Inconsistent behavior when running Reports > Design Summary Report in Allegro Package Designer " ~) R3 A k, H+ L1539077 ALLEGRO_EDITOR SYMBOL PCB Editor crashes when choosing Layout > Renumber Pins2 G: y: v5 n/ P1 M+ B
1539997 ALLEGRO_EDITOR SKILL PCB Editor crashes when the axlStringRemoveSpaces() command is run! M3 t& \. u8 {# C7 j6 u3 M
1541445 APD DIE_EDITOR There are two Recent Designs submenus in the APD Symbol Editor; one should be removed ' H5 p, j7 z4 o; o1 u. W1 j) Q9 G9 W6 r- P: S. z+ r3 m
DATE: 02-12-2016 HOTFIX VERSION: 0655 o3 Z9 X: v" g' i" |' T7 K# F
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=================================================================================================================================== 0 B! u+ r, f$ l3 V1511947 ADW DSN_MIGRATION Command line arguments of the 'designmigration' command are not working3 T0 t6 G; _( E% J2 E7 {$ M
1517388 ALLEGRO_EDITOR SHAPE DRC error reported as PCB Editor fails to read the void for a via6 C9 ^5 m* O0 m9 J' U! }' M
1521661 ALLEGRO_EDITOR PLACEMENT 'place replicate create': Automatically select etch objects connected to symbols, but not to objects outside the circuit* A6 a( x2 W8 b
1522831 APD OTHER axlSpreadsheetSetColumnProp with 'AUTO_WIDTH' propName does not autofit the contents.) E& y$ ?* u- G
1524773 SIG_INTEGRITY SIMULATION Running PCB SI Probe and SigXplorer simulations show different number and shapes of waveforms# `! H/ _ t. V4 O% z o
1524875 F2B PACKAGERXL Packaging using csnetlister fails, while manual packaging of individual blocks works fine 3 M% |2 y, s- G X# `' _1527785 SIP_LAYOUT WIREBOND SiP Layout stops responding when adding a wire to an existing finger 9 \- S/ M( L% |# i9 r0 p3 ]( l1528479 ADW LRM LRM crashes when opened on a lower-level block in a hierarchical design & U, d6 B, d" z1531425 CONCEPT_HDL CORE DE-HDL crashing while trying to add a NetGroup , I* Y* ~8 y' ]- ]1532722 ALLEGRO_EDITOR NC Backdrill NCDrill files not getting created with PA3100 license. . `; r/ L5 O2 J* B } ( `+ G5 y0 [+ e4 G6 YDATE: 01-29-2016 HOTFIX VERSION: 064: `5 G S% k: u: F9 T0 ]
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=================================================================================================================================== - P4 B! W0 x5 T3 Y# [0 x1510387 FSP EXTERNAL_PORTS Break in extending a net as a deep connection when it is targeted to multiple FPGAs connected in a daisy chain 1 Y/ _" x1 `5 `3 k2 m( k0 h5 T1514132 ALLEGRO_EDITOR INTERFACES Element position changes after importing DXF 9 O. |3 w$ ~% A% ^- Y% Y' a1514285 ALLEGRO_EDITOR TECHFILE Importing .tcf file from Constraint Manager does not import user-defined properties.% ], `! P6 ~, A \
1515580 ALLEGRO_EDITOR EDIT_ETCH Sliding routed differential pair signals results in odd angles if the 'Dynamic Fillets' option is selected# } F4 O1 u- O4 S
1519040 ALLEGRO_EDITOR DATABASE Match groups are lost when a board created in SCM is saved in Allegro PCB Designer. 3 j3 ]& k; D; K" o2 b. P1519910 CONCEPT_HDL INTERFACE_DESIGN Hotfix 62: Information on manually-remapped port groups is not saved, but reset to default% S" a. t: V U" b1 r C" x
1519943 ALLEGRO_EDITOR DATABASE When user units are changed from 4 to 2, the design seems to disappear from the canvas3 F( i& M; V0 |: U+ H
1519946 CONCEPT_HDL CORE Renaming a net leads to loss of constraints associated with the net9 K) a3 G; L9 M& y) E5 X1 |
1519987 ALLEGRO_EDITOR SCHEM_FTB In Hotfix 61, constraints are lost on importing a netlist . _$ o0 e; t' ? h$ a" G1520727 CONCEPT_HDL CORE In Project Manager, the 'Design Sync - Export Physical' command does not automatically update the schematic2 P7 V; f# ~0 |6 w" P5 \
1521174 SIP_LAYOUT DIE_STACK_EDITOR Padstack shapes not converted correctly to die-stack layer using Die-stack Editor& e! @$ B$ I5 l( G
1522227 SIP_LAYOUT IC_IO_EDITING SiP Layout stops responding when trying to add a co-design die (.xda file)3 r {% L: ?! d
1522900 ORBITIO ALLEGRO_SIP_IF Padstack shape distortion after translation to OrbitIO from SiP design : n( W. u9 `9 b! J8 d1523237 ALLEGRO_EDITOR SKILL SKILL function axlDBGetExtents() causing PCB Editor to crash, k- F8 R0 W( S4 C: y
1524641 ALLEGRO_EDITOR DATABASE PCB Editor stops responding when updating outdated dynamic shapes4 l9 ~/ a) ^6 e% @
1525432 CONSTRAINT_MGR OTHER User-defined property not being transferred from DE-HDL to PCB Editor % c; e. I8 T* o: y5 y; ?1525948 F2B PACKAGERXL Reference designators assigned by the Packager tool are not correct4 U# o E( V+ U- t$ o h. L
1527321 ALLEGRO_EDITOR SCHEM_FTB Unable to create netlist with the 'Open Board in OrCAD PCB Editor' option in Hotfix 63 ( ^+ y+ S4 ~4 Z5 B1528254 CONSTRAINT_MGR CONCEPT_HDL Import Logic with the 'Overwrite current constraints' option is deleting some attributes; G( ]4 j/ @* ?9 k6 \
, }$ Y1 \7 V; ~" q' M$ j; HDATE: 01-15-2016 HOTFIX VERSION: 0631 W- j/ l! @: h2 {
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1472414 ALLEGRO_EDITOR SCHEM_FTB netrev changes pin-shape spacing rule in constraint region ; e& x1 D: }/ t1 n7 v& T1494194 CONCEPT_HDL CORE Random display of the 'PHYS_NET_NAME' property in hierarchical designs8 u& B, t# K% q- Y) F( s4 Q5 V
1500190 ALLEGRO_EDITOR EDIT_ETCH Snake Router Creates Line-to-Line DRCs. H8 D1 C) ~# K
1501093 SIP_LAYOUT OTHER Package design variant shows wirebonds connected to a die which is not part of the variant! W; Q8 [. u3 \' R/ @
1509184 ALLEGRO_EDITOR DATABASE BB vias in mirror have terminal pads suppressed by artwork 9 S) ^/ S% a; B2 R& J1511397 SIP_LAYOUT TECHFILE Tech file exported from release 16.5 cannot be reused in SiP Layout in 16.5 or 16.6 % K; u( K- U0 @$ @1511744 ALLEGRO_EDITOR OTHER Allegro PCB Editor removes property from component instance) d. T5 S6 X' ?( [
1511761 SIG_INTEGRITY OTHER Allegro PCB Editor crashes on running the cns_show command.# l3 i0 o/ a( S6 v6 m& R
1511787 ALLEGRO_EDITOR INTERFACES IPC-2581 not exporting overlapping shapes correctly.- r8 k2 K3 p! R5 Y' P
1512071 ALLEGRO_EDITOR OTHER The color of 'SHAPE PROBLEMS' subclass is reflected in the color of 'NCLEGEND-1-4' subclass when executing PDF out + Q9 V! Z7 H- N7 e) i0 u1513085 CONCEPT_HDL CORE NC pins combine with NC_1 and routed as one net in Allegro PCB Editor 2 ?9 d$ w8 y; M1 ]- e+ W% D5 Q: f2 v2 E1514469 CONCEPT_HDL CORE Unable to get rid of an underscore from the PHYS_NET_NAME property . ]( `1 u% o6 V% u5 X1515318 PCB_LIBRARIAN IMPORT_EXPORT Import Pin Table: 'CTRL + C' and 'CTRL + V' not working correctly # T0 ~1 z+ k/ @$ Q; Q1516093 ALLEGRO_EDITOR PADS_IN Pads library translator does not translate slot orientation & @1 {+ j( ^- j5 `" M( R1517351 CONCEPT_HDL CORE Genview does not update an existing split symbol+ z( I' i9 p9 q5 K' s" I
1518032 CONCEPT_HDL SECTION How to get rid of error 'SPCOCN-2009 - Symbol has the SEC property but the required SEC_TYPE property is missing.'% R' Z1 q; {2 H. \$ M
1518724 PCB_LIBRARIAN PTF_EDITOR PTF Editor is not saving changes6 d6 H- N0 }6 g2 d: _
1519518 CONCEPT_HDL OTHER Genview does not generate split symbols/ l2 Q4 S3 ?1 e Z" c
1519623 CONCEPT_HDL CORE Differential pair added to a NetClass does not display 'NET_PHYSICAL_TYPE' on the canvas3 j' V8 ]; _2 ^: B
1520207 CONCEPT_HDL CORE Genview crashes after renaming ports ( W1 I6 R( Z3 E8 b. H0 R- ?! u j+ X" s& D
DATE: 12-11-2015 HOTFIX VERSION: 062 * B; ?" Q% P3 B4 F; l! w- `=================================================================================================================================== 8 k. b( E5 H J8 L1 K7 ]8 X5 VCCRID PRODUCT PRODUCTLEVEL2 TITLE( [ D9 b0 i2 ]+ Q0 Q! X
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1012606 ALLEGRO_EDITOR REPORTS Natural sort option for Report output 5 e% g( D3 P7 x# _5 w& x( d1408218 ALLEGRO_EDITOR MANUFACT Specifying the Offset value results in unexpected value of the NC Route coordinates in the .rou file# }& `5 R4 L' A* {& L7 j2 u
1440509 ALLEGRO_EDITOR PLOTTING Ratsnest do not follow the refdes position when plotting the BOTTOM layer with the 'Mirror' option: P( U) ]; Y+ @" l
1444144 ALLEGRO_EDITOR DRC_CONSTR The 'add taper' command generates line to line spacing DRC % Q& f, s, U- G X% n5 q& C1 G1471275 SCM UI Allegro System Architect (SCM) - Allow sorting on the pin number field in the Matrix view% f- H* N, k( D `' K3 @
1474764 ALLEGRO_EDITOR PLACEMENT In SPB166 Hotfix 56, the place replicate create command does not produce desired results if the fanout is marked 3 k$ i8 l0 [" o; i, s9 `. E* O1474894 ALLEGRO_EDITOR PLACEMENT Place replicate fails to include vias when the module is applied to other circuits. , P1 q j. c( a; [ ^1485931 ALLEGRO_EDITOR INTERFACES Errors generated when importing IDF in an existing board file ) J! G& d. i' S8 O1487603 SIP_LAYOUT WIREBOND SiP Layout XL - Add multibondwire option to non-standard wirebonding6 V: n, Y9 D7 Q: C7 Q) k* Q. d
1490311 SCM OTHER Block Packaging reports duplication when it should not* c( X$ l$ f& q/ ^& Q
1491272 ALLEGRO_EDITOR EXTRACT Incorrect information exported to DXF if the value of SeparateSlotHoleLegend is set to 'yes' ; g6 b% t6 A% N0 I3 ^5 n1491521 F2B PACKAGERXL Packager reports error (SPCODD-269) when there are duplicate subdesign suffixes - need a clearer message # \3 H; ?* p' k% M+ u( X w1492013 CONCEPT_HDL CORE Stale PNN properties not cleared from schematic on packaging design (backannotation) 6 H4 y. O0 o/ j, l) E9 K7 u+ P8 ~: E1492703 CONCEPT_HDL OTHER 'Global Property Display' not working for symbol edit) u) e; i7 u( ^) C
1495296 SIG_EXPLORER OTHER The T-point sequence in SigXplorer is different from the layout 3 ]) ? M z, Q7 }9 n7 d& V- {1495789 ALLEGRO_MFG_OP CORE DFM checker checks for laser vias ( LVDC, LVDP, LVDT ) ; s; {: L, v* o3 j, m; B% l1496286 ALLEGRO_EDITOR PLOTTING Export PDF is not exporting hidden, phantom, and dotted line types# T7 ]" E) h0 c& [& F
1499051 ALLEGRO_EDITOR PLOTTING PDF Publisher reports error for a donut shape model in the layout - 'Shape symbol cannot have a void in a shape' ! {/ o6 a" ^8 M* x1 w$ F: w9 ~7 Q) k1499380 SIP_LAYOUT DEGASSING Oblong shape degassing voids are not created correctly* M. L4 p) f8 G9 u3 f
1499538 ALLEGRO_EDITOR PAD_EDITOR Pad_designer does not allow layer name change from Begin_layer to diepad1_top; dbdoctor does not fix this , d7 c3 l' S' x! e7 E% F5 Y1500422 ALLEGRO_EDITOR SKILL SKILL function, axlTriggerSet, results in PCB Editor crashing at launch7 V: L* H! K* u) p9 }) M! i8 N
1500659 FLOWS PROJMGR Need the ability to ensure that the standard library is not added to the project libraries list by default & `8 Y4 h* ? J- h* N7 N/ N% [1500725 F2B PACKAGERXL Unable to clear pstprop.dat file conflicts ) D1 p/ S) O ?! M1501139 ALLEGRO_EDITOR PADS_IN Pads_in creates pastemask for Through Hole padstacks 1 R# L$ s" l1 b3 V4 N! U$ }1501165 F2B DESIGNVARI TDO does not manage overlay files and variant_roz1040660_1.ba cannot be created unless variant_merged.dat is checked out & S; P8 H Q$ Q* j) P' \1501774 ALLEGRO_EDITOR OTHER PDF Publisher: If text is attached to an object, the object is also printed in the PDF . \2 P8 B) l0 `6 {7 M* e1 X8 D1501898 F2B DESIGNVARI Variant custom variables are visible in the schematic border but are not there in the Variant Details form# v# C3 G7 a7 Y y8 N2 x9 ^
1501974 F2B PACKAGERXL 'Feedback has found Illegal pin swap(s)' error although the pin was already swapped and fed back (B2F) to DE-HDL + T7 |% P9 _+ k; M, j1502782 ALLEGRO_EDITOR SCHEM_FTB Allegro System Architect (SCM) - Export Physical stops unexpectedly without any errors or warnings 3 [; G$ t) c1 B1503551 APD STREAM_IF In SPB166 Hotfix 60, error reported if a self-intersecting polygon outline exists at a specific location : f( T3 I! ?0 G' V* `' U6 O1504093 ASI_SI GUI View Topology and Waveform buttons overlap when Signal Analysis window is resized 1 Q+ O3 v+ c1 I7 m1504767 CONSTRAINT_MGR SCHEM_FTB Constraint Manager generates errors if the 'sNoF2BFlow' property is added to the Constraint Manager Dictionary ; }- r( V5 @7 w. E1505497 SIP_LAYOUT LOGIC Assign net fails to fully connect propagated items ' k+ }4 v6 p/ W1 M9 c: p1506110 ALLEGRO_EDITOR DRC_CONSTR No DRC shown when a text on etch layer is overlapped on mechanical pin + P1 u) H" Z6 K1 \& _9 ~ b; d2 Z ^3 X1506654 CONCEPT_HDL INTERFACE_DESIGN Netgroups broken when moving 5 r) b% W/ k% |0 U3 R4 H. X& Q$ W1506983 ALLEGRO_EDITOR SKILL axlBackDrill SKILL command crashes PCB Editor after backdrill analysis is run when App mode is set to None 3 e3 q3 o- d8 t6 x [ L$ q* _3 |3 l+ a$ P5 Z1 C2 k
DATE: 11-20-2015 HOTFIX VERSION: 061 8 H# ?9 ~$ p3 j+ U7 X=================================================================================================================================== ; r3 j/ n# x G5 ~7 w. A" ]' A2 h7 ]9 kCCRID PRODUCT PRODUCTLEVEL2 TITLE) L- p0 g5 E0 z8 p; z9 E1 S
=================================================================================================================================== g ^: D" H1 L" N/ s1306441 APD OTHER The Minimum Shape Area option in Layer Compare uses an unspecified value/ I' @8 _0 V/ [! E! z
1342644 ADW COMPONENT_BROWSE Need directive or method for Component Browser to load a search criteria file upon init 2 {" ^4 t" [) P! C+ T1413248 CONCEPT_HDL CORE Import from another TDO project makes the block read-only * Q: o2 l* U* D6 s1417429 ALLEGRO_EDITOR INTERACTIV Pick box only accepts 1 set of values. You need to close the box and reopen it to draw a rectangle + \; n0 v) h3 p$ t% F+ U' l1417442 ALLEGRO_EDITOR INTERACTIV Spin via stack and only part of the stack spins ' z2 P, H1 w7 x& _* j1 t3 s1451977 CONCEPT_HDL PDF Origin of PDF mediabox not starting at (0,0) when PDF page_height and page_width are set7 i; f! }9 w2 \7 h! s8 P
1453527 ALLEGRO_EDITOR EDIT_ETCH Contour route hugs the outer edge of the route keepin, l; j- a i% b- Y+ C# h
1464948 PCB_LIBRARIAN VERIFICATION The errors/warnings do not match between the various tools . S) R& F. t! Y* }2 I1467826 CONCEPT_HDL PDF PublishPDF from Console Window creates a long PDF filename 9 Z) U( }$ F7 y% F! U0 K" O1478639 CAPTURE OTHER Capture Browse Nets window does not display all nets9 O: Y4 N, M6 K9 c$ s
1479177 SIP_LAYOUT OTHER Pin pair constraints do not appear to be supported in Sip Layout XL; c8 S/ m. J& l* C7 o- f5 a2 J
1479227 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule flagging invalid voltage in hierarchy 8 `. g/ r: T% h5 V6 u1479454 CONCEPT_HDL OTHER DE-HDL issue: locked DIFF_PAIR property is editable : u" y9 e+ F' q$ [0 U0 Q5 t+ U1480293 CAPTURE PROJECT_MANAGER Capture hangs when searching for all nets * G h8 y' M' u9 t, O1483894 CONCEPT_HDL CORE Import Design hangs when pull-down arrow is clicked twice) r$ X$ {5 M" [: E4 f
1484781 CONCEPT_HDL CORE Three different Hierarchical Viewer issues 7 s" z: b& Y4 ~2 T. Y1485059 PCB_LIBRARIAN CORE Part Developer pin attributes are randomly marked as read-only9 e- q# }/ g6 }
1485960 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule is crashing the project 0 D5 N& B m( s0 K1486086 ALLEGRO_EDITOR ARTWORK Cannot generate artwork.8 W7 q: [2 t8 u9 n
1486834 CONSTRAINT_MGR OTHER Restore the Status column in cmDiffUtility ' m, f' j: U/ @' Z9 x3 ?1 H1487085 CONCEPT_HDL CONSTRAINT_MGR Import Physical with the Constraints only option reports problems 4 Y. k# c% o9 g! b6 M& q' O/ _1487197 ALLEGRO_EDITOR DRC_CONSTR Drill to Via DRCs are not being reported : G b& O% B7 }2 Z7 F2 w1487265 CONCEPT_HDL CORE Replace command in Windows mode shows incorrect behavior: g) t" B9 w A% q/ x
1487733 CONSTRAINT_MGR OTHER Running Export Physical - It takes over two hours to update the PCB Editor board8 o+ X+ `9 ~" b. x7 a3 m' H; e
1488758 CONCEPT_HDL CONSTRAINT_MGR CM_VALIDATION_ON_SAVE should be a hard stop on Constraint Manager2 n$ G/ P% e) \- \
1490299 SCM OTHER ASA does not update revision properly; h* ]% k2 Z' _! P* k
1490744 ALLEGRO_EDITOR SKILL axlChangeLine2Cline changes line to cline and places it on the TOP layer) g9 A' _' U5 i
1490924 F2B PACKAGERXL Save Design/Export Physical is resetting Via constraints 5 ~0 Q6 A9 f! M6 }1491351 ALLEGRO_EDITOR OTHER Create Detail for bond fingers on a custom layer not working # M2 s/ Y: I# m% i; R1492595 ALLEGRO_EDITOR MANUFACT Dimension character substitution help is wrong " i+ G$ H$ A# ]2 j1492777 ORBITIO ALLEGRO_SIP_IF OrbitIO import of customer mcm results in crash3 q% D f8 X; C6 p6 g8 f, f7 B
1492901 CONCEPT_HDL CORE Cannot instantiate a multi-sections symbol (> 10 versions) in Design Entry HDL : z9 J6 {2 Q- R) ^" X( K1 q1495621 ALLEGRO_EDITOR INTERFACES Oval pins are placed with wrong orientation in IPC2581& t A8 N: F. E, H9 U: E4 [
1497597 ALLEGRO_EDITOR DATABASE Show Element on pin shows wrong drill size 3 L$ c1 O# y; Q& N5 ~1497956 CONCEPT_HDL CORE ADW Library Flow test schematic generation crashes DE-HDL while saving the design when using customer adw_conf_root$ a R( C- q- w$ K
1498234 ALLEGRO_EDITOR ARTWORK PCB Editor fails to create artwork and no error is listed in the log file& V ?: X5 d3 A1 q) ` V. G/ I
1499363 CONCEPT_HDL CORE Custom attributes under variant management stopped working in Hotfix60作者: jacklee_47pn 时间: 2016-6-29 12:27
截至目前 071 版本，- _& @ @0 C l/ M# w# A
有關 CAPTURE 最後補丁到 061 版。/ U, U5 Q8 r, C$ J. p$ d
有關 PSPICE 最後補丁到 058 版。; m5 z' M9 Z; n9 L- @" ?
只用上面所說的二項軟件的朋友，不用追補丁到處跑。作者: hermes 时间: 2016-8-17 13:05
何处下载？作者: jacklee_47pn 时间: 2016-8-18 07:41
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Hotfix_SPB16.60.073_wint_1of1补丁 & H2 o4 y! l; }! ^% A+ i$ z & P3 t4 l0 z- c6 Q. r$ P; V# n2 y! P http://pan.baidu.com/s/1i5jStCx 9 p3 n- U: y, C& V% I1 ^作者: hermes 时间: 2016-8-22 09:13
已下载，谢谢!作者: jacklee_47pn 时间: 2016-9-2 06:37
新增 076-072 版的補丁內容 - N( X8 \* `6 ?& t' |7 T 9 k( t/ g5 F3 X; r 7 X4 H4 m' O9 V: B& yDATE: 08-25-2016 HOTFIX VERSION: 076 ( P$ `- b! f' G0 t: X0 h=================================================================================================================================== - V" I x! E* j' v# t( DCCRID PRODUCT PRODUCTLEVEL2 TITLE* ~. b7 F1 a! i3 _7 ^
=================================================================================================================================== + _7 ~& A) Q5 v; o2 K* o/ V) X4 r1614667 SIG_INTEGRITY SIMULATION Different results from Probe in SI Base and SigXp 8 Z$ u5 w! K& M1615601 GRE IFP_INTERACTIVE Delete Bundle then try to delete plan lines results in fatal error & M4 _7 m$ X. C6 L0 m S9 H8 O4 F1616540 SIP_LAYOUT DRC_CONSTRAINTS Same net DRC Line-to-Line reappearing after dyn shape update% Q @- G C( q
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DATE: 08-12-2016 HOTFIX VERSION: 075 : _( T; { i, V, n=================================================================================================================================== , S0 p# f1 \1 Q, `" N3 lCCRID PRODUCT PRODUCTLEVEL2 TITLE ; E B/ D. M0 F5 [; n' U/ b7 z===================================================================================================================================. T n1 X. `6 O& E
1461626 CONCEPT_HDL CREFER Cross-references shown to the same pin on different block instances though the signal names differ2 w9 z; x. x8 T+ s
1597000 CONCEPT_HDL INTERFACE_DESIGN Renaming NG does not work if >1 segments have NG names4 k4 E% w7 }+ ~, [* \
1602801 SIG_INTEGRITY OTHER Dielectric Warning message when opening SiP tool. : S* n* N2 G0 [1 k1 ^! ^1 _1606861 CONCEPT_HDL CORE Crash on Linux during Generate View $ ?; H$ }) k1 ~3 M3 L0 `) |0 L1608524 SIP_LAYOUT MANUFACTURING The Display Pin Text tool fails in the 16.6.073 version with a parseString error. d* c; q$ d% U9 _
1609922 CONCEPT_HDL INFRA Launching Model Assignment crashes DE-HDL when the temp/edbDump.txt is read-only # z3 z0 X6 V8 P& O9 }, w0 R2 @1612108 ALLEGRO_EDITOR OTHER Netlist Import is crashing with the .SAV message. ; z- o( N' X0 @. X' v% r7 I9 c# R2 x0 I1 p2 e# M
DATE: 07-22-2016 HOTFIX VERSION: 074$ @2 k! j0 o9 j
=================================================================================================================================== + ~* M( R }( w+ s* pCCRID PRODUCT PRODUCTLEVEL2 TITLE / g, ~$ @3 L" H& T4 Q2 ~" L===================================================================================================================================% @2 o. l" `7 Y1 H
1423889 ALLEGRO_EDITOR EDIT_ETCH AiDT gets poor routing result 6 d& e! S& O+ B% k9 o6 S7 J; Z1547356 ALLEGRO_EDITOR EDIT_ETCH Results variations from ISR S034 to S066 3 S2 u" P" e* h8 Z7 Q% ~6 ~- k1 ~' A1568912 RF_PCB BE_IFF_IMPORT Route keepouts can only be imported once # P W' S2 m: _/ t; R9 w1574676 ORBITIO ALLEGRO_SIP_IF sip->oio eco doesn't work properly p4 h2 `5 P/ a" }9 U1580744 F2B PACKAGERXL ERROR(SPCODD-114): Duplicate physical part name NETSHORT found e7 s0 G# x, G! M
1582628 ADW TDA When one user takes an update of physical object while the other user is still checking in the object, TDO crashes 3 }0 q( N9 _; u! s" y! d& V1584719 TDA CORE Caching errors coming for a board ref project while doing Block update$ s+ n# L1 p+ j# ~
1587157 CONCEPT_HDL CONSTRAINT_MGR pstprop.net reports conflicts on nets with VOLTAGE properties 8 B+ g3 C& }2 W" B; h1587498 CONCEPT_HDL INTERFACE_DESIGN Possibility to tap bus bits removed- W) w( _- K: A3 l
1588786 ALLEGRO_EDITOR OTHER strip_design reports "Design corrupted message"6 k0 z8 R: u+ Z# f2 G3 g% F
1589252 CONCEPT_HDL CORE Search options go to page origo not chosen component ! v3 S i8 E# o' Q+ M1590538 CONCEPT_HDL DOC Open Archive shows unclear behavior + i) \5 K+ u% r' ^2 ?1 R& s, L( L1590639 CONCEPT_HDL OTHER DEHDL crash when importing design$ ]$ ]' a/ }$ A/ s
1590651 CONCEPT_HDL INTERFACE_DESIGN DEHDL duplicate NetGroups created in Interface Browser and CM - z! ] x5 f! t/ B1594076 TDA CORE TDO is crashing on concurrent checkin when one of the user got blocks which are not modified ) j* C' J: k. f! f1594358 CONSTRAINT_MGR CONCEPT_HDL Enable hierarchical BOM fails for sub block with working variant view ( ?6 k5 a8 F& ^3 }- ~1596780 ALLEGRO_EDITOR SKILL PCB Editor crashes after doing SRM update and save: V) Y0 Y5 h& P5 ?
1597153 F2B DESIGNVARI ERROR SPCODD-53 in Variant Editor ) ?% [% @4 @$ q; Z! M1 O: u1597385 F2B DESIGNVARI Some 16.5 variant DNI parts are now appearing in 16.6 as X-OUT and some don't have X-OUT or DNI ( m# Q, n% a1 s2 _1597413 SIG_EXPLORER SIMULATION SigXp crashes when simulating with via that was added to canvas ' c9 F- s: I1 D, }1598629 F2B PACKAGERXL Export Physical crashes+ h! G a, P; r3 \) h
1599452 ALLEGRO_EDITOR ARTWORK Import Artwork, Mirror option does import pins or shapes.; s5 H& G/ `4 Z1 f
1599950 SCM OTHER Adding the GND net to parts/pins takes a long time.3 H% `! c+ I4 B; d1 B$ U- t
1600226 RF_PCB AUTO_PLACE Fail to auto-place RF group. ?; U+ k; |9 U/ \" x( H
1601281 ALLEGRO_EDITOR OTHER STEP model link gets corrupted with SKILL axlLoadSymbol' [( W) j. P. _8 ~" ~: Q/ Q
1601282 ALLEGRO_EDITOR OTHER Export Libraries will not export device files when there is a space in the folder name. e$ v% D" x! V! U4 t6 k, b
1602186 PCB_LIBRARIAN VERIFICATION con2con should work with PCB_Library_Manager license in 166 as 166 tools should work with 172 upgraded licenses( c8 S1 l1 }, _' q1 ^, \
1602514 PCB_LIBRARIAN METADATA References to some primitives is missing in block metadata causing TDA errors for missing parts after join project: K& s. M3 @+ `
1602823 SIP_LAYOUT WIREBOND SiP Crashed during Add Wire command8 p; s1 e T' y: M. i: j- [. V
1602955 ALLEGRO_EDITOR SHAPE Shape no DRC when there is a Route Keepout in base layer. 4 \7 f3 b, S( ^1604223 CONCEPT_HDL CORE ERROR: SPCOCD-553: Connectivity Server Error, _: v+ a# g: v7 a k
1605310 TDA CORE TDA is crashing sometimes in the Join Project wizard6 U/ K6 ]. K: h' c
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DATE: 06-24-2016 HOTFIX VERSION: 0734 \& X$ c- u) e9 f/ Y9 h
===================================================================================================================================5 e1 {* \" D$ G( H2 P. Q0 N- ?/ z
CCRID PRODUCT PRODUCTLEVEL2 TITLE$ H! y& m! \* J9 C! @
===================================================================================================================================) z9 W/ e9 k* R; ^- s" D
1570032 ALLEGRO_EDITOR GRAPHICS Issue with 3D View+ m* K9 c# I6 h0 h& o
1582103 ALLEGRO_EDITOR PADS_IN PADS Library Import creates additional filled shape not present in source data ! _3 W7 p( Z" e/ W& D, [1590954 ORBITIO ALLEGRO_SIP_IF import of brd file fails with "Undefined argument" error % C) j" C1 m; Y- O! l: h1591223 CONCEPT_HDL CORE Variant information does not display on lower level schematic3 n' G5 V+ q0 F( j* k. @
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DATE: 06-3-2016 HOTFIX VERSION: 072 ' ?; e% m0 e( R1 A' W' v. \' v=================================================================================================================================== 5 }& r6 g5 ^3 ]CCRID PRODUCT PRODUCTLEVEL2 TITLE( \ t f& }7 R3 u
=================================================================================================================================== , J6 ~4 h) y+ o p1 e, g1546151 CONCEPT_HDL CORE Add port, Genview, move pin on block - the pin name disappears F! G7 o! d0 R5 ?5 T, L
1566274 RF_PCB FE_IFF_IMPORT RF-PCB -> Import IFF crashes in DE-HDL% ~& K0 V2 R M* e. |) y" u
1573039 ALLEGRO_EDITOR INTERFACES IDX returns control to the general interface prematurely during an incremental IDX export4 R3 V5 @. ~$ t# ~
1573127 CONCEPT_HDL COPY_PROJECT copyproject creates incorrect view_pcb entry5 N5 m# K, z+ T
1577381 CONCEPT_HDL CORE ERROR(SPCOCN-2128): The NetGroup structure does not match the PortGroup structure' [$ s# l3 d* X, j' w5 X/ D, I6 [3 W
1580891 SCM REPORTS Dsreportgen crashes on different scenarios% } U" w$ f8 {3 A* d' q9 x
1582863 CONCEPT_HDL CORE Generate View creates non existent ports# B. D8 X* I5 u5 ~5 T* M
1584317 CONCEPT_HDL CORE When packager fails, no option to open pxl.log file from design sync window. ! R6 @7 G. `2 o3 X1 K: z8 D