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标题: SystemSI仿真时VTT报错 [打印本页]

作者: ares0260    时间: 2016-6-18 17:24
标题: SystemSI仿真时VTT报错
请教各位,在仿真ddr时有如图报错
  [# J0 F3 A9 q! ~% E4 t5 l( V3 b有劳各位指点一下!!!
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*** Messages reported by SPDSIM (build14.0.2.09101) ***1 [: c3 G5 l6 ?2 Y, {2 Z9 c! _
Warning 5160: ".ends rpacks  " is not supported in include file, ignored.; _+ ?2 K( ]9 B) Q; Z" e4 @
  Location: statement at line 4
$ V: L: L1 R" T; G$ `  Context: .inc 'D:\Cadence-SI\CHP4\T20160612\L1\TEST\DEMO\rpacks.sp'
8 x( \' x3 p- @Error 2178: In the value expression:
) D- D$ s0 b* j Undefined parameter name "vtt".8 _+ r# e4 w0 ^. x7 i* p+ A0 j

. N( M6 c! ]/ U& [5 ?4 ^; m- B  Location: statement at line 197  p$ x) j9 Q8 z' `
  Context: .end
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作者: Dandy_15    时间: 2016-10-11 09:00
VTT 没有定义,定义一下就可以了,




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