标题: Synthesiable High Performance SDRAM Contoller [打印本页] 作者: Haiting32451 时间: 2016-6-12 10:59 标题: Synthesiable High Performance SDRAM Contoller Synthesiable High Performance SDRAM Contoller8 a- k1 n# c* i2 ]6 d, e
3 _+ B, L4 { C V9 GSynthesiable High Performance SDRAM Contoller % l0 @; [* b& X4 Y0 mSynchronous DRAMs are available in speed grades above 100 MHz using LVTTL I/Os. The 1 t) ]- q$ B Y( y% _1 e+ K7 }& V2 |" ]Virtex? series of FPGAs and the Spartan?-II family of FPGAs have many features, such as, P( u5 t3 U* D5 n2 F* s
SelectI/O? resource and the Clock Delay Lock Loop, that make it easy to interface to high 2 V% W E$ l% ~5 ?& `speed Synchronous DRAMs. This application note describes the design and implementation of$ n5 B \* { ?. \
a synthesizable, parameterizable, flexible, auto-placed-and-routed synchronous DRAM 0 _' j1 ^' p: tcontroller in the Virtex FPGA family. The design can also be implemented with a Spartan-II / [) w1 I0 i# B4 M, k7 ]4 ndevice. A 32-bit wide data interface version can run up to 125 MHz when automatically placed( ^/ X! r. V7 U1 J# B$ V& l: x
and routed in a Virtex -6 speed grade device. Hand placed versions of the design can run even m. q1 |/ g* _ g# m; H* ]faster.
