标题: 这段文字如何理解呢？为何会进入亚稳态？ [打印本页] 作者: mengzhuhao 时间: 2007-12-18 21:19 标题: 这段文字如何理解呢？为何会进入亚稳态？ 这段文字如何理解呢？为何会进入亚稳态？ * K* [2 x" Q0 P. ]8 D/ i% A. [" M3 R. n7 ]2 f$ u
If the asynchronous reset is released at or near the active clock edge of a flip-flop, the output of the flip-flop could go metastable and thus the reset state of the ASIC could be lost.作者: mengzhuhao 时间: 2007-12-18 21:50
The biggest problem with asynchronous resets is that they are asynchronous, both at the2 v9 L+ \, \( u; P1 N% t6 U
assertion and at the de-assertion of the reset. The assertion is a non issue, the de-assertion is the & x3 z6 j' o; t" I r) yissue. If the asynchronous reset is released at or near the active clock edge of a flip-flop, the 5 v+ \0 s3 b) X$ M' B7 U- h# ooutput of the flip-flop could go metastable and thus the reset state of the ASIC could be lost.# Z0 V& m5 p/ h6 h% y8 h' E
Another problem that an asynchronous reset can have, depending on its source, is spurious resets ' ?2 ^( a4 d& y8 ldue to noise or glitches on the board or system reset. See section 8.0 for a possible solution to " o$ y( x; }8 k0 p) j+ `0 V7 Nreset glitches. If this is a real problem in a system, then one might think that using synchronous % p8 I4 G; m( Y, \: h" w6 @( x9 {* eresets is the solution. A different but similar problem exists for synchronous resets if these 1 E6 N( j# F& ?+ ]spurious reset pulses occur near a clock edge, the flip-flops can still go metastable (but this is4 |# k' h4 h& v* T" Y$ a
true of any data input that violates setup requirements).